CN110085587A - Three-dimensional longitudinal direction one-time programming memory - Google Patents
Three-dimensional longitudinal direction one-time programming memory Download PDFInfo
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- CN110085587A CN110085587A CN201810072197.8A CN201810072197A CN110085587A CN 110085587 A CN110085587 A CN 110085587A CN 201810072197 A CN201810072197 A CN 201810072197A CN 110085587 A CN110085587 A CN 110085587A
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- address wire
- otp
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- vertical
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
Abstract
The present invention proposes a kind of three-dimensional longitudinal one-time programming memory (3D-OTPV).It contains the horizontal address wire of multiple-level stack, multiple storage wells for penetrating horizontally location line, one layer of covering storage well abutment wall antifuse film, a plurality of vertical address wire being formed in storage well.In a read cycle, the information for all OTP storage member storage being electrically coupled with a wordline is read.
Description
Technical field
The present invention relates to integrated circuit memory fields, more precisely, being related to one-time programming memory (OTP).
Background technique
Three-dimensional one-time programming memory (3D-OTP) is a kind of monomer (monolithic) semiconductor memory, it contains more
The OTP of a vertical stacking stores member.The storage member of 3D-OTP is distributed in three dimensions, and the storage of traditional plane OTP
Member is distributed on two-dimensional surface.Relative to traditional OTP, the advantages such as 3D-OTP has storage density big, and carrying cost is low.In addition,
3D-OTP archival life is long (> 100 years), is suitble to permanent storing data.
United States Patent (USP) 5,835,396(inventor: state's hurricane；Grant date: on November 10th, 1998) disclose a kind of 3D-
OTP.3D-OTP chip contains a substrate and multiple OTP accumulation layers being stacked on substrate circuitry layer.Transistor on substrate and
Its interconnection line constitutes substrate circuitry (peripheral circuit including 3D-OTP).Each OTP accumulation layer contains a plurality of horizontal address wire (packet
Include wordline and bit line) and multiple OTP storage member.Each OTP accumulation layer contains multiple OTP arrays, and each OTP array is to share to have
The set of the OTP storage member of at least one address wire.Address wire and substrate circuitry are electrically coupled by contact access opening.
Since its address wire is all horizontal, the 3D-OTP referred to as transverse direction 3D-OTP(3D-OTPH).Work as 3D-OTPHDeposit
When storage capacity is more than 100Gb, address wire line width enters 1x nm, this is needed using high precision lithography (such as multiple exposure skill
Art), increase chip cost.Meanwhile with the increase of OTP storage number of layers, planarization will be more and more difficult.Therefore, 3D-OTPH
OTP storage number of layers be restricted.
Summary of the invention
The main object of the present invention is to provide a kind of cheap and highdensity three-dimensional one-time programming memory (3D-OTP).
It is another object of the present invention to manufacture 3D-OTP using lower accuracy photoetching technique.
It is another object of the present invention to increase the number of OTP accumulation layer.
It is another object of the present invention to guarantee the normal work of 3D-OTP in the case where OTP stores the biggish situation of first leakage current.
In order to realize that these and other purpose, the present invention propose a kind of three-dimensional longitudinal one-time programming memory (3D-
OTPV).It contains the OTP storage string of multiple side by side arrangement in substrate circuitry, each OTP storage string vertically with substrate and contain
The OTP of multiple vertical stackings stores member.Particularly, 3D-OTPVHorizontal address wire (wordline) containing a plurality of vertical stacking.?
After etching multiple storage wells for penetrating these horizontal address wires, one layer of antifuse film is covered in the abutment wall of storage well, and fill
Conductor material is to form vertical address wire (bit line).Conductor material can be the semiconductor material of metal material or doping.OTP is deposited
Chu Yuan is formed in the infall of wordline and bit line.
Each OTP storage member contains an antifuse and a diode, and antifuse contains an antifuse film.Antifuse film is exactly
One layer of insulating film (such as silica, silicon nitride), it is irreversibly changed into low resistance state from high-resistance state in programming.For
Multidigit member 3D-OTPV(i.e. each OTP storage member storage n > 1 information), each OTP storage member > 1 data of storage, it has N
> 2 kinds of states.The program current that the OTP storage member of different conditions uses is different, and therefore, they have different resistance.Diode contains
Have conductive membrane surely, it has following generalized character: when the numerical value of applied voltage be less than the direction of read voltage or applied voltage with
When read voltage is opposite, resistance is much larger than its resistance (reading resistance) under read voltage.
In OTP storage member, the cathode size of diode is only the radius of storage well.It is difficult to press since the size is too small
The leakage current of diode processed, 3D-OTPVThe leakage current of middle OTP storage member is higher than 3D-OTPH.In order to solve this problem, of the invention
It is proposed a kind of " full-time course " mode.Full-time course mode refers to: reading all OTP being electrically coupled with a wordline in a read cycle and deposits
The information of Chu Yuan storage.Read cycle is in two stages: pre-charging stage and read phase.Own in pre-charging stage, OTP array
Address wire (including all wordline and all bit lines) is precharged to a predeterminated voltage.In read phase, when in a selected word line
Voltage rise to read voltage VRAfterwards, it is charged by OTP storage member coupled thereto to all bit lines.By on measurement bit line
Voltage change, it may be determined that the information that corresponding OTP storage member is stored.
Correspondingly, the present invention proposes a kind of three-dimensional longitudinal one-time programming memory (3D-OTPV), it is characterised in that contain:
One contains the semiconductor substrate (0) of a substrate circuitry (0K)；One is located at the OTP storage string (1A) in the substrate circuitry (0K), should
OTP storage string (1A) stores member (1aa- containing multiple OTP for being mutually perpendicular to stack and be electrically coupled with a vertical address wire (4a)
1ha)；Each OTP stores first (1aa) and contains one layer of antifuse film (6a), and in programming, the antifuse film (6a) is from high-resistance state
Irreversibly it is changed into low resistance state.
The present invention also proposes a kind of 3D-OTPV, it is further characterized in that containing: one contains the semiconductor of a substrate circuitry (0K)
Substrate (0)；Multilayer is on the substrate circuitry (0K) and is mutually perpendicular to the horizontal address wire (8a-8h) stacked；At least one wears
The storage well (2a) of the saturating multiple-layer horizontal address wire (8a-8h)；One layer of antifuse film for covering storage well (2a) abutment wall
(6a), in programming, the antifuse film (6a) is irreversibly changed into low resistance state from high-resistance state；One by storage
Well (2a) fills a conductive material and the vertical address wire (4a) that is formed；It is multiple to be formed in the horizontal address wire (8a-8h) and be somebody's turn to do
The OTP of vertical address wire (4a) infall stores first (1aa-1ha).
Detailed description of the invention
Figure 1A is the first 3D-OTPVZ-x sectional view；Figure 1B is its x-y sectional view along AA '.
Fig. 2A-Fig. 2 C is the 3D-OTPVThe sectional view of three processing steps.
Fig. 3 A is second of 3D-OTPVZ-x sectional view；Fig. 3 B is its x-y sectional view along BB '.
Fig. 4 A indicates the symbol and its meaning of OTP storage member；Fig. 4 B is the electricity for the reading circuit that the first OTP array uses
Lu Tu；Fig. 4 C is its timing diagram；Fig. 4 D is a kind of I-V curve of quasi- conductive membrane.
Fig. 5 A is the third 3D-OTPVZ-x sectional view；Fig. 5 B is its x-y sectional view along CC '；Fig. 5 C is second
The circuit diagram for the reading circuit that OTP array uses.
Fig. 6 is a kind of multidigit member 3D-OTPVX-y sectional view.
It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar
Structure."/" indicates the relationship of "and" or "or"." in substrate " refers to that function element is respectively formed (including substrate table in the substrate
On face), and interconnection line be formed in above substrate, not with substrate contact." on substrate " refer to function element be formed in above substrate,
Not with substrate contact.
Specific embodiment
Figure 1A is a kind of three-dimensional longitudinal one-time programming memory (3D-OTPV) z-x sectional view.It contains multiple positioned at lining
On the circuit 0K of bottom and vertical OTP storage string (referred to as OTP storage string) 1A, 1B ... of side by side arrangement.Each OTP storage string 1A
Vertical with substrate 0, it contains the OTP storage member 1aa-1ha of multiple vertical stackings.
Embodiment in this figure is an OTP array 10.OTP array 10 is all shared storages for having at least one address wire
The set of member.It contains horizontal address wire (wordline) 8a-8h of a plurality of vertical stacking.Multiple these are penetrated horizontally etching
After the storage well 2a-2d of location line 8a-8h, one layer of antifuse film 6a-6d is covered in the abutment wall of storage well 2a-2d, and fill conductor
Material is to form vertical address wire 4a-4d(bit line).Conductor material can be the semiconductor material of metal material or doping.
OTP storage member 1aa-1ha is formed in the infall of wordline 8a-8h Yu bit line 4a.It is anti-molten in OTP storage member 1aa
Cortina 6a is one layer of dielectric insulating film.It has high resistance when unprogrammed；Conductor silk is formed when programming wherein
(conductive filament) 11, therefore its resistance is irreversibly changed into low resistance.For simplicity meter, Figure 1A only draws and deposits
The conductor silk for storing up the conductor silk in member 1aa, and being not drawn into other storage members.
Figure 1B is the 3D-OTPVAlong the x-y sectional view of AA '.Horizontal address wire 8a be a conductor plate, it can with two rows or
Vertical address wires more than two rows (is herein eight vertical address wire 4a-4h) coupling, stores member 1aa- to form eight OTP
1ah.These OTP storage member (all OTP storage member being electrically coupled with a horizontal address wire 8a) 1aa-1ah constitutes an OTP and deposits
Storage group 1a.Since horizontal address wire 8a is very wide, it can use low accurate lithographic technology (such as characteristic line breadth > 60 nm photoetching skill
Art) it is formed.
Fig. 2A-Fig. 2 C indicates 3D-OTPVThree processing steps.All horizontal address layer 12a-12h are formed continuously (figure
2A).Particularly, after by substrate circuitry 0K planarization, first level conductor layer 12a is formed.This horizontal conductor layer 12a is not
Contain any figure.The first insulating layer 5a is formed on first level conductor layer 12a.Similarly, the first insulating layer 5a is not yet
Contain any figure.The second horizontal conductor layer 12b is re-formed on the first insulating layer 5a.So analogize, it is all until being formed
Horizontal conductor layer (totally eight layers herein).In the forming process of Fig. 2A, without image conversion step (such as lithography step).Due to every
The planarization of a horizontal conductor layer keeps good, 3D-OTPVTens of a horizontal conductor layers up to a hundred can be contained, far more than 3D-
OTPH.After foring all horizontal conductor layer 12a-12h, all horizontal conductor layers are disposably etched by the first etching
12a-12h is to form horizontal address wire 8a-8h(Fig. 2 B of a plurality of vertical stacking).Later, pass through the second disposable landform of etching
At multiple storage well 2a-2d(Fig. 2 C for penetrating all horizontal address wire 8a-8h).Antifuse film 6a-6d is covered on its side wall,
And conductor material is filled, to form a plurality of vertical address wire 4a-4d.
Fig. 3 A is second of 3D-OTPV10 z-x sectional view；Fig. 3 B is its x-y sectional view along BB '.It and Figure 1A-
Embodiment is similar in Figure 1B, and unique difference is also to contain one layer of quasi- conductive membrane 16a-16d in storage well 2a-2d.Quasi- conductive membrane is
The main composition part of diode, it has following broad aspects: when the numerical value of applied voltage is less than read voltage or applied voltage
Direction it is opposite with read voltage when, the resistance of quasi- conductive membrane is much larger than its resistance under read voltage.Quasi- conductive membrane 16a-16d can
To be one layer of ceramic membrane (such as metal oxide).In the present embodiment, quasi- conductive membrane 16a-16d is located at the side storage well 2a-2d
Between wall and antifuse film 6a-6d；In other embodiments, antifuse film 6a-6d can be located at storage well 2a-2d side wall and standard is led
Between logical film 16a-16d.
Group 4A is the symbol of OTP storage member 1.It indicates that OTP storage member 1 contains antifuse 12 and diode 14.Antifuse
12 contain an antifuse film 6a-6d.Antifuse film is exactly one layer of insulating film (such as silica, silicon nitride), it is in programming Shi Conggao
Resistance states are irreversibly changed into low resistance state.For diode 14 containing conductive membrane 16a-16d surely, it has following broad sense special
Sign: when the numerical value of applied voltage be less than read voltage or it is contrary when, resistance much larger than under read voltage resistance (read electricity
Resistance).
The example of diode 14 includes semiconductor diode, Schottky diode etc. and ceramic diode etc..For partly leading
Body diode, horizontal address wire 8a-8h contains p-type semiconductor material, vertical address wire 4a-4d contains N-type semiconductor；For Xiao
Special based diode, horizontal address wire 8a-8h contain metal material, and vertical address wire 4a-4d contains semiconductor material；For ceramics
Diode contains at least one layer of ceramic membrane (such as metal oxide) between horizontal address wire 8a-8h and vertical address wire 4a-4d.
In OTP storage member, the cathode size of diode is only the radius of storage well.It is difficult to press since the size is too small
The leakage current of diode processed, 3D-OTPVThe leakage current of middle OTP storage member is higher than 3D-OTPH.In order to solve this problem, of the invention
It is proposed a kind of " full-time course " mode.Full-time course mode refers to: reading all OTP being electrically coupled with a wordline in a read cycle and deposits
The information of Chu Yuan storage.
Fig. 4 B indicates the reading circuit that the first OTP array 10 uses.It uses full-time course mode.Under the context of circuit,
Horizontal address wire 8a-8h is wordline, and vertical address wire 4a-4h is bit line.OTP array 10 containing wordline 8a-8h, bit line 4a-4h,
And storage member 1aa-1ad....The peripheral circuit of OTP array 10 contains multiplexer (MUX) 40 and one and reads amplification
Device 30.In this embodiment, MUX 40 is 4-to-1 MUX.
Fig. 4 C is its timing diagram.Read cycle T contains a pre-charging stage tpreWith a read phase tR: in precharge tpreRank
Section, all address wires (8a-8h, 4a-4h) are all charged to a predeterminated voltage (input of such as amplifying circuit 30 are inclined in storage array 16
Set voltage Vi).In read phase tR, all bit line 4a-4h suspend, and the voltage of selected wordline 8a rises to read voltage VR, and pass through
OTP storage member 1aa-1ah charges to all bit line 4a-4h.Voltage on every bit line is sent to reading amplification by MUX 40 respectively
Device 30.If the voltage is greater than the turnover voltage V of sense amplifier 30T, then V is exportedOOverturning.At the end of read cycle T, storage
The digital information of all storage member 1aa-1ah storages is read in group 1a.
Fig. 4 D is a kind of I-V curve of quasi- conductive membrane.Due to the threshold voltage V of sense amplifier 30tSmaller (~ 0.1V),
Voltage change on all bit line 4a-4h of read phase is smaller, the selected backward voltage stored on first (such as 1ca) about-
Vt.As long as the I-V characteristic of quasi- conductive membrane meets I (VR)>>I(-VT), even if there is biggish leakage current, 3D-OTP will not be influencedV
Normal work.
For convenience of address decoding, the present invention also forms multiple vertical transistors using the side wall of storage well.Fig. 5 A- Fig. 5 C table
Show the third 3D-OTPV..It contains vertical transistor 3aa-3ad.Wherein, vertical transistor 3aa is a transmission transistor (pass
Transistor), it contains grid 7a, gate medium 6a and channel 9a(Fig. 5 A).Channel 9a is by being filled in storage well 2a
Semiconductor material is constituted, and doping can be identical as vertical address wire 4a, thin or opposite.Grid 7a encirclement storage well 2a,
2e, and control transmission transistor 3aa, 3ae(Fig. 5 B)；Grid 7b is surrounded storage well 2b, 2f, and controls transmission transistor
3ab,3af；Grid 7c surrounds storage well 2c, 2g, and controls transmission transistor 3ac, 3ag；Grid 7d surrounds storage well 2d, 2h,
And control transmission transistor 3ad, 3ah.Transmission transistor 3aa-3ah forms an at least decoder stage (Fig. 5 C).In one embodiment,
When the voltage on grid 7a is height, and the voltage on grid 7b-7d is low, only transmission transistor 3aa and 3ae conducting is other
Transmission transistor disconnects.At this moment, the MUX 40` in substrate circuitry layer selects a signal in bit line 4a and 4e, send to reading
Amplifier 30 out.By forming multiple vertical transistor 3aa-3ad in storage well 2a-2d, the present invention can simplify decoder
Design.
Fig. 6 indicates a kind of multidigit member longitudinal direction 3D-OTPV .It contains multiple OTP storage member 1aa-1ah.In this embodiment,
OTP stores member 1aa-1ah tool, and there are four types of states: ' 0 ', and ' 1 ', ' 2 ', ' 3 ', the OTP storage member 1aa-1ah of different conditions is adopted
Program current is different, and therefore, they have different resistance.Wherein, storage member 1ac, 1ae, 1ah is state ' 0 ', it is not compiled
Journey, antifuse film 6c, 6e, 6h are complete.Other storage members have programmed.Wherein, storage member 1ab, 1ag is state ' 1 ',
Conductor silk 11b is most thin, and resistance has programmed maximum in antifuse film all；Storage member 1aa is state ' 3 ', and conductor silk 11d is most
Slightly, resistance has programmed minimum in antifuse film all；Storing member 1ad, 1af is state ' 2 ', and the size of conductor silk 11c is situated between
Between conductor silk 11b and 11d, resistance also falls between.
It should be appreciated that under the premise of not far from the spirit and scope of the present invention, it can be to form and details of the invention
It is modified, this does not interfere them using spirit of the invention.Therefore, in addition to the spirit according to appended claims,
The present invention should not be any way limited.
Claims (10)
1. a kind of three-dimensional longitudinal one-time programming memory (3D-OTPV), it is further characterized in that containing:
One contains the semiconductor substrate (0) of a substrate circuitry (0K)；
Multilayer is on the substrate circuitry (0K) and the horizontal address wire (8a-8h) of vertical stacking；
Multiple storage wells (2a) for penetrating the multiple-layer horizontal address wire (8a-8h)；
One layer of antifuse film (6a) for covering storage well (2a) abutment wall, in programming the antifuse film (6a) from high-resistance state not
Reversibly it is changed into low resistance state；
The a plurality of vertical address wire (4a) in storage well (2a)；
Multiple OTP storage member (1aa- for being formed in the horizontal address wire (8a-8h) and vertical address wire (4a) infall
1ha)；
In a read cycle (T), the information of first (1aa-1ah) storage is stored with all OTP that a horizontal address wire is electrically coupled
It is read, the horizontal address wire is a wordline.
2. a kind of three-dimensional longitudinal one-time programming memory (3D-OTPV), it is further characterized in that containing:
One contains the semiconductor substrate (0) of a substrate circuitry (0K)；
Multilayer is on the substrate circuitry (0K) and the horizontal address wire (8a-8h) of vertical stacking；
Multiple storage wells (2a) for penetrating the multiple-layer horizontal address wire (8a-8h)；
One layer of antifuse film (6a) for covering storage well (2a) abutment wall, in programming the antifuse film (6a) from high-resistance state not
Reversibly it is changed into low resistance state；
The a plurality of vertical address wire (4a) in storage well (2a)；
Multiple OTP storage member (1aa- for being formed in the horizontal address wire (8a-8h) and vertical address wire (4a) infall
1ha)；
In a read cycle (T), the information of first (1aa-1ah) storage is stored with all OTP that a vertical address wire is electrically coupled
It is read, the vertical address wire is a wordline.
3. memory according to claims 1 and 2, it is further characterized in that: the read cycle contains a pre-charging stage,
The pre-charging stage is precharged to same predeterminated voltage with all bit lines that the wordline is electrically coupled.
4. memory according to claims 1 and 2, it is further characterized in that: the read cycle contains a read phase, described
The value of read phase, the voltage change for all bit lines being electrically coupled with the wordline is much smaller than read voltage.
5. memory according to claims 1 and 2, it is further characterized in that: the storage well (2a) is without containing individually quasi-
Conductive membrane.
6. memory according to claims 1 and 2, it is further characterized in that: the storage well (2a) contains conductive membrane surely
(16a)。
7. memory according to claims 1 and 2, it is further characterized in that: the horizontal address wire (8a-8h) contains a metal
Material, semiconductor material of the vertical address wire (4a) containing a doping.
8. memory according to claims 1 and 2, it is further characterized in that: the horizontal address wire (8a-8h) contains a doping
Semiconductor material, the vertical address wire (4a) contain an at least counter-doping semiconductor material.
9. memory according to claims 1 and 2, it is further characterized in that: the storage member (1aa- in the storage well (2a)
A vertical storage string (1A) 1ha) is constituted, the vertical storage string (1A) is electrically coupled with a vertical transistor (7a).
10. memory according to claims 1 and 2, it is further characterized in that: each storage member has N(N > 2) kind shape
State (11b-11d), the antifuse film under different conditions have different resistance.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810072197.8A CN110085587A (en) | 2018-01-25 | 2018-01-25 | Three-dimensional longitudinal direction one-time programming memory |
| US15/947,852 US10559574B2 (en) | 2016-04-16 | 2018-04-08 | Three-dimensional vertical one-time-programmable memory comprising Schottky diodes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810072197.8A CN110085587A (en) | 2018-01-25 | 2018-01-25 | Three-dimensional longitudinal direction one-time programming memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110085587A true CN110085587A (en) | 2019-08-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810072197.8A Pending CN110085587A (en) | 2016-04-16 | 2018-01-25 | Three-dimensional longitudinal direction one-time programming memory |
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| Country | Link |
|---|---|
| CN (1) | CN110085587A (en) |
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2018
- 2018-01-25 CN CN201810072197.8A patent/CN110085587A/en active Pending
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Application publication date: 20190802 |