CN110071078A - Flat no-lead packages body - Google Patents
Flat no-lead packages body Download PDFInfo
- Publication number
- CN110071078A CN110071078A CN201910327120.5A CN201910327120A CN110071078A CN 110071078 A CN110071078 A CN 110071078A CN 201910327120 A CN201910327120 A CN 201910327120A CN 110071078 A CN110071078 A CN 110071078A
- Authority
- CN
- China
- Prior art keywords
- flat
- chip
- pin
- lead
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The present invention relates to flat no-lead packages bodies.An embodiment according to the present invention, a flat no-lead packages body have the first opposite side and second side, include: a chip, one covers the injection-moulded housing and several pins for being respectively in first side and second side of the chip.Each of several pins include to be shielded in the intracorporal interior lead portion of the injection moulded shell and bottom surface exposes to the outer pin portion outside the injection-moulded housing, the interior lead portion of at least the two has different planar dimensions in several pins, which does not pass through pedestal and be at least directly mounted at wherein in one of lead portion in larger size.The design of symmetrical pin is changed to asymmetrical by the present invention, to still ensure that it obtains enough supports of pin in the case where chip is without pedestal and biasing, does not have obvious hanging.On the one hand it ensure that the quality of packaging body, while also avoiding the limitation of pedestal technique.
Description
The application be on August 22nd, 2014 the applying date, application No. is " 201410417894.4 ", and entitled
The divisional application of the application of " flat no-lead packages body ".
Technical field
The present invention relates to integrated circuit package bodies, especially flat no-lead packages body (QFN, Quad Flat No-
lead Package)。
Background technique
Typical integrated circuit package body is usually to pass through pedestal chip is connected on pin.It is sealed with flat non-pin
For filling body, it chip notacoria or gum technique can be used to be mounted on the base chip, then make chip using routing technique
It is connected with corresponding pin.
However as the development of electronic technology, the size of industry expectation chip is smaller and smaller to adapt to becoming for product miniaturization
Gesture.This is just that the encapsulation of integrated circuit proposes new problem, main reason is that existing footmaker's skill is difficult to meet
The demand of this miniaturization.Therefore, existing packaging technology need to be further improved the package requirements that can meet small-size chips.
Summary of the invention
One of the embodiment of the present invention is designed to provide an integrated circuit package body, especially flat no-lead packages
Body installs chip without using pedestal, to avoid the technique limitation of pedestal but not influence integrated circuit package body
Performance.
One embodiment of the invention provides a flat no-lead packages body, has the first opposite side and second side.This is flat
Flat leadless packages body includes: a chip, the injection-moulded housing of the masking chip and several is respectively in first side and second side
Pin.Each of several pins include to be shielded in the intracorporal interior lead portion of the injection moulded shell and bottom surface exposes to the injection molding
Outer pin portion outside shell, the interior lead portion in several pins both at least have different planar dimensions, which does not pass through
Pedestal, which is at least directly mounted at wherein, to be had in larger size in one of lead portion.
According to another embodiment of the present invention, in one embodiment, the size of the flat no-lead packages body be less than 2mm ×
2mm.The chip be relative to several pins horizontal extension direction rotate an angle place.The chip is flat not at this
The center of leadless packages body.The outer pin portion size of each of several pins is identical.Several pins it is interior
Lead portion is half-etching structure.It is both at least opposite comprising being located at two of first side and second side in several pins
Pin.The spacing of this two opposite pins is not less than 0.07mm.The chip is only installed on one in first side and second side
On the pin of person.In another embodiment, which is installed on all several pins.
The design of symmetrical pin is changed to asymmetric by flat no-lead packages body of the invention compared to traditional structure
, to still ensure that it obtains enough supports of pin in the case where chip is without pedestal and biasing, do not have obvious hanging.
On the one hand it ensure that the quality of packaging body, while also avoiding the limitation of pedestal technique.
Detailed description of the invention
It is the structural profile illustration of integrated circuit package body according to an embodiment of the invention shown in Fig. 1.
It is the present invention looks up structural representation of integrated circuit package body in Fig. 1 shown in Fig. 2, illustrates only wherein chip for the sake of simple
And the layout of pin.
It is the present invention looks up structural representation of integrated circuit package body according to another embodiment of the present invention shown in Fig. 3, it is simple to rise
See the layout for illustrating only wherein chip and pin.
It is the present invention looks up structural representation of the integrated circuit package body of another embodiment according to the present invention shown in Fig. 4, it is simple to rise
See the layout for illustrating only wherein chip and pin.
It is the present invention looks up structural representation of the integrated circuit package body of other embodiments according to the present invention shown in Fig. 5, simply
For the sake of illustrate only the layout of wherein chip and pin.
Specific embodiment
Spirit for a better understanding of the present invention makees furtherly it below in conjunction with part preferred embodiment of the invention
It is bright.
For the small size such as less than chip of 2mm × 2mm, it is limited to existing pedestal technique, no pedestal can be used
Packaged type.That is, chip is directly installed on pin.But due to the multifactor consideration of design, chip can not be in sometimes
The center of entire packaging body but side can be partial to.In this way, may go out according to the symmetric arrays pin that traditional design rule designs
A case where existing column pin can not all touch chip, it is hanging that corresponding chip will appear large area.Since chip large area is outstanding
Sky, in routing operation, since chip bearing is unstable and cause can not routing.
The embodiment of the present invention can avoid above-mentioned technical problem.An embodiment according to the present invention, flat non-pin envelope
Fill body, have the first opposite side and second side, include: one chip, one covers the injection-moulded housing of the chip, and is respectively in this
Several pins of the first side and second side.Wherein each of several pins include be shielded in the injection moulded shell it is intracorporal in draw
Foot and bottom surface expose to the outer pin portion outside the injection-moulded housing, there is different the interior lead portion of at least the two in several pins
Planar dimension, the chip do not pass through pedestal and are at least directly mounted at wherein in one of lead portion in larger size.
It is the structural profile illustration of integrated circuit package body 10 according to an embodiment of the invention shown in Fig. 1.
It is the present invention looks up structural representation of integrated circuit package body 10 in Fig. 1 shown in Fig. 2, illustrates only its core for the sake of simple
The layout of piece 12 and pin 14.
In conjunction with shown in Fig. 1,2, which is a flat no-lead packages body, includes chip 12, masking
The injection-moulded housing 16 of the chip 12 and four pins 14.The flat no-lead packages body 10 has opposite the first side 100 and the
Two sides 102.Four pins 14 are located at the first side 100 and second side 102 of the chip 12.Each pin 14 includes to be shielded in
Interior lead portion 140 and bottom surface in injection-moulded housing 16 expose to the outer pin portion 142 outside the injection-moulded housing 16.The interior lead portion
140 have relatively thin thickness relative to outer pin portion 142, and interior lead portion 140 can be formed by etch process, i.e., interior lead portion
140 be half-etching structure, and in encapsulation process, interior lead portion 140 will be completely enclosed in mould-injection body, and outer pin
The bottom surface in portion 142 exposes the bottom surface of integrated circuit package body 10.Pin 14 is used to support the chip 12 and passes through electric connection line
It is electrically connected with the chip 12 realization.In the present embodiment, although the outer pin portion 142 of four pins 14 have identical size (
In other embodiments, outer pin portion 142 may also have different sizes), but interior lead portion 140 is not fully identical, is located at phase
There are a longer interior lead portion 140 and a shorter interior lead portion 140 respectively to a pair of of respective pins 14 of two sides.This is two opposite
The spacing of pin is not less than 0.07mm, preferably desirable 0.1mm.In the present embodiment, the pin 14 with longer interior lead portion 140
It is interspersed in the first side 100 and second side 102.The chip 12 not at integrated circuit package body 10 center, but not
It is directly mounted on two pins 14 with longer interior lead portion 140 by pedestal, and be offset to side (to be in the present embodiment
Second side) have on the pin 14 of shorter interior lead portion 140.It so can guarantee, most of area of chip 12 all can be with pin
14 contacts, without the obvious overhanging portion at edge, and then in routing operation, chip 12 is not in downward deformation.
It is the present invention looks up structural representation of integrated circuit package body 10 according to another embodiment of the present invention shown in Fig. 3, simply
For the sake of illustrate only the layout of wherein chip 12 and pin 14.
Similar to embodiment illustrated in fig. 2, which is that there are four the flat non-pins of pin 14 for a tool
Packaging body.The interior lead portion 140 of four pins 14 is not fully identical, and a pair of of respective pins 14 positioned at opposite sides are distinguished
There are a longer interior lead portion 140 and a shorter interior lead portion 140.In the present embodiment, drawing with longer interior lead portion 140
Foot 14 is interspersed in the first side 100 and second side 102.Unlike, which is the water relative to four pins 14
Flat extending direction rotates an angle and places to contact with the interior lead portion 140 of four pins 14, avoids obvious hanging
Marginal portion.
It is the present invention looks up structural representation of the integrated circuit package body 10 of another embodiment according to the present invention shown in Fig. 4, simply
For the sake of illustrate only the layout of wherein chip 12 and pin 14.
As shown in figure 4, the integrated circuit package body 10 is a tool there are six the flat no-lead packages body of pin 14, respectively draw
Foot 14 be respectively in the integrated circuit package body 10 the first side 100 and opposite second side 102.The interior pin of six pins 14
Portion 140 is not fully identical, positioned at a pair of of respective pins 14 of opposite sides have respectively a longer interior lead portion 140 and one compared with
Short interior lead portion 140, and the pin 14 with longer interior lead portion 140 is respectively positioned on the first side 100.The chip 12 is offset to
Two sides 102 are placed, thus can be contacted shorter interior lead portion 140 and longer interior lead portion 140 simultaneously and be obtained enough supports.
It is the present invention looks up structural representation of the integrated circuit package body 10 of another embodiment according to the present invention shown in Fig. 5, simply
For the sake of illustrate only the layout of wherein chip 12 and pin 14.
As shown in figure 5, the integrated circuit package body 10 is a flat no-lead packages body with eight pins 14, respectively draw
Foot 14 be respectively in the integrated circuit package body 10 the first side 100 and opposite second side 102.The interior pin of eight pins 14
Portion 140 is not fully identical, positioned at a pair of of respective pins 14 of opposite sides have respectively a longer interior lead portion 140 and one compared with
Short interior lead portion 140.Pin 14 with longer interior lead portion 140 can be located at the first side 100 or second side 102, and each
There can be different dimension combinations to opposite pin 14 and be not limited to regular arrangement.The chip 12 can be offset to any side and put
It sets, equally can avoid apparent Hanging sectionally and obtain enough supports.
The essence of above-described embodiment only to illustrate the invention, those skilled in the art should appreciate that specific number of pins and row
Cloth can have many variations, and be not limited to listed above.And two pairs of two rows of pins 14 setting can be extended to four row's pins
14 integrated circuit package body 10, in addition two rows of terminals are applicable in the design rule of above-mentioned two rows completely.
Opposite two rows of pins 14 by being improved to relatively by the present invention by the identical symmetric design of interior lead portion 140
At least two corresponding pins 14 of side have different planar dimensions, as one is longer or wider and another one is shorter or relatively narrow；
Or have multiple pins that there is longer interior lead portion 140, and also have between multiple longer interior lead portion 140 different
Size (length or width).As long as can make chip 12 that the support of most of pins 14 can be obtained and avoid apparent hanging part
?.
Technology contents and technical characterstic of the invention have revealed that as above, however those skilled in the art still may base
Make various replacements and modification without departing substantially from spirit of that invention in teachings of the present invention and announcement.Therefore, protection model of the invention
The revealed content of embodiment should be not limited to by enclosing, and should include various without departing substantially from replacement and modification of the invention, and be this patent
Application claims are covered.
Claims (10)
1. a kind of flat no-lead packages body has the first opposite side and second side；Include:
One chip；
One injection-moulded housing covers the chip；
Several pins are respectively in first side and the second side；
Wherein each of several pins include to be shielded in the intracorporal interior lead portion of the injection moulded shell and bottom surface exposes to the note
The external outer pin portion of plastic housing, the interior lead portion in several pins both at least have different planar dimensions, and the chip is obstructed
Pedestal is crossed at least while to be directly mounted at the pin of lead portion in larger planar dimension and have compared in facet size
On the pin of lead portion.
2. flat no-lead packages body as described in claim 1, size is less than 2mm × 2mm.
3. flat no-lead packages body as described in claim 1, wherein the chip is prolonged relative to the levels of several pins
It stretches direction and rotates angle placement.
4. flat no-lead packages body as described in claim 1, wherein the chip is not at the flat no-lead packages body
Center.
5. flat no-lead packages body as described in claim 1, the wherein outer pin portion ruler of each of several pins
It is very little identical.
6. flat no-lead packages body as described in claim 1, wherein the interior lead portion of several pins is half-etching structure.
7. flat no-lead packages body as described in claim 1, wherein at least the two includes to be located in several pins
Two opposite pins of first side and second side.
8. flat no-lead packages body as claimed in claim 7, wherein the spacing of this two opposite pins is not less than 0.07mm.
9. flat no-lead packages body as described in claim 1, wherein the chip is only installed on positioned at first side and second
In side on the pin of one.
10. flat no-lead packages body as described in claim 1, wherein the chip is installed on all several pins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910327120.5A CN110071078A (en) | 2014-08-22 | 2014-08-22 | Flat no-lead packages body |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910327120.5A CN110071078A (en) | 2014-08-22 | 2014-08-22 | Flat no-lead packages body |
| CN201410417894.4A CN104157620A (en) | 2014-08-22 | 2014-08-22 | Flat pin-free packaging body |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410417894.4A Division CN104157620A (en) | 2014-08-22 | 2014-08-22 | Flat pin-free packaging body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110071078A true CN110071078A (en) | 2019-07-30 |
Family
ID=51883093
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410417894.4A Pending CN104157620A (en) | 2014-08-22 | 2014-08-22 | Flat pin-free packaging body |
| CN201910327120.5A Pending CN110071078A (en) | 2014-08-22 | 2014-08-22 | Flat no-lead packages body |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410417894.4A Pending CN104157620A (en) | 2014-08-22 | 2014-08-22 | Flat pin-free packaging body |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN104157620A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1630945A (en) * | 2000-12-14 | 2005-06-22 | 国际整流器公司 | Semiconductor device package and lead frame with die overhanging lead frame pad |
| CN201417765Y (en) * | 2009-04-01 | 2010-03-03 | 苏州固锝电子股份有限公司 | Base island free semi-conductor chip package structure |
| CN201838575U (en) * | 2010-07-12 | 2011-05-18 | 无锡华润安盛科技有限公司 | Flipchip thin-small outline packaged lead frame and package structure thereof |
| CN202196776U (en) * | 2011-06-13 | 2012-04-18 | 西安天胜电子有限公司 | Flat carrier-free leadless pin exposed packaging part |
| US20120175756A1 (en) * | 2011-01-11 | 2012-07-12 | Samsung Electronics Co., Ltd. | Semiconductor packages having lead frames |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201262956Y (en) * | 2008-09-04 | 2009-06-24 | 浙江华越芯装电子股份有限公司 | High-power multi-chip packaging structure of integrated circuit |
| US8703545B2 (en) * | 2012-02-29 | 2014-04-22 | Alpha & Omega Semiconductor, Inc. | Aluminum alloy lead-frame and its use in fabrication of power semiconductor package |
| CN204167288U (en) * | 2014-08-22 | 2015-02-18 | 苏州日月新半导体有限公司 | Flat no-lead packages body |
-
2014
- 2014-08-22 CN CN201410417894.4A patent/CN104157620A/en active Pending
- 2014-08-22 CN CN201910327120.5A patent/CN110071078A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1630945A (en) * | 2000-12-14 | 2005-06-22 | 国际整流器公司 | Semiconductor device package and lead frame with die overhanging lead frame pad |
| CN201417765Y (en) * | 2009-04-01 | 2010-03-03 | 苏州固锝电子股份有限公司 | Base island free semi-conductor chip package structure |
| CN201838575U (en) * | 2010-07-12 | 2011-05-18 | 无锡华润安盛科技有限公司 | Flipchip thin-small outline packaged lead frame and package structure thereof |
| US20120175756A1 (en) * | 2011-01-11 | 2012-07-12 | Samsung Electronics Co., Ltd. | Semiconductor packages having lead frames |
| CN202196776U (en) * | 2011-06-13 | 2012-04-18 | 西安天胜电子有限公司 | Flat carrier-free leadless pin exposed packaging part |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104157620A (en) | 2014-11-19 |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190730 |
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| WD01 | Invention patent application deemed withdrawn after publication |