CN110069119A - A kind of chip-in series circuit and calculate equipment - Google Patents
A kind of chip-in series circuit and calculate equipment Download PDFInfo
- Publication number
- CN110069119A CN110069119A CN201910432399.3A CN201910432399A CN110069119A CN 110069119 A CN110069119 A CN 110069119A CN 201910432399 A CN201910432399 A CN 201910432399A CN 110069119 A CN110069119 A CN 110069119A
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- chip
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- circuit
- power supply
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3253—Power saving in bus
Abstract
The present invention relates to power supply power supply technical fields, and disclose a kind of chip-in series circuit, comprising: the n grade chip of series connection；Every grade of chip has main operating voltage input terminal, ground terminal and I/O voltage input end；Wherein, the ground terminal ground connection of the 1st grade of chip, the main operating voltage input terminal connection power supply of n-th grade of chip, the ground terminal of the main operating voltage input terminal connection i+1 grade chip of i-stage chip, i ∈ [1, n)；The I/O voltage input end of j-th stage chip connects the main operating voltage input terminal of jth+m-1 grades of chip, and wherein m is determined according to the main operating voltage standard value of chip and I/O standard voltage value, j ∈ [1, n-m+1].The chip-in series circuit and calculating equipment, I/O power supply mode are eliminated through the efficiency losses between LDO decompression bring pressure difference, improve the power supply conversion efficiency of product.
Description
Technical field
The present invention relates to power supply power supply technical field, specially a kind of chip-in series circuit and calculating equipment.
Background technique
Special purpose computer is a kind of calculating equipment based on large scale integrated circuit, calculates the core that power chip is special purpose computer
Center portion part, chip performance determine the calculated performance of special purpose computer.Currently, using chip-in series on traditional calculation power circuit board
Power supply mode, i.e. multiple groups chip form plural serial stage by the way of being serially connected between power input and ground terminal
Voltage domain.
External power supply power supply VIN is powered to the chip of multiple series connections in the prior art, due to each chip
All there is internal resistance, the chip of series connection forms a power supply and divides link.The quantity of chip and the voltage swing of VIN are related；
Since the internal resistance of chip is of slight difference, in the ideal situation, the main operating voltage of chip be it is equal, main operating voltage is mainly
The arithmetic element and storage unit of chip interior are powered；In the prior art, based on the requirement of Design consistency, it will usually
It is powered using the I/O and PLL that after same supply voltage progress conversion process are different chips.
Chip at different levels needs LDO circuit to be powered to I/O component and PLL component in above-mentioned existing power supply link, LDO
Circuit can bring pressure drop as accessory power supply itself, and this pressure drop brings the loss of power supply conversion efficiency；In addition, due to LDO
The presence of circuit affects properties of product, increases product cost so that the PCBA for calculating power circuit board is complex.
Summary of the invention
(1) the technical issues of solving
In view of the deficiencies of the prior art, the present invention provides a kind of chip-in series circuit and equipment is calculated, has to eliminate and passes through
The advantages that LDO is depressured the efficiency losses between bring pressure difference, improves the power supply conversion efficiency of product, solves existing confession
Chip at different levels needs LDO circuit to be powered to I/O component and PLL component in current source road, and LDO circuit is as accessory power supply itself
Pressure drop can be brought, the problem of this pressure drop brings the loss of power supply conversion efficiency.
(2) technical solution
To realize that above-mentioned eliminate improves the power supply conversion of product by the efficiency losses between LDO decompression bring pressure difference
A kind of the purpose of efficiency, the invention provides the following technical scheme: chip-in series circuit, comprising: the n grade chip of series connection；Often
Grade chip has main operating voltage input terminal, ground terminal and I/O voltage input end；
Wherein, the ground terminal ground connection of the 1st grade of chip, the main operating voltage input terminal of n-th grade of chip connect power supply, i-stage
The ground terminal of the main operating voltage input terminal connection i+1 grade chip of chip, i ∈ [1, n)；
The I/O voltage input end of j-th stage chip connects the main operating voltage input terminal of jth+m-1 grades of chip, and wherein m is according to core
The main operating voltage standard value of piece and I/O standard voltage value determine, j ∈ [1, n-m+1].
Preferably, the product of the m and main operating voltage standard value between I/O voltage minimum sandards value and I/O voltage most
Between big standard value.
Preferably, every grade of chip also has PLL voltage input end；The PLL voltage input end of chips at different levels is by dividing
Volt circuit is connect with the I/O voltage input end of chips at different levels.
Preferably, the voltage of the I/O voltage input end of any chip of the n-th-m+2 grades of chips into n-th grade of chip
It is provided by auxiliary circuit.
Preferably, the auxiliary circuit connect with power supply or the auxiliary circuit with except the power supply with
Outer other feeder ears connection.
Preferably, the auxiliary circuit is connect by booster circuit with power supply；The input terminal of the booster circuit with
Power supply connection, the output end of the booster circuit are connect with auxiliary circuit；Wherein, the auxiliary circuit is LDO circuit.
Preferably, the series circuit further include: be connected between power supply and ground terminal and in parallel with n grades of chips
Voltage regulator circuit.
Preferably, the series circuit further include: the voltage regulator circuit in parallel with level-one chip or multiple chips.
Preferably, the voltage regulator circuit includes: the resistance and capacitor being connected in parallel.
According to a kind of chip-in series circuit, it is proposed that a kind of calculating equipment, including described in any item a kind of cores among the above
Piece series circuit.
(3) beneficial effect
Compared with prior art, the present invention provides a kind of chip-in series circuit and calculating equipment, have following the utility model has the advantages that should
Chip-in series circuit and calculating equipment, the voltage of what main operating voltage input terminal is straight after the chip-in series circuit provided utilizes
What I/O voltage input end is powered before being connected in, using this I/O power supply mode, without in each I/O voltage input end
Power supply link in LDO circuit is all added, reduce calculate power circuit board PCBA difficulty, improve properties of product, reduce
Product cost；In addition, this I/O power supply mode is eliminated through the efficiency losses between LDO decompression bring pressure difference, improve
The power supply conversion efficiency of product.
Detailed description of the invention
Fig. 1 is the series connection schematic diagram for calculating power chip in the prior art；
Fig. 2 is what preceding chip connected mode schematic diagram of one embodiment of chip-in series circuit of the present invention；
Fig. 3 is what rear chip connected mode schematic diagram of one embodiment of chip-in series circuit of the present invention；
Fig. 4 is the connected mode schematic diagram of the part grade chip of another embodiment of chip-in series circuit of the present invention.
Specific embodiment
Below in conjunction with the embodiment of the present invention and attached drawing, technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
A kind of chip-in series circuit, comprising: the n grade chip of series connection；Every grade of chip have main operating voltage input terminal,
Ground terminal and I/O voltage input end；
Wherein, the ground terminal ground connection of the 1st grade of chip, the main operating voltage input terminal of n-th grade of chip connect power supply, i-stage
The ground terminal of the main operating voltage input terminal connection i+1 grade chip of chip, i ∈ [1, n)；
The I/O voltage input end of j-th stage chip connects the main operating voltage input terminal of jth+m-1 grades of chip, and wherein m is according to core
The main operating voltage standard value of piece and I/O standard voltage value determine, j ∈ [1, n-m+1].
In the present invention, the product of the m and main operating voltage standard value is between I/O voltage minimum sandards value and I/O voltage
Between maximum standard value.
In the present invention, every grade of chip also has PLL voltage input end；The PLL voltage input end of chips at different levels passes through
Bleeder circuit is connect with the I/O voltage input end of chips at different levels.
In the present invention, the electricity of the I/O voltage input end of any chip of the n-th-m+2 grades of chips into n-th grade of chip
Pressure is provided by auxiliary circuit.
In the present invention, the auxiliary circuit connect with power supply or the auxiliary circuit with except the power supply
Other feeder ears connection in addition.
In the present invention, the auxiliary circuit is connect by booster circuit with power supply；The input terminal of the booster circuit
It is connect with power supply, the output end of the booster circuit is connect with auxiliary circuit；Wherein, the auxiliary circuit is LDO circuit.
In the present invention, the series circuit further include: be connected to it is between power supply and ground terminal and with n grades of chips simultaneously
The voltage regulator circuit of connection.
In the present invention, the series circuit further include: the voltage regulator circuit in parallel with level-one chip or multiple chips.
In the present invention, the voltage regulator circuit includes: the resistance and capacitor being connected in parallel.
Embodiment:
As shown in Fig. 2, the chip-in series circuit includes: the n grade chip of series connection；External power supply VIN is to n grades of chips
It is powered, so that n grades of chips, which form a power supply, divides link.Wherein, every grade of chip have main operating voltage input terminal and
Ground terminal.The ground terminal ground connection of 1st grade of chip, the main operating voltage input terminal of n-th grade of chip connect power supply VIN, i-stage
The ground terminal of the main operating voltage input terminal connection i+1 grade chip of chip, i ∈ [1, n).With preceding 8 grades of cores shown in Fig. 2
For piece, the ground terminal ground connection of the 1st grade of chip, the main operating voltage input terminal of the 1st grade of chip connects the ground connection of the 2nd grade of chip
End, the ground terminal of the main operating voltage input terminal connection 3rd level chip of the 2nd grade of chip, and so on.
Main operating voltage (core voltage) is mainly powered the arithmetic element and storage unit of chip interior, resonable
Think under state, the main operating voltage of chip is equal.In the present embodiment, it would be desirable to the main operating voltage value of the chip under state
Referred to as main operating voltage standard value.By taking the main operating voltage standard value of each chip is 0.45V as an example, in Fig. 2 on each chip
The dated voltage value in portion is the standard voltage value of the main operating voltage input terminal of the chip.It can be seen that according to from front to back
Sequence, the standard voltage value of the main operating voltage input terminal of chips at different levels be with 0.45V be a voltage domain carry out it is incremental.
Other than the arithmetic element of chip interior and storage unit need to power, the I/O component of chip interior is also required to
Power supply.Chips at different levels also have I/O voltage input end, and the I/O voltage value of chip is known as I/O voltage standard in the ideal situation
Value.The present embodiment is illustrated so that I/O standard voltage value is 1.8V as an example.
The Variation Features of the standard voltage value of main operating voltage input terminal based on chips at different levels, the present embodiment utilize rear several
What I/O voltage input end is powered before the voltage of the main operating voltage input terminal of grade is directly.Specifically, j-th stage core
The I/O voltage input end of piece connects the main operating voltage input terminal of jth+m-1 grades of chip, that is, uses the master of jth+m-1 grades of chip
The voltage of operating voltage input terminal is that the I/O voltage input end of j-th stage chip is powered.Here, m is the main work according to chip
Make standard voltage value and I/O standard voltage value to determine, j ∈ [1, n-m+1].
In the present embodiment, the I/O voltage input end of j-th stage chip is preferably the main work electricity of direct-connected jth+m-1 grades of chips
Press input terminal.
In actual application, due to the influence of chip manufacturing performance, the performance parameter of chip is not necessarily ideal
The main operating voltage and I/O voltage of parameter namely chip appear in the case where being floated in a certain range of standard value.Than
Such as, the main operating voltage of certain chips is slightly less than 0.45V, a little higher than 0.45V of main operating voltage of certain chips.It is sieving in practice
When selecting chip, quality control can be carried out according to floating situation, really be selected and use the floating of the chip in actual circuit and all exist
It allows in floating range, such as it is ± 10% that main operating voltage, which is floated, i.e. the main operating voltage range of chip is [0.45V-
0.045V,0.45V+0.045V]。
Similarly, in practice, the I/O voltage of chip also allows a certain range of floating, specifically sets I/O voltage
Minimum sandards value and I/O voltage maximum standard value, allow the I/O voltage of chip I/O voltage minimum sandards value and I/O voltage most
It floats between big standard value.Such as I/O voltage float be ± 10%, i.e. the I/O voltage floating range of chip be [1.8V-0.18V,
1.8V+0.18V]。
Due to the chip in practical screening chip main operating voltage floating range can control, if cannot sieve completely
Choosing obtains the chip that main operating voltage is standard value, and it is relatively low in main operating voltage standard value to can choose one group of main operating voltage
Chip selects the higher chip in main operating voltage standard value of another group of main operating voltage, according to circumstances adjusts when being connected
Series sequence of the whole two groups of chip in entire series circuit, so that the partial pressure of final series circuit is able to maintain equilibrium unanimously.
That is, the main operating voltage floating bring of chip can be ignored in practice to be influenced.
Therefore, in the present embodiment, the determination basis of m are as follows: the product of m and main operating voltage standard value between I/O voltage most
Between small standard value and I/O voltage maximum standard value.Standard voltage value using the main operating voltage input terminal of chips at different levels is
It carries out being incremented by this feature, the determining product with main operating voltage standard value using main operating voltage standard value as a voltage domain
Value of some integer value as m between I/O voltage minimum sandards value and I/O voltage maximum standard value.Have at one
In the example of body, I/O voltage minimum sandards value be 1.8V-0.18V=1.62V, I/O voltage maximum standard value be 1.8V+0.18V=
1.98V seeks with 0.45 integer value of the product between 1.62 and 1.98 being 4, i.e. m=4.It is visible in fig. 2, the 1st grade of core
The I/O voltage input end of piece connects the main operating voltage input terminal of the 4th grade of chip, the I/O voltage input end connection of the 2nd grade of chip
The main operating voltage input terminal of 5th grade of chip, the I/O voltage input end of 3rd level chip connect the main operating voltage of the 6th grade of chip
Input terminal, and so on.If there is some or certain several j-th stage chips, the main work electricity of corresponding jth+m-1 grades of chips
Press the voltage value of input terminal can be in its I/O voltage input end and jth+m-1 for this grade of chip beyond I/O voltage floating range
Auxiliary circuit is added in the connecting link of the main operating voltage input terminal of grade chip and carries out pressure drop, to guarantee the I/O of this grade of chip
Normal working voltage.
The 1st grade of chip to the n-th-m+1 grades of chip in series circuit can be directly from certain grade of core after chips at different levels
The main operating voltage input terminal of piece introduces I/O voltage.For the n-th-m+2 grades of chip to n-th grade of chip, any chip therein
The voltage of I/O voltage input end then needs to provide by auxiliary circuit.
In the example depicted in fig. 3, series circuit includes 24 grades of chips altogether, wherein the 1st grade of chip to the 21st grade of chip all
I/O voltage directly can be introduced from the main operating voltage input terminal of certain grade of chip after chips at different levels, and for the 22nd grade of core
Piece then needs to mention from power supply to the 24th grade of chip since the pressure difference between the same level chip and any rear class chip is not high enough
The supply voltage VIN of confession introduces I/O voltage.Here supply voltage VIN is also the main operating voltage input of n-th grade of chip simultaneously
The input voltage at end.In order to meet the requirements the 22nd grade of chip to the voltage value of the I/O voltage input end of the 24th grade of chip, need
Auxiliary circuit LDO is added in a link, further, in order to ensure the pressure difference that LDO is worked normally, needs to boost to VIN
Processing and then the I/O voltage input end that the 22nd grade of chip to the 24th grade of chip is fed back to by LDO.That is the 22nd grade of chip is extremely
The voltage of the I/O voltage input end of 24th grade of chip is provided by LDO, and LDO is connect by booster circuit with power supply.
As another embodiment of the present invention, if the supply voltage of power supply is sufficiently high, above-mentioned and the n-th-m+2 grades of chip
The auxiliary circuit of the I/O voltage input end connection of any chip into n-th grade of chip can directly be connect with power supply, be not necessarily to
It is connect by booster circuit with power supply.In this case, since the power supply of power supply is higher, partial pressure electricity can be passed through
Road carries out partial pressure appropriate, the input voltage by partial pressure as the main operating voltage input terminal of n-th grade of chip.
As another embodiment of the present invention, the above-mentioned I/ with any chip of the n-th-m+2 grades of chip into n-th grade of chip
O voltage input end connection auxiliary circuit can not be connect with power supply, but with other power supplies other than above-mentioned power supply
End connection.For example, introducing voltage to auxiliary circuit, for auxiliary from other feeder ears of the circuit board comprising the chip-in series circuit
Help circuit to the I/O voltage for being supplied to any chip of the n-th-m+2 grades of chip into n-th grade of chip after voltage progress pressure drop processing
Input terminal.
Further, every grade of chip also has PLL voltage input end, and the PLL voltage input end of chips at different levels passes through partial pressure
Circuit is connect with the I/O voltage input end of chips at different levels.In general, the supply voltage of PLL voltage input end is less than I/O voltage
The supply voltage of input terminal is supplied to PLL electricity after being divided the supply voltage of I/O voltage input end by bleeder circuit
Press input terminal.
Before the voltage of what main operating voltage input terminal is directly after chip-in series circuit provided in this embodiment utilizes
What I/O voltage input end is powered, using this I/O power supply mode, without the power supply in each I/O voltage input end
LDO circuit is all added in link, reduce calculate power circuit board PCBA difficulty, improve properties of product, reduce product at
This.In addition, this I/O power supply mode is eliminated through the efficiency losses between LDO decompression bring pressure difference, product is improved
Power supply conversion efficiency.
In above-mentioned Fig. 2 and embodiment shown in Fig. 3, every grade of chip of series connection is carried out by taking a chip as an example
Illustrate.In another embodiment of the invention, any level chip in n grades of chips or multiple chips can include number
A chip being connected in parallel.It is not multiple chips of ideal value for main operating voltage, can takes certain several chip are in parallel
The wherein level-one being connected in n grades of chips.After parallel connection, so that the main operating voltage of level-one chip tends to ideal
Value, thus it is more with consistency.
It further, can be in order to enable the main operating voltage of chip at different levels is more with consistency in power supply partial pressure link
Increase voltage regulator circuit in series circuit.Fig. 4 shows the portion of another embodiment of chip-in series circuit provided by the invention
It is classified the connected mode schematic diagram of chip.As shown in figure 4, the present embodiment on the basis of the above embodiments, further increases
Two voltage regulator circuits.One of voltage regulator circuit with connect after the 21st grade of chip and the 22nd grade of chip be in parallel,
Another voltage regulator circuit with connect after the 23rd grade of chip and the 24th grade of chip be in parallel.Voltage regulator circuit includes parallel connection
The circuit and capacitor of connection, shunt voltage adjusts circuit in two-stage chip, plays the role of electric voltage equalization and filtering.
Optionally, the present invention can also be connected in parallel voltage regulator circuit in wherein any level chip.In which rank of core
It is consistent depending on the main operating voltage of which rank of chip or which grade chip that piece or which grade chip shunt voltage adjust circuit
Property is not sufficiently good.The chip that designer can arbitrarily select main operating voltage consistency not sufficiently good adjusts electricity to its shunt voltage
Road.
Optionally, the present invention can also increase the voltage in parallel with n grades of chips between power supply and ground terminal and adjust
Circuit is also able to maintain the consistency of the partial pressure of chip at different levels in power supply partial pressure link.
The present invention also provides a kind of calculating equipment, which includes chip string described in any of the above-described embodiment
Join circuit.Optionally, which can be special purpose computer.
The chip-in series circuit and calculating equipment, what main operating voltage inputs after the chip-in series circuit provided utilizes
What I/O voltage input end is powered before the voltage at end is directly, using this I/O power supply mode, without in each I/O
LDO circuit is all added in the power supply link of voltage input end, reduces the difficulty for calculating the PCBA of power circuit board, improves product
Can, reduce product cost；In addition, this I/O power supply mode eliminates the efficiency damage being depressured between bring pressure difference by LDO
Consumption, improves the power supply conversion efficiency of product.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
A variety of variations, modification, replacement can be carried out to these embodiments without departing from the principles and spirit of the present invention by understanding
And modification, the scope of the present invention is defined by the appended.
Claims (10)
1. a kind of chip-in series circuit characterized by comprising the n grade chip of series connection；Every grade of chip has main work electricity
Press input terminal, ground terminal and I/O voltage input end；
Wherein, the ground terminal ground connection of the 1st grade of chip, the main operating voltage input terminal of n-th grade of chip connect power supply, i-stage
The ground terminal of the main operating voltage input terminal connection i+1 grade chip of chip, i ∈ [1, n)；
The I/O voltage input end of j-th stage chip connects the main operating voltage input terminal of jth+m-1 grades of chip, and wherein m is according to core
The main operating voltage standard value of piece and I/O standard voltage value determine, j ∈ [1, n-m+1].
2. a kind of chip-in series circuit according to claim 1, which is characterized in that the m and main operating voltage standard value
Product between I/O voltage minimum sandards value and I/O voltage maximum standard value.
3. a kind of chip-in series circuit according to claim 1 or 2, which is characterized in that every grade of chip also has PLL
Voltage input end；The PLL voltage input end of chips at different levels is connect by bleeder circuit with the I/O voltage input end of chips at different levels.
4. a kind of chip-in series circuit according to any one of claim 1-3, which is characterized in that described n-th-m+2 grades
The voltage of the I/O voltage input end of any chip of the chip into n-th grade of chip is provided by auxiliary circuit.
5. a kind of chip-in series circuit according to claim 4, which is characterized in that the auxiliary circuit and power supply connect
It connects or the auxiliary circuit is connect with other feeder ears in addition to the power supply.
6. a kind of chip-in series circuit according to claim 5, which is characterized in that the auxiliary circuit passes through booster circuit
It is connect with power supply；The input terminal of the booster circuit is connect with power supply, the output end and auxiliary of the booster circuit
Circuit connection；Wherein, the auxiliary circuit is LDO circuit.
7. a kind of chip-in series circuit according to claim 1 to 6, which is characterized in that the series circuit is also
It include: to be connected to voltage regulator circuit between power supply and ground terminal and in parallel with n grades of chips.
8. a kind of chip-in series circuit according to claim 1 to 6, which is characterized in that the series circuit is also
It include: the voltage regulator circuit in parallel with level-one chip or multiple chips.
9. a kind of chip-in series circuit according to claim 7 or 8, which is characterized in that the voltage regulator circuit includes:
The resistance and capacitor being connected in parallel.
10. a kind of calculating equipment, which is characterized in that including a kind of chip-in series circuit of any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910432399.3A CN110069119A (en) | 2019-05-23 | 2019-05-23 | A kind of chip-in series circuit and calculate equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910432399.3A CN110069119A (en) | 2019-05-23 | 2019-05-23 | A kind of chip-in series circuit and calculate equipment |
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| Publication Number | Publication Date |
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| CN110069119A true CN110069119A (en) | 2019-07-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910432399.3A Pending CN110069119A (en) | 2019-05-23 | 2019-05-23 | A kind of chip-in series circuit and calculate equipment |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111857224A (en) * | 2020-07-31 | 2020-10-30 | 深圳君略科技有限公司 | Multistage chip series circuit and driving system |
| CN112968600A (en) * | 2021-02-19 | 2021-06-15 | 浙江曲速科技有限公司 | Limited dynamic power consumption chip system and task scheduling method for serial power supply thereof |
| CN114546088A (en) * | 2020-11-25 | 2022-05-27 | 北京比特大陆科技有限公司 | Chip power supply circuit and electronic equipment |
-
2019
- 2019-05-23 CN CN201910432399.3A patent/CN110069119A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111857224A (en) * | 2020-07-31 | 2020-10-30 | 深圳君略科技有限公司 | Multistage chip series circuit and driving system |
| CN114546088A (en) * | 2020-11-25 | 2022-05-27 | 北京比特大陆科技有限公司 | Chip power supply circuit and electronic equipment |
| WO2022111360A1 (en) * | 2020-11-25 | 2022-06-02 | 北京比特大陆科技有限公司 | Chip power supply circuit and electronic device |
| CN114546088B (en) * | 2020-11-25 | 2023-11-14 | 北京比特大陆科技有限公司 | Chip power supply circuit and electronic equipment |
| CN112968600A (en) * | 2021-02-19 | 2021-06-15 | 浙江曲速科技有限公司 | Limited dynamic power consumption chip system and task scheduling method for serial power supply thereof |
| CN112968600B (en) * | 2021-02-19 | 2022-07-08 | 浙江曲速科技有限公司 | Task scheduling method for serial power supply of limited dynamic power consumption chip system |
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