CN110062946A - 3d nand的智能刷新 - Google Patents

3d nand的智能刷新 Download PDF

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CN110062946A
CN110062946A CN201780073037.9A CN201780073037A CN110062946A CN 110062946 A CN110062946 A CN 110062946A CN 201780073037 A CN201780073037 A CN 201780073037A CN 110062946 A CN110062946 A CN 110062946A
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flash memory
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CN110062946B (zh
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哈里·坎南
罗伯特·李
毛育红
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Pure Storage Inc
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    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
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    • G11INFORMATION STORAGE
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    • G11CSTATIC STORES
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    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Abstract

提供了一种用于处理闪速存储器的区块以减少来自闪速存储器的原始比特差错的方法。该方法包括针对刷新操作识别闪速存储器的一个或多个区块并且将关于所识别的区块的信息写入到数据结构。该方法包括作为刷新操作根据该数据结构向所识别的区块发出后台读取。该方法可体现在计算机可读介质上。在一些实施例中,后台读取可基于响应于闪速存储器中的原始比特差错计数随着时间的增大的基于时间的刷新。

Description

3D NAND的智能刷新
背景技术
例如闪存之类的固态存储器当前用在固态驱动器(solid-state drive, SSD)中来增强或取代被统称为旋转介质的传统硬盘驱动器(hard disk drive,HDD)、可写CD(致密盘)或可写DVD(数字多功能盘)驱动器以及磁带驱动器,用于存储大量的数据。闪存和其他固态存储器具有不同于旋转介质的特性。然而,许多固态驱动器出于兼容性原因被设计为符合硬盘驱动器标准,这使得提供增强的特征或者利用闪存和其他固态存储器的独特方面是困难的。一种新类型的闪速存储器——三维(3D)NAND——具有随着时间的流逝变化但在硬盘驱动器或固态驱动器体系结构中没有缓和的差错行为。这些差错行为可导致对数据的不一致且易出错的读取,以及由于错误地相信闪速存储器已劣化而使得闪速存储器提前退休。
实施例是在这个背景内出现的。
发明内容
在一些实施例中,提供了一种用于处理闪速存储器的区块以减少来自闪速存储器的原始比特差错的方法。该方法包括针对刷新操作识别闪速存储器的一个或多个区块并且将关于所识别的区块的信息写入到数据结构。该方法包括作为刷新操作根据该数据结构向所识别的区块发出后台读取。该方法可体现在计算机可读介质上。在一些实施例中,后台读取可基于响应于闪速存储器中的原始比特差错计数随着时间的增大的基于时间的刷新。
在一些实施例中,提供了一种存储系统。该存储系统包括闪速存储器和可配置为保存数据结构的另一存储器。该系统包括一个或多个处理器,可配置为针对刷新操作识别闪速存储器的区块,并且该一个或多个处理器可配置为将关于所识别的区块的信息写入到该数据结构。该系统包括硬件引擎,可配置为作为刷新操作根据该数据结构对所识别的区块的后台读取定序。
实施例的其他方面和优点将通过以下结合附图的详细描述而变得清楚,附图以示例方式图示了所描述的实施例的原理。
附图说明
通过结合附图参考接下来的描述,将最好地理解描述的实施例及其优点。这些附图绝不限制本领域技术人员可在不脱离描述的实施例的精神和范围的情况下对描述的实施例做出的形式和细节上的任何改变。
图1是根据一些实施例的存储集群的透视图,该存储集群具有多个存储节点和耦合到每个存储节点的内部存储,用来提供附网存储。
图2是根据一些实施例示出互连交换机耦合多个存储节点的框图。
图3是根据一些实施例示出存储节点的内容和非易失性固态存储单元之一的内容的多级框图。
图4根据一些实施例示出了存储服务器环境,其使用图1-图3的存储节点和存储单元的实施例。
图5是根据一些实施例的刀片(blade)硬件框图,示出了控制平面、计算和存储平面和与底层物理资源交互的权力机构(authority)。
图6示出了NAND闪速存储器中常见的示例位线和串联晶体管电路。
图7描绘了3D NAND闪存,其可随着时间的流逝累积静电电荷。
图8是3D NAND闪速存储器的比特差错率与时间的图线。
图9是固态存储装置的实施例的框图,其具有循环经过对于由数据结构指示的闪速存储器区块的后台读取操作的定序器。
图10是根据一些实施例的刷新3D NAND闪速存储器的方法的流程图,其可在图1-图9的存储集群中实现,或者在存储阵列、固态存储装置或存储系统中实现。
图11是示出可实现本文描述的实施例的示范性计算设备的图示。
具体实施方式
本文描述的存储系统的实施例解决了三维(3D)NAND闪速存储器上的电荷累积和关联的差错增加的问题。定序器循环经过闪速存储器的区块的后台读取操作,释放电荷累积,从而刷新3D NAND闪存以获得与任由电荷累积存在的情况相比具有更低原始差错率的读取。3D NAND的智能刷新的各种特征可实现在存储集群(例如,具有多个存储节点)、存储阵列(例如,具有中央控制器或高可用性控制器对)、固态驱动器、固态存储装置或其他存储系统中。有可能其他类型的固态存储器也可受益。
下面的实施例描述了存储集群,其存储用户数据,例如源自一个或多个用户或客户端系统或存储集群外部的其他来源的用户数据。存储集群利用纠删编码(erasurecoding)和元数据的冗余拷贝来在容纳在一个或多个机箱内的存储节点间分布用户数据。纠删编码指的是一种数据保护或重建的方法,其中数据被存储在一组不同的位置(例如盘、存储节点或地理位置)上。闪速存储器是可与实施例集成的一类固态存储器,但实施例可扩展到其他类型的固态存储器或其他存储介质,包括非固态存储器。对存储位置和工作量的控制在集群式对等系统中被分布在各存储位置间。诸如在各种存储节点之间调解通信,检测存储节点何时变得不可用以及在各种存储节点之间平衡I/O(输入和输出)之类的任务全都是以分布方式处理的。数据在一些实施例中以支持数据恢复的数据片段或条带的形式被布局或分布在多个存储节点上。数据的所有权可在集群内被重指派,独立于输入和输出模式。下文更详细描述的这个体系结构允许了集群中的存储节点失效,而系统保持可工作,因为数据可从其他存储节点重建并从而保持可用于输入和输出操作。在各种实施例中,存储节点可被称为集群节点、刀片或服务器。下文参考图1-图5论述各种系统方面。参考图6-图10描述 3D NAND的智能刷新。
存储集群被包含在机箱(即,容纳一个或多个存储节点的外壳)内。在机箱内包括了一种向每个存储节点提供电力的机制,例如配电总线,以及一种通信机制,例如使能存储节点之间的通信的通信总线。根据一些实施例,存储集群可在一个位置中作为独立系统运行。在一个实施例中,机箱包含配电和通信总线两者的至少两个实例,它们可被独立使能或禁用。内部通信总线可以是以太网总线,然而,诸如快速外围组件互连 (PeripheralComponent Interconnect,PCI)、InfiniBand和其他之类的其他技术是同等合适的。机箱为外部通信总线提供了一种端口,用于使能多个机箱之间的直接或通过交换机的通信,以及与客户端系统的通信。外部通信可使用诸如以太网、InfiniBand、光纤通道等等之类的技术。在一些实施例中,外部通信总线对于机箱间和客户端通信使用不同的通信总线技术。如果交换机被部署在机箱内或机箱之间,则交换机可充当多个协议或技术之间的转化。当多个机箱被连接来定义存储集群时,存储集群可被客户端利用专属接口或诸如网络文件系统(network file system,NFS)、共用互联网文件系统(common internet file system,CIFS)、小型计算机系统接口(small computer system interface,SCSI)或超文本传送协议(hypertext transfer protocol,HTTP)之类的标准接口来访问。从客户端协议的转化可发生在交换机处、机箱外部通信总线处或者每个存储节点内。
每个存储节点可以是一个或多个存储服务器并且每个存储服务器连接到一个或多个非易失性固态存储器单元,它们可被称为存储单元或存储设备。一个实施例包括每个存储节点中的单个存储服务器和一到八个非易失性固态存储器单元,然而这一个示例并不打算是限制性的。存储服务器可包括处理器、动态随机访问存储器(DRAM)和用于内部通信总线和每个电力总线的配电的接口。在一些实施例中,在存储节点内部,接口和存储单元共享通信总线,例如快速PCI。非易失性固态存储器单元可通过存储节点通信总线直接访问内部通信总线接口,或者请求存储节点访问总线接口。非易失性固态存储器单元包含嵌入式中央处理单元(CPU)、固态存储控制器和一定量的固态大容量存储装置,例如在一些实施例中在2到32 兆兆字节(TB)之间。例如DRAM之类的嵌入式易失性存储介质和能量储备装置被包括在非易失性固态存储器单元中。在一些实施例中,能量储备装置是使能在电力丢失的情况下将DRAM内容的子集转移到稳定存储介质的电容器、超级电容器或者电池。在一些实施例中,非易失性固态存储器单元是利用存储级存储器来构成的,例如代替DRAM并且使能化简的电力贮存装置的相变或磁阻随机访问存储器(MRAM)。
存储节点和非易失性固态存储装置的许多特征之一是在存储集群中前瞻性地重建数据的能力。存储节点和非易失性固态存储装置可确定存储集群中的存储节点或非易失性固态存储装置何时不可达,此操作独立于是否存在涉及该存储节点或非易失性固态存储装置的读取数据的尝试。存储节点和非易失性固态存储装置随后合作来在至少部分新的位置恢复并且重建数据。这构成了一种前瞻性重建,因为系统重建数据,而不等待直到对于从采用该存储集群的客户端系统发起的读取访问需要数据为止。储存存储器及其操作的这些和进一步细节在下文论述。
图1是根据一些实施例的存储集群160的透视图,该存储集群具有多个存储节点150和耦合到每个存储节点的内部固态存储器,用来提供附网存储或存储区域网络。附网存储、存储区域网络或存储集群或其他储存存储器可包括一个或多个存储集群160,每个存储集群160具有一个或多个存储节点150,采取物理组件和由其提供的储存存储器的量两者的灵活且可重配置的布置。存储集群160被设计为适合装在机架中,并且一个或多个机架可被设置起来并且根据储存存储器的需要被填充。存储集群160具有机箱138,机箱138具有多个插槽142。应当明白,机箱138可被称为壳体、外壳或机架单元。在一个实施例中,机箱138具有十四个插槽 142,但容易设计其他数目的插槽。例如,一些实施例具有四个插槽、八个插槽、十六个插槽、三十二个插槽或者其他适当数目的插槽。在一些实施例中每个插槽142可容纳一个存储节点150。机箱138包括可被利用来将机箱138安放在机架上的襟翼(flap)148。风扇144为存储节点150及其组件的冷却提供空气循环,但可使用其他冷却组件,或者可设计没有冷却组件的实施例。交换结构146将机箱138内的存储节点150耦合在一起并且耦合到网络以用于到存储器的通信。在图1所示的实施例中,交换结构146和风扇144左侧的插槽142被示为由存储节点150占据,而出于说明目的交换结构146和风扇144右侧的插槽142是空的并且可用于插入存储节点150。此配置是一个示例,并且在各种另外的布置中一个或多个存储节点150可占据插槽142。在一些实施例中存储节点布置不需要是顺序的或相邻的。存储节点150是可热插的,意思是存储节点150可在不将系统停止或断电的情况下被插入到机箱138中的插槽142中,或者从插槽 142去除。在将存储节点150插入插槽142或从插槽142去除后,系统自动重配置以便识别并适应该变化。重配置在一些实施例中包括恢复冗余和/ 或重平衡数据或负载。
每个存储节点150可具有多个组件。在这里示出的实施例中,存储节点150包括安装有CPU 156(即,处理器)、耦合到CPU 156的存储器 154和耦合到CPU 156的非易失性固态存储装置152的印刷电路板158,但在其他实施例中可使用其他配件和/或组件。存储器154具有被CPU 156 执行的指令和/或被CPU 156操作的数据。如下文进一步说明的,非易失性固态存储装置152包括闪存,或者在其他实施例中,包括其他类型的固态存储器。
参考图1,存储集群160是可扩展的,意思是容易添加具有非统一存储大小的存储容量,如上所述。一个或多个存储节点150可被插入到每个机箱中或从每个机箱去除并且存储集群在一些实施例中自配置。插入的存储节点150,无论是在交付时安装在机箱中或者在后来添加,可具有不同的大小。例如,在一个实施例中,存储节点150可具有4TB的任何倍数,例如8TB、12TB、16TB、32TB等等。在另外的实施例中,存储节点150可具有其他存储量或容量的任何倍数。每个存储节点150的存储容量被广播,并且影响关于如何将数据分条的决策。为了获得最大存储效率,一个实施例可在条带中尽可能宽地自配置,同时受制于如下预定要求:在机箱内丢失多达一个或者多达两个非易失性固态存储装置152或存储节点150的情况下继续操作。
图2是示出耦合多个存储节点150的通信互连170和配电总线172的框图。返回参考图1,通信互连170在一些实施例中可被包括在交换结构146中或者利用交换结构146实现。在多个存储集群160占据一机架的情况下,通信互连170在一些实施例中可被包括在架顶交换机中或者利用架顶交换机实现。如图2中所示,存储集群160被包封在单个机箱138内。外部端口176通过通信互连170耦合到存储节点150,而外部端口174直接耦合到存储节点。外部电力端口178耦合到配电总线172。存储节点150可包括各种量和不同容量的非易失性固态存储装置152,如参考图1 所述。此外,一个或多个存储节点150可以是仅限计算存储节点,如图2 中所示。权力机构168被实现在非易失性固态存储装置152上,例如实现为存储在存储器中的列表或其他数据结构。在一些实施例中,权力机构被存储在非易失性固态存储装置152内并且由在非易失性固态存储装置152 的控制器或其他处理器上执行的软件支持。在另一实施例中,权力机构 168实现在存储节点150上,例如实现为存储在存储器154中并且由在存储节点150的CPU 156上执行的软件支持的列表或其他数据结构。权力机构168在一些实施例中控制数据被如何存储在非易失性固态存储装置152 中以及存储在何处。这个控制帮助确定哪种类型的纠删编码方案被应用到数据,以及哪些存储节点150具有数据的哪些部分。每个权力机构168可被指派到一非易失性固态存储装置152。在各种实施例中,每个权力机构可控制索引节点(inode)号、片段号或者由文件系统、由存储节点150或者由非易失性固态存储装置152指派给数据的其他数据识别符的某个范围。
在一些实施例中,每条数据以及每条元数据在系统中具有冗余。此外,每条数据和每条元数据具有所有者,该所有者可被称为权力机构。如果该权力机构不可达,例如由于存储节点的失效,则对于如何找到该数据或该元数据存在后继计划。在各种实施例中,存在权力机构168的冗余拷贝。权力机构168在一些实施例中具有与存储节点150和非易失性固态存储装置152的关系。覆盖某个范围的数据片段号或数据的其他识别符的每个权力机构168可被指派到特定的非易失性固态存储装置152。在一些实施例中,所有这种范围的权力机构168分布在存储集群的非易失性固态存储装置152上。每个存储节点150具有提供对该存储节点150的(一个或多个)非易失性固态存储装置152的访问的网络端口。数据可被存储在片段中,该片段与片段号相关联并且该片段号在一些实施例中是RAID(独立磁盘冗余阵列)条带的配置的间接性。权力机构168的指派和使用从而建立了到数据的间接性。根据一些实施例,间接性可被称为间接地(在此情况下是经由权力机构168)引用数据的能力。片段识别非易失性固态存储装置152的集合和该非易失性固态存储装置152的集合中的可包含数据的本地识别符。在一些实施例中,本地识别符是设备中的偏移量并且可被多个片段顺序地重复利用。在其他实施例中,本地识别符是特定片段特有的并且从不被重复利用。非易失性固态存储装置152中的偏移量被应用来定位数据以便写入到非易失性固态存储装置152或从非易失性固态存储装置152读取(以RAID条带的形式)。数据被分条于非易失性固态存储装置152的多个单元上,这多个单元可包括或不同于具有用于特定数据片段的权力机构168的非易失性固态存储装置152。
如果特定数据片段所位于的位置存在变化,例如在数据移动或数据重建期间存在变化,则应当在具有用于该数据片段的权力机构168的该非易失性固态存储装置152或存储节点150处咨询该权力机构168。为了定位特定的一条数据,实施例为数据片段计算散列值或者应用索引节点号或数据片段号。此操作的输出指向具有用于该特定一条数据的权力机构168的非易失性固态存储装置152。在一些实施例中,此操作有两个阶段。第一阶段将实体识别符(ID)映射到权力机构识别符,其中实体识别符例如是片段号、索引节点号或者目录号。此映射可包括诸如散列或位元遮罩之类的计算。第二阶段是将权力机构识别符映射到特定的非易失性固态存储装置152,这可通过显式映射完成。该操作是可重复的,从而当该计算被执行时,计算的结果可重复且可靠地指向具有该权力机构168的特定非易失性固态存储装置152。该操作可包括可达存储节点的集合作为输入。如果可达非易失性固态存储单元的集合变化,则最优集合变化。在一些实施例中,持续值是当前指派(其始终为真)并且计算出的值是集群将尝试重配置到的目标指派。此计算可用于在存在可到达并且构成同一集群的一组非易失性固态存储装置152的情况下为权力机构确定最优非易失性固态存储装置152。该计算还确定对等非易失性固态存储装置152的有序集合,该有序集合也将记录权力机构到非易失性固态存储装置映射,从而即使指派的非易失性固态存储装置不可达也可确定权力机构。在一些实施例中如果特定的权力机构168不可用则可咨询复制或替代权力机构168。
参考图1和图2,存储节点150上的CPU 156的许多任务中的两个是分解写入数据,并且重组装读取数据。当系统确定了数据要被写入时,如上所述定位该数据的权力机构168。当已经确定了数据的片段ID时,写入请求被转发到当前被确定为是从该片段确定的权力机构168的主机的非易失性固态存储装置152。非易失性固态存储装置152和相应权力机构168 所在的存储节点150的主机CPU 156随后对数据进行分解或分片并且将数据发送出到各种非易失性固态存储装置152。发送的数据根据纠删编码方案被写入为数据条带。在一些实施例中,数据被请求拉取,而在其他实施例中,数据被推送。相反,当数据被读取时,如上所述定位用于包含该数据的片段ID的权力机构168。非易失性固态存储装置152和相应权力机构 168所在的存储节点150的主机CPU 156从该权力机构所指向的非易失性固态存储装置和相应存储节点请求该数据。在一些实施例中,以数据条带的形式从闪速存储装置读取数据。存储节点150的主机CPU 156随后重组装读取的数据,根据适当的纠删编码方案纠正任何差错(如果存在的话),并且将重组装的数据转发到网络。在另外的实施例中,可在非易失性固态存储装置152中处理这些任务中的一些或全部。在一些实施例中,片段主机通过向存储装置请求页并随后将数据发送到做出原始请求的存储节点来请求数据被发送到存储节点150。
在一些系统中,例如在UNIX风格文件系统中,利用索引节点或者 inode来处理数据,该索引节点指定表示文件系统中的对象的数据结构。该对象例如可以是文件或目录。元数据可伴随该对象,作为诸如许可数据和创建时间戳之类的属性,以及其他属性。片段号可被指派到文件系统中的这种对象的全部或一部分。在其他系统中,利用在别处指派的片段号来处理数据片段。出于论述的目的,分布的单位是实体,并且实体可以是文件、目录或片段。也就是说,实体是存储系统存储的数据或元数据的单位。实体被分组成被称为权力机构的集合。每个权力机构具有权力机构所有者,权力机构所有者是具有更新权力机构中的实体的独家权力的存储节点。换言之,存储节点包含权力机构,并且该权力机构进而包含实体。
片段根据一些实施例是数据的逻辑容器。片段是介质地址空间和物理闪存位置之间的地址空间,即,数据片段号在此地址空间中。片段也可包含元数据,这使得能够在不涉及更高级别软件的情况下恢复数据冗余(再写入到不同的闪存位置或设备)。在一个实施例中,片段的内部格式包含客户端数据和介质映射来确定该数据的位置。通过如下方式来针对例如存储器和其他失效保护每个数据片段:在适用时将该片段分解成若干个数据和奇偶分片。数据和奇偶分片根据纠删编码方案被分布(即分条)在耦合到主机CPU 156的非易失性固态存储装置152上(参见图5)。对术语片段的使用在一些实施例中指的是容器及其在片段的地址空间中的位置。对术语条带的使用指的是与片段相同的一组分片并且根据一些实施例包括分片如何被分布以及冗余或奇偶信息。
一系列地址空间变换在整个存储系统上发生。在顶部是链接到索引节点的目录实体(文件名)。索引节点指向逻辑上存储数据的介质地址空间。介质地址可通过一系列间接介质被映射来分散大文件的负担,或者实现类似去重复或快照之类的数据服务。介质地址可通过一系列间接介质被映射来分散大文件的负担,或者实现类似去重复或快照之类的数据服务。片段地址随后被转化成物理闪存位置。物理闪存位置根据一些实施例具有受系统中的闪存的量限制的地址范围。介质地址和片段地址是逻辑容器,并且在一些实施例中使用128比特或更大的识别符,从而几乎是无限的,重复利用的可能性被计算为长于系统的预期寿命。来自逻辑容器的地址在一些实施例中是以层次方式来分配的。最初,每个非易失性固态存储单元 152可被指派某个范围的地址空间。在这个指派的范围内,非易失性固态存储装置152能够在不与其他非易失性固态存储装置152同步的情况下分配地址。
数据和元数据由针对各种工作量模式和存储设备优化的一组底层存储布局来存储。这些布局包含多个冗余方案、压缩格式和索引算法。这些布局中的一些存储关于权力机构和权力机构主人的信息,而其他的布局存储文件元数据和文件数据。冗余方案包括容忍单个存储设备(例如NAND闪存芯片)内的损坏比特的纠错码、容忍多个存储节点的失效的纠删码和容忍数据中心或区域性失效的复制方案。在一些实施例中,在单个存储单元内使用低密度奇偶校验(low density parity check,LDPC)码。在存储集群内使用里德-索罗门编码,并且在一些实施例中在存储网格内使用镜像。元数据可利用有序日志结构化索引(例如日志结构化合并树)来存储,并且大数据可不被存储在日志结构化布局中。
为了维持实体的多个拷贝间的一致性,存储节点通过计算就两件事隐式地达成一致:(1)包含该实体的权力机构,以及(2)包含该权力机构的存储节点。实体到权力机构的指派可通过将实体伪随机地指派到权力机构、通过基于外部产生的密钥将实体分割成范围或者通过向每个权力机构中放置单个实体来完成。伪随机方案的示例是线性散列和散列的可伸缩散列下复制(Replication Under Scalable Hashin,RUSH)家族,包括受控可伸缩散列下复制(Controlled Replication Under Scalable Hashing, CRUSH)。在一些实施例中,伪随机指派只被用于将权力机构指派到节点,因为节点的集合可变化。权力机构的集合不能变化,因此在这些实施例中可应用任何主观函数。一些放置方案自动地将权力机构放置在存储节点上,而其他放置方案依赖于权力机构到存储节点的显式映射。在一些实施例中,伪随机方案被利用来从每个权力机构映射到候选权力机构所有者的集合。与CRUSH有关的伪随机数据分布函数可将权力机构指派到存储节点并且创建权力机构被指派到的位置的列表。每个存储节点具有伪随机数据分布函数的一个拷贝,并且可达成相同的计算来分布以及随后找到或定位权力机构。伪随机方案的每一者在一些实施例中要求存储节点的可达集合作为输入来得出相同的目标节点。一旦实体已被放置在权力机构中,该实体就可被存储在物理设备上,从而使得预期失效不会导致非预期的数据丢失。在一些实施例中,重平衡算法尝试将所有实体的拷贝以相同布局并且在同一组机器上存储在权力机构内。
预期失效的示例包括设备失效、机器被盗、数据中心火灾和区域性灾害,例如核或地质事件。不同的失效导致不同级别的可接受数据丢失。在一些实施例中,被盗的存储节点既不影响系统的安全性也不影响系统的可靠性,而取决于系统配置,区域性事件可不导致数据的丢失、导致几秒或几分钟的丢失更新或者甚至导致完全数据丢失。
在实施例中,针对存储冗余性的数据放置独立于针对数据一致性的权力机构放置。在一些实施例中,包含权力机构的存储节点不包含任何持续性存储。相反,存储节点连接到不包含权力机构的非易失性固态存储单元。存储节点和非易失性固态存储单元之间的通信互连由多个通信技术构成并且具有非统一性能和故障容差特性。在一些实施例中,如上所述,非易失性固态存储单元经由快速PCI连接到存储节点,存储节点利用以太网背板在单个机箱内连接在一起,并且机箱被连接在一起形成存储集群。存储集群在一些实施例中利用以太网或光纤通道连接到客户端。如果多个存储集群被配置成存储网格,则多个存储集群是利用因特网或其他长距离联网链路来连接的,这些链路例如是“城市级”链路或不穿过互联网的私有链路。
权力机构所有者具有修改实体、将实体从一个非易失性固态存储单元迁移到另一非易失性固态存储单元以及添加和去除实体的拷贝的独家权力。这允许了维持底层数据的冗余性。当权力机构所有者失效、将要被退役或者超载时,该权力机构被转移到新的存储节点。暂态失效使得确保所有非故障机器就新权力机构位置达成一致是有意义的。由于暂态失效引起的含糊性可通过诸如Paxos之类的一致性协议、通过热-暖失效备援方案、经由远程系统管理员的手动干预或者通过本地硬件管理员(例如通过将失效的机器从集群中物理去除或者按下失效机器上的按钮)来实现。在一些实施例中,使用一致性协议,并且失效备援是自动的。如果在太短的时间段中发生太多的失效或复制事件,则根据一些实施例系统进入自我保护模式并且停止复制和数据移动活动,直到管理员干预为止。
由于权力机构在存储节点之间被传送并且权力机构所有者在其权力机构中更新实体,所以系统在存储节点和非易失性固态存储单元之间传送消息。对于持续性消息,具有不同目的的消息是不同类型的。取决于消息的类型,系统维持不同的排序和耐久性保证。随着持续性消息被处理,消息被临时存储在多个耐久和非耐久存储硬件技术中。在一些实施例中,消息被存储在RAM、NVRAM中和NAND闪存设备上,并且各种协议被使用来对每个存储介质进行高效使用。时延敏感客户端请求可被留存在复制的 NVRAM中,然后是NAND中,而后台重平衡操作被直接留存到NAND。
持续性消息在被发送之前被持续性存储。这允许了系统在即使有失效和组件更换的情况下也继续服务客户端请求。虽然许多硬件组件包含对系统管理员、制造者、硬件供应链和持续监视质量控制基础设施可见的唯一识别符,但在基础设施地址之上运行的应用虚拟化了地址。这些虚拟化地址在存储系统的寿命期间不变化,无论有什么组件失效和更换。这允许了随着时间的流逝更换存储系统的每个组件,而无需客户端请求处理的重配置或破坏。
在一些实施例中,虚拟化地址被以充分的冗余性存储。连续监视系统将硬件和软件状态与硬件识别符关联起来。这允许了检测和预测由于故障组件和制造细节引起的失效。监视系统在一些实施例中还使得能够在失效发生之前通过将组件从关键路径去除来前瞻性地将权力机构和实体从受影响的设备转移开。
图3是示出存储节点150的内容和存储节点150的非易失性固态存储装置152的内容的多级框图。数据在一些实施例中被网络接口控制器 (NIC)202传输到和传输自存储节点150。每个存储节点150具有CPU 156,以及一个或多个非易失性固态存储装置152,如上所述。在图3中向下移动一个级别,每个非易失性固态存储装置152具有相对快速的非易失性固态存储器,例如非易失性随机访问存储器(NVRAM)204,以及闪速存储器206。在一些实施例中,NVRAM 204可以是不要求编程/擦除循环 (DRAM、MRAM、PCM)的组件,并且可以是可支持写入频率比存储器被读取的频率大得多的存储器。在图3中再向下移动一个级别,NVRAM204在一个实施例中被实现为高速易失性存储器,例如动态随机访问存储器(DRAM)216,由能量储备218作为后援。能量储备218提供充分的电力来在电力失效的情况下保持DRAM 216被供电足够长的时间以便内容被转移到闪速存储器206。在一些实施例中,能量储备218是电容器、超级电容器、电池或其他设备,其提供适当的能量供应,足以使得DRAM 216的内容在电力丢失的情况下能够被转移到稳定的存储介质。闪速存储器206被实现为多个闪存管芯222,它们可被称为闪存管芯222的封装或者闪存管芯222的阵列。应当明白闪存管芯222可按任意多种方式被封装,每个封装单个管芯、每个封装多个管芯(即,多芯片封装)、混合封装、封装为印刷电路板或其他基板上的裸芯、封装为密封管芯,等等。在示出的实施例中,非易失性固态存储装置152具有控制器212或其他处理器,以及耦合到控制器212的输入输出(I/O)端口210。I/O端口210耦合到闪存存储节点150的CPU 156和/或网络接口控制器202。闪存输入输出(I/O)端口220耦合到闪存管芯222,并且直接存储器访问单元 (DMA)214耦合到控制器212、DRAM 216和闪存管芯222。在示出的实施例中,I/O端口210、控制器212、DMA单元214和闪存I/O端口220 实现在可编程逻辑器件(PLD)208(例如现场可编程门阵列(FPGA)) 上。在这个实施例中,每个闪存管芯222具有被组织为十六kB(千字节) 页224的页,以及寄存器226,通过该寄存器226可向闪存管芯222写入数据或从闪存管芯222读取数据。在另外的实施例中,其他类型的固态存储器被使用来取代或附加于在闪存管芯222内图示的闪速存储器。
存储集群160在本文公开的各种实施例中可与一般的存储阵列形成对照。存储节点150是创建存储集群160的集合的一部分。每个存储节点 150拥有一片数据和提供该数据所要求的计算。多个存储节点150合作来存储和取回数据。一般存储阵列中使用的储存存储器或存储设备没有那么参与处理和操纵数据。存储阵列中的储存存储器或存储设备接收读取、写入或擦除数据的命令。存储阵列中的储存存储器或存储设备不知晓它们所嵌入在的更大系统,或者数据意味着什么。存储阵列中的储存存储器或存储设备可包括各种类型的储存存储器,例如RAM、固态驱动器、硬盘驱动器,等等。本文描述的存储单元152具有同时活跃并且起到多个作用的多个接口。在一些实施例中,存储节点150的一些功能被转移到存储单元 152中,将存储单元152变换成存储单元152和存储节点150的组合。将计算(相对于存储数据)放置到存储单元152中会将此计算放置得更靠近数据本身。各种系统实施例具有能力不同的存储节点层的层次体系。与之对照,在存储阵列中,控制器拥有并知道关于该控制器在架子或存储设备中管理的所有数据的所有事情。在存储集群160中,如本文所述,多个存储单元152和/或存储节点150中的多个控制器以各种方式合作(例如,为了纠删编码、数据分片、元数据通信和冗余、存储容量扩展或收缩、数据恢复,等等)。
图4示出了存储服务器环境,其使用图1-图3的存储节点150和存储单元152的实施例。在这个版本中,每个存储单元152具有在机箱138 (参见图1)中的PCIe(快速外围组件互连)板上的例如控制器212(参见图3)这样的处理器、FPGA(现场可编程门阵列)、闪速存储器206和 NVRAM 204(其是由超级电容器后援的DRAM 216,参见图2和图3)。存储单元152可实现为包含存储的单个板,并且可以是机箱内部的最大可容忍失效域。在一些实施例中,最多两个存储单元152可失效并且设备将继续而没有数据丢失。
物理存储在一些实施例中基于应用使用被划分成命名域。NVRAM 204是存储单元152DRAM 216中的保留存储器的连续块,并且由NAND 闪存后援。NVRAM 204在逻辑上被划分成多个存储器区域,作为卷轴被写入两个(例如,spool_region)。NVRAM 204卷轴内的空间由每个权力机构512独立管理。每个设备向每个权力机构512提供某个量的存储空间。该权力机构512还管理该空间内的寿命和分配。卷轴的示例包括分布式事务或概念。当存储单元152的主电力失效时,板上超级电容器提供短持续时间的电力保持。在这个保持间隔期间,NVRAM 204的内容被冲刷到闪速存储器206。在下次加电时,从闪速存储器206恢复NVRAM204 的内容。
至于存储单元控制器,逻辑“控制器”的责任被分布在包含权力机构 512的每个刀片上。逻辑控制的这个分布在图4中被示为主机控制器 402、中层控制器404和(一个或多个)存储单元控制器406。控制平面和存储平面的管理被独立对待,但一些部分可在物理上共同位于同一刀片上。每个权力机构512实际上充当独立控制器。每个权力机构512提供其自己的数据和元数据结构、其自己的后台工人并且维护其自己的生命周期。
图5是刀片502硬件框图,利用图4的存储服务器环境中的图1-图3 的存储节点150和存储单元152的实施例示出了控制平面504、计算和存储平面506、508和与底层物理资源交互的权力机构512。控制平面504被划分成若干个权力机构512,权力机构512可使用计算平面506中的计算资源来在任何刀片502上运行。存储平面508被划分成一组设备,每个设备提供对闪存206和NVRAM 204资源的访问。
在图5的计算和存储平面506、508中,权力机构512与底层物理资源 (即,设备)交互。从权力机构512的角度来看,其资源被分条在所有物理设备上。从设备的角度来看,其向所有权力机构512提供资源,无论权力机构恰巧在何处运行。每个权力机构512分配了或者被分配了存储单元 152中的储存存储器的一个或多个分区510,例如闪速存储器206和NVRAM 204中的分区510。每个权力机构512使用属于它的这些分配的分区510,用于写入或读取用户数据。权力机构可与系统的不同量的物理存储相关联。例如,一个权力机构512在一个或多个存储单元152中可比一个或多个其他权力机构512具有更大数目的分区510或更大大小的分区 510。
图6示出了NAND闪速存储器中常见的示例位线602和串联晶体管电路。作为对照,NOR闪速存储器具有并联的浮栅晶体管,并且NAND闪速存储器具有串联的浮栅晶体管。读取NAND串联电路包括将字线之一提升到被擦除的浮栅晶体管的阈值之上,并且将其他字线提升到被编程的浮栅晶体管的阈值之上。如果所选浮栅晶体管被编程,则该晶体管不导通,并且位线不通过串联电路被放电。如果所选浮栅晶体管不被编程,则该晶体管导通,并且位线通过串联电路被放电。
图7描绘了3D NAND闪存,其可随着时间的流逝累积静电电荷。在这种类型的闪速存储器中,图6中描绘的串联晶体管电路被构造成列 702,在图7中作为示例示出了几列。应当明白,附图不是按比例的,并且实际3D闪速存储器密集得多。静电电荷可在3D NAND闪存中的各种位置中累积,破坏读取操作并且导致增加的差错。累积的静电电荷产生电场,这影响被编程和未被编程的浮栅晶体管的阈值。
图8是3D NAND闪速存储器的比特差错率802与时间的图线。读取闪速存储器的一个区块释放累积的静电电荷并且使得比特差错率802从在静电电荷存在时看到的升高水平回到优选水平。在一些实施例中,通过每三分钟读取整个存储系统中的每个闪速存储器管芯中的每个区块来最小化比特差错率。虽然此机制可起到降低比特差错率的作用,但这么频繁地读取每个闪速存储器管芯中的每个区块不会随着储存存储器的量增大而良好地缩放。另外,读取每个区块增大读取时延和常规I/O操作的操作竞争,因为每个区块的读取占用系统带宽。下文进一步描述的实施例对于3D NAND闪速存储器的哪些区块被读取是有选择的。
图9是固态存储装置的实施例的框图,其具有循环经过对于由数据结构904指示的闪速存储器区块的后台读取操作的定序器902。在这个示例中,这些特征是在包括多个存储节点150和具有闪速存储器206的多个存储单元152的存储集群中示出的,但容易对诸如存储阵列、固态驱动器等等之类的其他类型的存储系统设计另外的实施例。存储节点150的处理器 156确定应当刷新哪些区块,并且向存储单元152的NVRAM 204中的数据结构904写入关于这些区块的信息,例如地址。在如图1-图9所示的联网存储集群中,各种存储节点150在为了刷新而设置闪速存储器206的区块时可与各种存储单元152通信。对于刷新哪些区块的确定是动态的,并且数据结构904可在其他区块被识别用于刷新操作时根据需要被更新或者按规律的间隔被更新。在一个实施例中,数据结构904包括循环队列,从而旧的条目随着新的条目被添加而离开或被覆写。
例如,存储节点150可接收对读取文件的请求,并且用于该文件的索引节点的权力机构168(参见图2)可在读取文件的同时确定为了低比特差错率要刷新哪些区块,并且将关于这些区块的信息写入到数据结构 904。在一些实施例中,用于该文件的数据片段的范围的权力机构168可确定要刷新哪些区块,并且将关于这些区块的信息并行写入到各种存储单元152中的数据结构904。作为区块选择的另一示例,存储节点150中的处理器156可确定闪速存储器206的哪些区块具有文件系统元数据,并且将关于这些区块的信息写入到数据结构904和存储单元152。对于闪速存储器的区块的刷新,系统可以类似的方式推荐数据或元数据的其他部分。
在一些实施例中,要被刷新的区块的列表例如被存储节点150的处理器构建在不同的刀片502上(参见图5),并且随后被向下转移到存储单元152(例如,转移到存储单元硬件,例如PLD 208或FPGA)。使用 DMA单元214的直接存储访问将区块的列表的内容转移到每个存储单元 152中的PLD 208。一旦在PLD 208中,每个存储单元152中的闪存控制器212就溯源相关区块来添加到特定于该存储单元152的刷新列表。
参考图2、图3和图9,存储单元152中的控制器212随后指挥定序器 902根据数据结构904中的信息顺序经过对区块的后台读取。在示出的实施例中,仲裁器906在读取操作、写入操作、擦除操作以及可能其他前台或后台操作(例如后台维护操作)和由定序器902发出的刷新后台读取之间进行仲裁。例如,读取和写入操作可被赋予比擦除操作和后台刷新操作更高的优先级。仲裁器与闪存I/O 220通信,闪存I/O 220进而与闪速存储器206通信,如上文参考图3所述。与用户数据读取不同,为后台刷新操作读出的数据值在一些实施例中可被无视并且不被传送出存储单元152。
在图9所示的实施例中,存储单元152的控制器212和存储节点150 的处理器156都可与存储单元152中的NVRAM 204直接通信。定序器 902在一些实施例中可实现为硬件引擎,例如实现在现场可编程门阵列 (FPGA)或可编程逻辑器件(PLD)中的状态机中。另外,在一些实施例中,定序器902在预定的时间间隔内对后台读取循环定序,该时间间隔例如是由定时器确定的或者由数据结构904中的条目的数目确定的。为了设置该时间间隔,存储节点150的处理器156可将这种时间间隔传达给存储单元152的控制器212,控制器212随后在一些实施例中可根据该时间间隔来设置定序器902。
图10是根据一些实施例的刷新3D NAND闪速存储器的方法的流程图,其可在图1-图9的存储集群中实现,或者在存储阵列、固态存储装置或存储系统中实现。该方法可由一个或多个处理器(例如,执行软件)和/ 或硬件引擎或者固件或者其组合实现。在动作1002中,为刷新循环确定时间间隔。在一些实施例中,该时间间隔可基于对3D闪速存储器的制造者推荐、实验室测试或者通过系统诊断来经验地确定。在一些实施例中,后台读取可基于响应于随着时间跟踪的原始比特差错计数的基于时间的增大的基于时间的刷新。从而,在一些实施例中,后台读取的刷新周期可基于此原始比特差错计数跟踪而自适应。在动作1004中,为刷新识别3D闪速存储器的区块。系统可识别很快或最终将为基于读取请求的文件读取被读取的区块,或者识别具有文件系统元数据的区块,等等。在动作1006 中,关于区块的识别信息被写入到数据结构。该信息可以包括区块识别符、地址、指针等等。在动作1008中,根据数据结构的内容顺序经过对所识别的区块的后台读取。例如,定序器或其他硬件引擎或者固件引擎或软件引擎可被编程以数据结构的内容或指向数据结构,并且发出后台刷新读取操作的序列。在动作1010中,读取操作、写入操作、擦除操作、后台维护操作和用于刷新3D闪速存储器区块的后台读取被仲裁。仲裁可以是单通道的、多通道的、硬连线的或者基于规则可编程的,等等。对所识别的区块的后台读取起到释放累积的静电电荷并且减少来自3D闪速存储器的原始比特差错的作用。在动作1012中,按仲裁那样利用闪速存储器执行操作。应当明白,前台任务指的是应当与对客户端可见的任何动作顺序、并行或一致执行的任务,而诸如后台刷新读取之类的后台任务是可立即或者稍后执行的任务,但不一定需要在对客户端可见的动作(例如,对客户端的确认、回复或其他响应)之前执行。
应当明白,本文描述的方法可利用数字处理系统(例如传统的通用计算机系统)来执行。作为替换可使用被设计或编程为只执行一个功能的专用计算机。图11是示出可实现本文描述的实施例的示范性计算设备的图示。图11的计算设备可用于根据一些实施例执行3D NAND闪速存储器的智能刷新的功能的实施例。该计算设备包括通过总线1105耦合到存储器 1103的中央处理单元(CPU)1101,以及大容量存储设备1107。大容量存储设备1107表示持续性数据存储设备,例如软盘驱动器或固定盘驱动器,其在一些实施例中可以是本地或远程的。存储器1103可包括只读存储器、随机访问存储器,等等。存在于计算设备上的应用在一些实施例中可被存储在诸如存储器1103或大容量存储设备1107之类的计算机可读介质上或经由计算机可读介质来访问。应用也可采取经由计算设备的网络调制解调器或其他网络接口来调制访问的调制电子信号的形式。应当明白, CPU 1101在一些实施例中可实现在通用处理器、专用处理器或者特别编程的逻辑器件中。
显示器1111通过总线1105与CPU 1101、存储器1103和大容量存储设备1107通信。显示器1111被配置为显示与本文描述的系统相关联的任何视觉化工具或报告。输入/输出设备1109耦合到总线1105以便将命令选择中的信息传达到CPU 1101。应当明白,去往和来自外部设备的数据可通过输入/输出设备1109来传达。CPU 1101可被定义为执行本文描述的功能以使能参考图1-图10描述的功能。实现此功能的代码在一些实施例中可被存储在存储器1103或大容量存储设备1107内供诸如CPU 1101之类的处理器执行。计算设备上的操作系统可以是MS DOSTM、MS- WINDOWSTM、OS/2TM、UNIXTM、LINUXTM或其他已知的操作系统。应当明白,本文描述的实施例也可与利用物理计算资源实现的虚拟化计算系统相集成。应当理解,虽然本文中可使用第一、第二等术语来描述各种步骤或计算,但这些步骤或计算不应当受这些术语所限。这些术语只是用于区分一个步骤或计算与另一个步骤或计算。例如,第一计算可被称为第二计算,并且类似地,第二步骤可被称为第一步骤,而不脱离本公开的范围。就本文使用的而言,术语“和/或”和“/”符号包括关联的列出项目中的一个或多个的任意项和所有组合。
按照本文使用的,单数形式“一”和“该”打算也包括复数形式,除非上下文明确地另有指示。还要理解,术语“包括”和/或“包含”当在本文中使用时指明了所记述的特征、整数、步骤、操作、元素和/或组件的存在,但并不排除一个或多个其他特征、整数、步骤、操作、元素、组件和/或其群组的存在或添加。因此,本文使用的术语只是为了描述特定实施例,而并不意欲作出限制。
还应注意,在一些替换实现方式中,所记载的功能/动作可不按图中记载的顺序发生。例如,取决于所涉及的功能/动作,接连示出的两幅图事实上可基本同时执行,或者有时可按相反顺序执行。
了解了上述实施例,应当理解这些实施例可采用涉及计算机系统中存储的数据的各种由计算机实现的操作。这些操作是要求对物理量的物理操纵的那些。通常(但并非一定),这些量采取能够被存储、传送、组合、比较和以其他方式操纵的电信号或磁信号的形式。另外,执行的操纵经常被用诸如产生、识别、确定或比较之类的术语来称呼。本文描述的形成实施例的一部分的任何操作是有用的机器操作。实施例也涉及用于执行这些操作的设备或装置。装置可以是为所要求的目的特别构造的,或者装置可以是被存储在计算机中的计算机程序选择性激活或配置的通用计算机。具体地,各种通用机器可与根据本文的教导编写的计算机程序一起使用,或者构造更专门的装置来执行要求的操作可能是更方便的。
模块、应用、层、代理或其他方法可操作实体可实现为硬件、固件或者执行软件的处理器,或者其组合。应当明白,在本文公开了基于软件的实施例的情况下,该软件可实现在诸如控制器之类的物理机器中。例如,控制器可包括第一模块和第二模块。控制器可被配置为执行例如方法、应用、层或代理的各种动作。
实施例也可实现为非暂态计算机可读介质上的计算机可读代码。计算机可读介质是任何能够存储以后可被计算机系统读取的数据的数据存储设备。计算机可读介质的示例包括硬驱动器、附网存储(network attached storage,NAS)、只读存储器、随机访问存储器、CD-ROM、CD-R、CD- RW、磁带以及其他光学和非光学数据存储设备。计算机可读介质也可分布在由网络耦合的计算机系统上,以使得计算机可读代码被以分布方式来存储和执行。本文描述的实施例可利用各种计算机系统配置来实现,这些配置包括手持设备、平板设备、微处理器系统、基于微处理器的或者可编程的消费型电子产品、小型计算机、大型计算机等等。实施例也可在分布式计算环境中实现,其中任务由通过基于线路的网络或无线网络链接的远程处理设备执行。
虽然方法操作是按特定顺序来描述的,但应当理解在描述的操作之间可执行其他操作,可以调整描述的操作以使得它们在略微不同的时间发生,或者可将描述的操作分布在允许与处理相关联的各种间隔的处理操作的发生的系统中。
在各种实施例中,本文描述的方法和机制的一个或多个部分可形成云计算环境的一部分。在这种实施例中,可根据一个或多个各种模型以服务的形式通过因特网提供资源。这种模型可包括基础设施即服务 (Infrastructure as a Service,IaaS)、平台即服务(Platform as a Service, PaaS)和软件即服务(Software as a Service,SaaS)。在IaaS中,计算机基础设施被作为服务交付。在这种情况下,计算设备一般由服务提供者拥有和操作。在PaaS模型中,软件工具和开发者用来开发软件解决方案的底层设备可被作为服务提供并且被服务提供者容宿。SaaS通常包括服务提供者根据需要将软件作为服务许可。服务提供者可容宿软件,或者可在给定的一段时间中将软件部署到客户。上述模型的许多组合是可能的并且被设想到了。
各种单元、电路或其他组件可被描述或在权利要求中记载为“被配置为”或“可配置为”执行一个或多个任务。在这样的上下文中,短语“被配置为”或“可配置为”用于通过表明该单元/电路/组件包括在操作期间执行该一个或多个任务的结构(例如,电路)来暗示结构。这样,即使当指定的单元/电路/组件当前未工作时(例如,未开启),也可以说该单元/电路/组件被配置为执行该任务,或者可配置为执行该任务。结合“被配置为”或“可配置为”语句一起使用的单元/电路/组件包括硬件——例如,电路、存储可执行来实现该操作的程序指令的存储器,等等。明确希望,记载单元/电路/ 组件“被配置为”执行一个或多个任务或者“可配置为”执行一个或多个任务不会对于该单元/电路/组件援用35U.S.C.112,第六款。此外,“被配置为”或“可配置为”可包括被软件和/或固件(例如,FPGA或者执行软件的通用处理器)操纵来以能够执行所述的(一个或多个)任务的方式操作的通用结构(例如,通用电路)。“被配置为”还可包括使制造过程(例如,半导体制造设施)适合于制造适于实现或执行一个或多个任务的装置(例如,集成电路)。“可配置为”并不打算应用到空白介质、未编程的处理器或未编程的通用计算机或者未编程的可编程逻辑器件、可编程门阵列或其他未编程的设备,除非伴随着给予未编程设备被配置为执行公开的(一个或多个)功能的能力的编程介质。
出于说明目的,以上描述是参考特定实施例来描述的。然而,以上的说明性论述并不打算是穷举性的或将本发明限制到所公开的精确形式。考虑到以上教导,许多修改和变化是可能的。选择和描述实施例是为了最好地说明实施例的原理及其实际应用,从而使得本领域的其他技术人员能够最好地利用实施例和可适合于所设想的特定用途的各种修改。因此,这里的实施例应被认为是说明性的而不是限制性的,并且本发明不限于本文给出的细节,而是可在所附权利要求的范围和等同物内被修改。

Claims (20)

1.一种用于处理闪速存储器的区块以减少来自所述闪速存储器的原始比特差错的方法,包括:
针对刷新操作识别所述闪速存储器的一个或多个区块;并且
作为所述刷新操作向所识别的区块发出后台读取。
2.如权利要求1所述的方法,其中,所述识别包括:
响应于接收到读取文件的请求,确定所述文件的索引节点;
确定属于所述文件的索引节点的数据部分;并且
确定所述闪速存储器的包括所述数据部分的一个或多个区块。
3.如权利要求1所述的方法,其中,所述识别包括:
确定所述闪速存储器的哪些区块包括文件系统元数据。
4.如权利要求1所述的方法,还包括:
将关于所识别的区块的信息写入到数据结构;
在对于用户数据或元数据的读取操作、对于用户数据或元数据的写入操作、后台维护操作、擦除操作和后台读取之间进行仲裁;并且其中所述发出是根据所述数据结构的。
5.如权利要求1所述的方法,其中,发出所述后台读取包括:
在预定时间间隔内循环所述后台读取,并且其中所述后台读取避免从所识别的区块对数据的任何转移。
6.如权利要求1所述的方法,还包括:
将关于所识别的区块的信息分布到多个数据结构,所述多个数据结构是可配置为发出所述后台读取的多个硬件引擎可访问的。
7.如权利要求4所述的方法,还包括:
利用关于另外的针对所述刷新操作的所识别区块的信息更新所述数据结构,并且其中所述闪速存储器是三维(3D)闪速存储器。
8.一种其上具有指令的有形非暂态计算机可读介质,所述指令当被处理器执行时使得该处理器执行一种方法,该方法包括:
针对刷新操作识别闪速存储器的多个区块;并且
将关于所识别的区块的信息写入到硬件引擎可访问的数据结构,所述硬件引擎对所识别的区块的后台读取定序来作为所述刷新操作。
9.如权利要求8所述的计算机可读介质,其中,所述方法还包括:
接收读取文件的请求;并且
确定属于所述文件的数据部分,其中识别所述多个区块包括确定所述闪速存储器的包括属于所述文件的数据部分的区块。
10.如权利要求8所述的计算机可读介质,其中,识别所述闪速存储器的多个区块包括识别所述闪速存储器的包括文件系统元数据的区块。
11.如权利要求8所述的计算机可读介质,其中,所述方法还包括:
将所述后台读取分布到与所述闪速存储器通信的多个通道,其中所述多个通道具有对用户数据的读取操作、元数据的读取操作、用户数据的写入操作、元数据的写入操作、后台维护操作、擦除操作和后台读取的仲裁。
12.如权利要求8所述的计算机可读介质,其中,所述方法还包括:
将时间间隔传达到硬件引擎,该硬件引擎根据所述时间间隔循环所述后台读取,并且其中所述后台读取避免从所识别的区块对数据的任何转移。
13.如权利要求8所述的计算机可读介质,其中,所述方法还包括:
针对所述刷新操作识别所述闪速存储器的另外区块;并且
利用关于所述另外区块的信息来更新所述数据结构。
14.一种存储系统,包括:
闪速存储器;
一个或多个处理器,可配置为针对刷新操作识别所述闪速存储器的区块,并且所述一个或多个处理器可配置为写入关于所识别的区块的信息;以及
硬件引擎,可配置为作为所述刷新操作根据所述信息对所识别的区块的后台读取定序。
15.如权利要求14所述的存储系统,其中,所述一个或多个处理器可配置为响应于接收到读取文件的请求而确定所述闪速存储器的哪些区块具有属于所述文件的数据部分。
16.如权利要求14所述的存储系统,其中,所述一个或多个处理器可配置为确定所述闪速存储器的哪些区块具有文件系统元数据。
17.如权利要求14所述的存储系统,还包括:
仲裁器,可配置为对于多个通道仲裁对于用户数据或元数据的读取操作、对于用户数据或元数据的写入操作、后台维护操作、擦除操作和后台读取;以及
另一存储器,可配置为保存数据结构,其中所述一个或多个处理器可配置为将关于所识别的区块的信息写入到所述数据结构。
18.如权利要求14所述的存储系统,其中,所述硬件引擎可配置为在预定时间间隔内对所述后台读取循环定序,并且其中所述后台读取无视读取的数据值。
19.如权利要求14所述的存储系统,还包括:
分布在整个所述存储系统中的多个硬件引擎;以及
分布在整个所述存储系统中的多个数据结构,所述多个数据结构的每一者与所述硬件引擎之一相关联。
20.如权利要求14所述的存储系统,还包括:
所述一个或多个处理器还可配置为针对所述刷新操作识别所述闪速存储器的另外区块并且可配置为更新关于所述另外区块的数据结构,并且其中所述闪速存储器是三维(3D)闪速存储器。
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