CN110060620A - Gate drive apparatus - Google Patents
Gate drive apparatus Download PDFInfo
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- CN110060620A CN110060620A CN201910451004.4A CN201910451004A CN110060620A CN 110060620 A CN110060620 A CN 110060620A CN 201910451004 A CN201910451004 A CN 201910451004A CN 110060620 A CN110060620 A CN 110060620A
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention relates to a kind of gate drive apparatus, which includes multiple shift register circuits.The shift register circuit includes: output-stage circuit, receives and provides that grid is low or high voltage charges to generate gate drive signal to output end according to control signal；Compensation circuit, wherein transistor receives rear class gate drive signal and control signal；First voltage adjuster, according to mode select signal, to provide, grid is low or high voltage is to adjust control signal；Second voltage adjuster, according to switching signal and reverse frequency signal to provide prime gate drive signal or initial pulse signal to adjust control signal；Grid is low or high voltage is to adjust control signal to provide for tertiary voltage adjuster, foundation mode select signal and control signal；4th voltage adjuster, according to reverse frequency signal to adjust control signal.
Description
Technical field
The present invention relates to a kind of gate drive apparatus, especially a kind of gate drive apparatus for showing equipment.
Background technique
There are many products in recent years is integrated in glass for the gate driving circuit (Gate driver) in circuit of display driving
On glass, gate driving (Gate-Driver-on-Array, GOA) circuit as on array.And gate driving electricity on the array
Road has many advantages, can reduce the width of the frame of display panel, to achieve the effect that narrow frame, and then effectively drops
The design area of the internal circuit of low display.
In the display device, since the display picture that display panel is presented is easy by the driving crystal in pixel circuit
The conducting voltage of pipe influences, and the quality for showing picture is caused to reduce.Therefore, gate driving circuit needs make same in compensated stage
One column pixel switch is switched on or is disconnected simultaneously, to compensate movement to the driving transistor.Then, gate driving electricity
Road needs that the pixel switch is connected by column in data write phase, by pixel voltage (or pixel data) write-in to correspondence
Pixel circuit in.
In other words, how when gate drive apparatus operates in compensated stage, it can effectively generate consistent grid and drive
Dynamic signal, and in data write phase, the gate drive signal can be generated, in order to promote gate drive apparatus
Efficiency, will be the important topic of relevant technical staff in the field.
Summary of the invention
The present invention provides a kind of gate drive apparatus, and each gate drive signal can be made to be caused simultaneously in compensated stage
Can, and so that each gate drive signal is sequentially enabled in write phase, to promote the efficiency of gate drive apparatus.
Gate drive apparatus of the invention includes multiple shift register circuits.Multiple shift register circuits are serially connected coupling
Connect, generate multiple gate drive signals respectively, wherein N grades of shift register circuit include output-stage circuit, compensation circuit with
And first to fourth voltage adjuster.Output-stage circuit has the first control terminal and the second control terminal to receive the first control respectively
Signal processed and second control signal, according to first control signal and second control signal to provide grid low-voltage or grid
High voltage charges to generate N grades of gate drive signals to output end.Compensation circuit is coupled to the first control terminal, wherein compensation electricity
Road includes capacitor and the first transistor.Capacitor is coupled between the first control terminal and first node.The of the first transistor
One end receives rear class gate drive signal, and the second end of the first transistor is coupled to first node, the control terminal of the first transistor
Receive first control signal.First voltage adjuster is coupled to the first control terminal, according to first mode selection signal and second
Mode select signal is to provide grid low-voltage or gate high-voltage to adjust first control signal.The coupling of second voltage adjuster
To the first control terminal, according to switching signal and reverse frequency signal to provide prime gate drive signal or initial pulse signal
To adjust first control signal.Tertiary voltage adjuster is coupled between the first control terminal and the second control terminal, according to second
Mode select signal and first control signal are to provide grid low-voltage or gate high-voltage to adjust second control signal.The
Four voltage adjusters are coupled to the second control terminal, according to reverse frequency signal to adjust second control signal.
Shift register circuit based on above-mentioned, of the invention gate drive apparatus can make output stage in compensated stage
N caused by circuit grades of gate drive signal and rear class gate drive signal synchronize output.And in write phase,
Make N caused by output-stage circuit grades of gate drive signal with rear class gate drive signal being exported sequentially, use promotion
The efficiency of gate drive apparatus.
Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail, but not as a limitation of the invention.
Detailed description of the invention
Fig. 1 is the circuit diagram according to N grades of the shift register circuit of one embodiment of the invention.
Fig. 2 is the waveform diagram according to N grades of the shift register circuit of one embodiment of the invention.
Fig. 3 be according to one embodiment of the invention N grades of shift register circuit compensated stage the first sub-stage
Circuit diagram.
Fig. 4 be according to one embodiment of the invention N grades of shift register circuit compensated stage the second sub-stage
Circuit diagram.
Fig. 5 be according to one embodiment of the invention N grades of shift register circuit compensated stage third sub-stage
Circuit diagram.
Fig. 6 be according to one embodiment of the invention N grades of shift register circuit write phase the first sub-stage
Circuit diagram.
Fig. 7 be according to one embodiment of the invention N grades of shift register circuit write phase the second sub-stage
Circuit diagram.
Fig. 8 is to keep the circuit in stage to illustrate in voltage according to N grades of the shift register circuit of one embodiment of the invention
Figure.
Wherein, appended drawing reference:
100: shift register circuit
110: output-stage circuit
120: compensation circuit
130~160: voltage adjuster
CT1~CT2: control terminal
CS1~CS2: control signal
CHA: switching signal
C1: capacitor
G [N-1]~G [N+1]: gate drive signal
M1~M14: transistor
OUT: output end
P1: node
VGL: grid low-voltage
VGH: gate high-voltage
SS1~SS2: mode select signal
ST: initial pulse signal
TFR: during pixel
TC: compensated stage
TR: write phase
TVH: voltage is kept for the stage
TC_1~TC_3, TR_1~TR_2: sub-stage
V1~V5: voltage value
VA: voltage potential
XCLK: reverse frequency signal
Specific embodiment
Structural principle and working principle of the invention are described in detail with reference to the accompanying drawing:
" coupling (or connection) " word used in description of the invention full text (including claims) can refer to appoint
What direct or indirect connection means.For example, if it is described herein that first device coupling (or connection) is then answered in second device
This be construed as the first device can be directly connected to the second device or the first device can by other devices or
Certain connection means and be coupled indirectly to the second device.In addition, all possible places, use phase in the drawings and embodiments
Component, component, step with label represent same or like part.Identical label is used in different embodiments or uses identical use
The component of language, component, step can be with cross-referenced related descriptions.
Fig. 1 is the circuit diagram according to N grades of the shift register circuit of one embodiment of the invention.The grid of the embodiment of the present invention
Electrode driving device includes multiple shift register circuits, also, these shift register circuits are serially connected coupling each other, to divide
Multiple gate drive signals are not generated.Wherein, the shift register circuit 100 of Fig. 1 is N grades for indicating the gate drive apparatus
Shift register circuit, and above-mentioned N be positive integer.
In one embodiment of the invention, as shown in Figure 1, shift register circuit 100 includes output-stage circuit 110, mends
Repay circuit 120 and voltage adjuster 130~160.Wherein, output-stage circuit 110 includes transistor M1~M2.Transistor M1's
First end receives grid low-voltage VGL, and the second end of transistor M1 is coupled to output end OUT, and the control terminal of transistor M1 receives
Control signal CS1.The first end of transistor M2 is coupled to output end OUT, and the second end of transistor M2 receives gate high-voltage
The control terminal of VGH, transistor M2 receive control signal CS2.
Specifically, the output-stage circuit 110 of the present embodiment can be distinguished by control terminal CT1 and control terminal CT2
Receive control signal CS1 and control signal CS2.Also, output-stage circuit 110 can be according to control signal CS1 and control
Signal CS2 come make grid low-voltage VGL or gate high-voltage VGH to output end OUT carry out charging action, promote output-stage circuit
110 generate the pixel circuit of N grades of gate drive signal G [N] to rear end.
Then, compensation circuit 120 is coupled to control terminal CT1.Compensation circuit 120 includes capacitor C1 and transistor M3.Its
In, capacitor C1 is coupled between control terminal CT1 and node P1.Also, the first end of transistor M3 receives rear class gate driving
Signal G [N+1], the second end of transistor M3 are coupled to node P1, and the control terminal of transistor M3 receives control signal CS1.
On the other hand, voltage adjuster 130 is coupled to control terminal CT1.Voltage adjuster 130 includes transistor M4~M6.
Wherein, the first end of transistor M4 receives grid low-voltage VGL, and the second end of transistor M4 is coupled to control terminal CT1, transistor
The control terminal reception pattern selection signal SS1 of M4.The first end of transistor M5 receives gate high-voltage VGH, the control of transistor M5
End processed receives mode select signal SS2.The first end of transistor M6 is coupled to the second end of transistor M5, and the second of transistor M6
End is coupled to control terminal CT1, the control terminal reception pattern selection signal SS2 of transistor M6.Specifically, the voltage of the present embodiment
Adjuster 130 can be determined according to the state of mode select signal SS1 and mode select signal SS2 by grid low-voltage
VGL or gate high-voltage VGH are provided to control terminal CT1, use allow voltage adjuster 130 by grid low-voltage VGL or
Gate high-voltage VGH controls signal CS1 to adjust.
Then, voltage adjuster 140 is coupled to control terminal CT1.Voltage adjuster 140 includes transistor M7~M8.Wherein,
The first end of transistor M7 receives the control termination of prime gate drive signal G [N-1] or initial pulse signal ST, transistor M7
Receive reverse frequency signal XCLK.The first end of transistor M8 is coupled to the second end of transistor M7, the second end coupling of transistor M8
It is connected to control terminal CT1, the control terminal of transistor M8 receives switching signal CHA.Specifically, the voltage adjuster of the present embodiment
140 can determine prime gate drive signal G [N-1] or be risen according to switching signal CHA and reverse frequency signal XCLK
Initial pulse signal ST is provided to control terminal CT1, and using allows voltage adjuster 140 to pass through prime gate drive signal G [N-1]
Or initial pulse signal ST controls signal CS1 to adjust.
Special one mentions, in the present embodiment, when shift register circuit 100 operates in compensated stage, voltage adjuster
140 can be such that transistor M8 is disconnected according to the switching signal CHA with high voltage potential.Whereby, defeated in compensated stage
The output state for the gate drive signal G [N] that grade circuit 110 is exported out can not be by prime gate drive signal G's [N-1]
Output state and be affected.
On the other hand, voltage adjuster 150 is coupled between control terminal CT1 and control terminal CT2.Voltage adjuster 150
Including transistor M9~M12.Wherein, the first end of transistor M9 receives grid low-voltage VGL, the second end coupling of transistor M9
To control terminal CT2, the control terminal reception pattern selection signal SS2 of transistor M9.The first end of transistor M10 is coupled to control terminal
The second end of CT2, transistor M10 receive gate high-voltage VGH, and the control terminal of transistor M10 receives control signal CS1.Crystal
The first end of pipe M11 is coupled to control terminal CT1, and the control terminal of transistor M11 is coupled to control terminal CT2.The first of transistor M12
End is coupled to the second end of transistor M11, and the second end of transistor M12 receives gate high-voltage VGH, the control of transistor M12
End is coupled to control terminal CT2.Specifically, the voltage adjuster 150 of the present embodiment can according to mode select signal SS2 and
Signal CS1 is controlled to determine grid low-voltage VGL or gate high-voltage VGH being provided to control terminal CT2, using adjusts voltage
Device 150 can adjust control signal CS2 by grid low-voltage VGL or gate high-voltage VGH.
Then, voltage adjuster 160 is coupled to control terminal CT2.Voltage adjuster 160 includes transistor M13~M14.Its
In, the first end and control terminal of transistor M13 receives reverse frequency signal XCLK jointly.The first end of transistor M14 couples
To the second end of transistor M13, the second end of transistor M14 is coupled to control terminal CT2, and the control terminal of transistor M14 receives anti-
To frequency signal XCLK.Specifically, the voltage adjuster 160 of the present embodiment can be adjusted according to reverse frequency signal XCLK
Control signal CS2.It is noted that the transistor M13~M14 of the present embodiment can be according to diode configuration (Diode
Connection connection type) forms a diode.Wherein, cathode (that is, the of transistor M13 of the diode
One end) reverse frequency signal XCLK is received, the anode (that is, second end of transistor M14) of the diode is coupled to control terminal
CT2.Incidentally, the transistor M1~M14 of the present embodiment be by taking P-type transistor as an example, but the embodiment of the present invention not with
This is limited.
Fig. 2 is the waveform diagram according to N grades of the shift register circuit of one embodiment of the invention.As shown in Fig. 2,
In the present embodiment, during a pixel of shift register circuit 100 TFR can divide into compensated stage TC, write phase TR with
And voltage keeps stage TVH, and compensated stage TC, write phase TR and voltage keep stage TVH not overlap each other.
Wherein, after compensated stage TC, voltage keeps stage TVH enable after write phase TR for write phase TR enable.
Fig. 3 be according to one embodiment of the invention N grades of shift register circuit compensated stage the first sub-stage
Circuit diagram.Referring to Fig. 2 and Fig. 3, specifically, when shift register circuit 100 operates in compensated stage TC's
When the first sub-stage TC_1, the frequency generator (not drawing) for being external in shift register circuit 100 can be provided with high voltage
The frequency signal CLK of current potential and reverse frequency signal XCLK with low voltage potential is to shift register circuit 100.In addition,
Shift register circuit 100 can set mode select signal SS1 as low voltage potential state, and set mode select signal SS2
For high voltage potential state.
Specifically, grid low-voltage VGL can be sent to by voltage adjuster 130 according to mode select signal SS1
Control terminal CT1 uses the voltage potential for drawing low control signal CS1.Also, voltage adjuster 120 can be according to the control being pulled low
Signal CS1 and be switched on.At the same time, shift register circuit 100 can set switching signal CHA as high voltage potential state,
So that transistor M8 can be disconnected.In the case, voltage adjuster 140 will be unable to transmission prime gate drive signal G [N-
1] or initial pulse signal ST to control terminal CT1.Whereby, the present embodiment can effectively completely cut off prime gate drive signal G [N-
1] or initial pulse signal ST and control signal CS1 between influence.
On the other hand, in the first sub-stage TC_1, voltage adjuster 160 can according to reverse frequency signal XCLK and by
Conducting, and charging action is carried out to control signal CS2.Then, voltage adjuster 150 can be according to the control signal being pulled low
Gate high-voltage VGH is sent to control terminal CT2 by CS1, and then control signal CS2 is drawn high to the electricity of gate high-voltage VGH
Piezoelectric position.
In other words, in the present embodiment, when shift register circuit 100 operates in the first sub-stage TC_1, output stage electricity
Road 110 can be provided according to the control signal CS1 being pulled low grid low-voltage VGL with to output end OUT carry out charging action,
And output-stage circuit 110 is set to pass through output end OUT to generate N grades of grid of the voltage potential with grid low-voltage VGL
Pole driving signal G [N].
Fig. 4 be according to one embodiment of the invention N grades of shift register circuit compensated stage the second sub-stage
Circuit diagram.Referring to Fig. 2 and Fig. 4, specifically, when shift register circuit 100 operates in the second sub-stage TC_
When 2, shift register circuit 100 can set mode select signal SS1 and mode select signal SS2 is all high voltage potential shape
State.Also, external frequency generator (not drawing) can provide frequency signal CLK and reverse frequency with periodical transition
Signal XCLK is to shift register circuit 100.
Specifically, voltage adjuster 130 can according to mode select signal SS1 and mode select signal SS2 and by
It disconnects, and voltage adjuster 140 can be persistently disconnected according to switching signal CHA.Then, compensation circuit 120 can be according to
It is switched on according to the control signal CS1 being pulled low.It is noted that due to rear class gate drive signal G [N+1] operation at this time
On the voltage potential of grid low-voltage VGL, therefore, the voltage value on node P1 can be according to rear class gate drive signal G [N+
1] synchronously it is pulled down to the voltage potential of grid low-voltage VGL.In this way, which compensation circuit 120 can be by capacitor C1
Coupling effect so that the voltage potential of control signal CS1 is adjusted to the voltage value and a voltage value V1 of grid low-voltage VGL
Summation.Should be noted, the voltage value V1 can be expressed as the conducting voltage of transistor M4 | VTH4 | with via coupling
The voltage difference between a deviant △ V after effect.Also that is, the voltage potential of control signal CS1 at this time is VGL+V1=
VGL+|VTH4|-△V。
On the other hand, voltage adjuster 160 is periodically disconnected according to reverse frequency signal XCLK.Also, voltage
Adjuster 150 can provide gate high-voltage VGH to control terminal CT2 according to the control signal CS1 being pulled low, so that control is believed
The voltage potential of number CS2 can be maintained at the voltage value of gate high-voltage VGH.
In other words, in the present embodiment, when shift register circuit 100 operates in the second sub-stage TC_2, output stage electricity
Road 110 can be provided according to the control signal CS1 being pulled low grid low-voltage VGL with to output end OUT carry out charging action,
And output-stage circuit 110 is set to pass through output end OUT to generate N grades of grid of the voltage potential with grid low-voltage VGL
Pole driving signal G [N].
Fig. 5 be according to one embodiment of the invention N grades of shift register circuit compensated stage third sub-stage
Circuit diagram.Referring to Fig. 2 and Fig. 5, specifically, when shift register circuit 100 operates in compensated stage TC's
When third sub-stage TC_3, shift register circuit 100 can set mode select signal SS1 and persistently be maintained at high voltage potential shape
State, and mode select signal SS2 is set as low voltage potential state.In addition, external frequency generator (not drawing) can be with
Frequency signal CLK with the high voltage potential and reverse frequency signal XCLK with low voltage potential is provided.
Specifically, voltage adjuster 130 can provide gate high-voltage VGH to control according to mode select signal SS2
End CT1 processed, and then the voltage potential for controlling signal CS1 is allow to be pulled to the voltage value of gate high-voltage VGH.It is same herein
When, voltage adjuster 120 can be disconnected according to the control signal CS1 being pulled up.Also, voltage adjuster 140 is according to switching
Signal CHA and lasting be disconnected.
On the other hand, voltage adjuster 160 can be switched on according to reverse frequency signal XCLK, to control signal
CS2 carries out charging action.Then, voltage adjuster 150 can provide grid low-voltage VGL according to mode select signal SS2
To control terminal CT2, so that the voltage potential of control signal CS2 is adjusted to the voltage value and a voltage value of grid low-voltage VGL
The summation of V2.Should be noted, the voltage value V2 can be expressed as the conducting voltage of transistor M9 | VTH9 |.Also that is, this
When control signal CS2 voltage potential be VGL+V2=VGL+ | VTH9 |.
In other words, in the present embodiment, when shift register circuit 100 operates in third sub-stage TC_3, output stage electricity
Road 110 can be provided according to the control signal CS2 being pulled low gate high-voltage VGH with to output end OUT carry out charging action,
And output-stage circuit 110 is set to pass through output end OUT to generate N grades of grid of the voltage potential with gate high-voltage VGH
Pole driving signal G [N].
Description according to above-mentioned Fig. 3 to Fig. 5, which can understand, to be learnt, in compensated stage TC, shift register circuit 100
It can be in such a way that switching signal CHA be set as high voltage potential state, to disconnect prime gate drive signal G [N-1]
It is sent to the path of control terminal CT1, and then makes caused by output-stage circuit 110 that gate drive signal G [N] will not be by preceding
Grade gate drive signal G [N-1] influence, and make gate drive signal G [N] can with rear class gate drive signal G [N+1] into
Row synchronism output uses the efficiency for promoting display gate drive apparatus.
Fig. 6 be according to one embodiment of the invention N grades of shift register circuit write phase the first sub-stage
Circuit diagram.Referring to Fig. 2 and Fig. 6, specifically, when shift register circuit 100 operates in write phase TR's
When the first sub-stage TR_1, shift register circuit 100 can set mode select signal SS1 and mode select signal SS2 all
For high voltage potential state.External frequency generator (not drawing) can provide the frequency signal CLK with high voltage potential
And the reverse frequency signal XCLK with low voltage potential is to shift register circuit 100.
Specifically, voltage adjuster 130 can according to mode select signal SS1 and mode select signal SS2 and by
It disconnects.Also, voltage adjuster 120 can be switched on according to the control signal CS1 being pulled low.Different from compensated stage TC's
It is that in write phase TR, shift register circuit 100 can set switching signal CHA as low voltage potential state, so that voltage
Adjuster 140 can be switched on according to switching signal CHA and reverse frequency signal XCLK.
In the case, voltage adjuster 140 can be by prime gate drive signal G [N-1] or initial pulse signal ST
Be sent to control terminal CT1 so that the voltage potential of control signal CS1 can be pulled down to the voltage value of grid low-voltage VGL with
The summation of one voltage value V3.Should be noted, the voltage value V3 can be expressed as the conducting voltage of transistor M7 | VTH7 |.
Also that is, the voltage potential of control signal CS1 at this time is VGL+V3=VGL+ | VTH7 |.
On the other hand, in the first sub-stage TR_1, voltage adjuster 160 can be according to the reverse frequency signal being pulled down
XCLK and it is lasting be switched on, and the carry out charging action lasting to control signal CS2.Then, voltage adjuster 150 can be according to
Gate high-voltage VGH is sent to control terminal CT2 according to the control signal CS1 being pulled down, so that the voltage electricity of control signal CS2
Position can be pulled to the voltage value of gate high-voltage VGH.
In other words, in the present embodiment, when shift register circuit 100 operates in the first sub-stage TR_1, output-stage circuit
110 can generate N grades of gate drive signal G [N] according to the control signal CS1 being pulled low.Wherein, N grades of grid at this time
The voltage potential of pole driving signal G [N] is the voltage value of grid low-voltage VGL and the summation of a voltage value V4.It should be noted
It is that the voltage value V4 can be expressed as the conducting voltage of transistor M7 | VTH7 | and the conducting voltage of transistor M1 | VTH1
|.Also that is, the voltage potential of gate drive signal G [N] at this time is VGL+V4=VGL+ | VTH7 |+| VTH1 |.
Fig. 7 be according to one embodiment of the invention N grades of shift register circuit write phase the second sub-stage
Circuit diagram.Referring to Fig. 2 and Fig. 7, specifically, when shift register circuit 100 operates in write phase TR's
When the second sub-stage TR_2, shift register circuit 100 can set mode select signal SS1 and mode select signal SS2 is held
It is continuous to be maintained high voltage potential state.External frequency generator (not drawing) can provide the letter of the frequency with low voltage potential
Number CLK and reverse frequency signal XCLK with high voltage potential is to shift register circuit 100.
Specifically, voltage adjuster 130 can be held according to mode select signal SS1 and mode select signal SS2
Continuous is disconnected, and voltage adjuster 120 can be disconnected again according to the reverse frequency signal XCLK being raised.Then,
Compensation circuit 120 can be switched on according to the control signal CS1 being pulled low.At the same time, due to rear class gate drive signal G
[N+1's] is pulled low to voltage potential VA, and therefore, the voltage value on node P1 can be according to rear class gate drive signal G [N+1]
And synchronously it is pulled down to voltage potential VA.In this way, compensation circuit 120 can by the coupling effect of capacitor C1 so that
The voltage potential of control signal CS1 is further adjusted to the voltage value of grid low-voltage VGL and the summation of a voltage value V5.
Should be noted, the voltage value V5 can be expressed as the conducting voltage of transistor M7 | VTH7 | after via coupling effect
Voltage difference between one deviant △ V.Also that is, the voltage potential of control signal CS1 at this time is VGL+V5=VGL+ | VTH7
|-△V。
On the other hand, voltage adjuster 160 can be disconnected again according to the reverse frequency signal XCLK being pulled up.It connects
, voltage adjuster 150 gate high-voltage VGH to control terminal CT2 can be provided according to the control signal CS1 being pulled low so that
The voltage potential of control signal CS2 is maintained the voltage value of gate high-voltage VGH.
In other words, in the present embodiment, when shift register circuit 100 operates in the second sub-stage TR_2, output stage electricity
Road 110 can be provided according to the control signal CS1 being pulled low grid low-voltage VGL with to output end OUT carry out charging action,
And output-stage circuit 110 is set to pass through output end OUT to generate N grades of grid of the voltage potential with grid low-voltage VGL
Pole driving signal G [N].
Fig. 8 is the circuit signal for keeping the stage in voltage according to N grades of the shift register circuit of one embodiment of the invention
Figure.Referring to Fig. 2 and Fig. 8, specifically, when shift register circuit 100, which operates in voltage, keeps stage TVH, move
Position register circuit 100 can set mode select signal SS1 and mode select signal SS2 is continuously high voltage potential state,
Also, frequency signal CLK and the reverse frequency letter that external frequency generator (not drawing) can be provided with periodical transition
Number XCLK is to shift register circuit 100.
Specifically, voltage adjuster 130 can be tieed up according to mode select signal SS1 and mode select signal SS2
It holds and is disconnected.At the same time, voltage adjuster 140 can be switched on according to reverse frequency signal XCLK and periodically, and
Voltage adjuster 140 periodically can carry out charging action to control signal CS1, use and draw high control signal CS1.Then,
Voltage adjuster 120 can be disconnected again according to the control signal CS1 being raised.
On the other hand, voltage adjuster 160 can be switched on according to reverse frequency signal XCLK and periodically, and electricity
It presses adjuster 160 periodically can carry out charging action to control signal CS2, uses the voltage electricity for drawing low control signal CS2
Position.
In other words, in the present embodiment, when shift register circuit 100, which operates in voltage, keeps stage TVH, output stage electricity
Road 110 can be provided according to the control signal CS2 being pulled low grid low-voltage VGH with to output end OUT carry out charging action,
And output-stage circuit 110 is set to pass through output end OUT to generate N grades of grids of the voltage potential with gate high-voltage VGH and drive
Dynamic signal G [N].
It should be noted, above-mentioned high voltage potential can be the voltage value of gate high-voltage VGH, and low voltage potential
It can be the voltage value of grid low-voltage VGL.
Description according to above-mentioned Fig. 6 to Fig. 8, which can understand, to be learnt, in write phase TR, shift register circuit
100 can be by the coupling effect of capacitor C1, and signal CS1 synchronizes is pulled down alloing to control, and then believes gate driving
Number G [N] and rear class gate drive signal G [N+1] can be exported sequentially, and the efficiency for promoting gate drive apparatus is used.
In conclusion the shift register circuit of gate drive apparatus of the invention can make output stage in compensated stage
N caused by circuit grades of gate drive signal and rear class gate drive signal synchronize output.And in write phase,
Make N caused by output-stage circuit grades of gate drive signal with rear class gate drive signal being exported sequentially, use promotion
The efficiency of gate drive apparatus.
Certainly, the present invention can also have other various embodiments, without deviating from the spirit and substance of the present invention, ripe
It knows those skilled in the art and makes various corresponding changes and modifications, but these corresponding changes and change in accordance with the present invention
Shape all should fall within the scope of protection of the appended claims of the present invention.
Claims (17)
1. a kind of gate drive apparatus characterized by comprising
Multiple shift register circuits 100, the multiple shift register circuit are serially connected coupling, generate multiple gate drivings respectively
Signal G [N], wherein N grades of shift register circuit includes:
One output-stage circuit 110 has one first control terminal and one second control terminal T2 to receive one first control letter respectively
Number and a second control signal, according to the first control signal and the second control signal to provide a grid low-voltage
VGL or a gate high-voltage VGH generate a N grades of gate drive signals to an output end；
One compensation circuit 120 is coupled to first control terminal, and wherein the compensation circuit includes:
One capacitor C1 is coupled between first control terminal and a first node；And
One the first transistor M3, first end receive a rear class gate drive signal G [N+1], the second end of the first transistor
It is coupled to first node CT1, the control terminal of the first transistor receives the first control signal；
One first voltage adjuster is coupled to first control terminal, according to a first mode selection signal and one second mould
Formula selection signal is to provide the grid low-voltage or the gate high-voltage to adjust the first control signal；
One second voltage adjuster is coupled to first control terminal, according to a switching signal and a reverse frequency signal to mention
For a prime gate drive signal or an initial pulse signal to adjust the first control signal；
One tertiary voltage adjuster is coupled between first control terminal and second control terminal, according to described second
Mode select signal and the first control signal are to provide the grid low-voltage or the gate high-voltage to adjust
State second control signal；And
One the 4th voltage adjuster is coupled to second control terminal, according to the reverse frequency signal to adjust described second
Control signal.
2. gate drive apparatus according to claim 1, which is characterized in that in a compensated stage, the second voltage tune
Whole device is cut off according to the switching signal, and the first voltage adjuster is provided according to the first mode selection signal
The grid low-voltage is to drag down the first control signal.
3. gate drive apparatus according to claim 2, which is characterized in that in the compensated stage, the 4th voltage
Adjuster is switched on according to the reverse frequency signal, which provides according to the first control signal
The gate high-voltage is to draw high the second control signal.
4. gate drive apparatus according to claim 3, which is characterized in that in the compensated stage, the output stage
Circuit provides the grid low-voltage according to the first control signal to the output end.
5. gate drive apparatus according to claim 2, which is characterized in that in one first sub-stage of a write phase,
The first voltage adjuster is disconnected, institute according to the first mode selection signal and the second mode selection signal
It states second voltage adjuster to be switched on according to the switching signal and the reverse frequency signal being pulled low, to transmit
Prime gate drive signal or the initial pulse signal are stated to drag down the first control signal.
6. gate drive apparatus according to claim 5, which is characterized in that in first sub-stage in said write stage,
4th voltage adjuster is switched on according to the reverse frequency signal, and the tertiary voltage adjuster is according to described first
It controls signal and provides the gate high-voltage to draw high the second control signal.
7. gate drive apparatus according to claim 5, which is characterized in that in the one second sub- rank in said write stage
Section, second transmission channel are cut off, the first control signal foundation according to the reverse frequency signal being raised
The grid low-voltage and be pulled low a deviant.
8. gate drive apparatus according to claim 5, which is characterized in that the output-stage circuit is according to first control
Signal processed is to provide the grid low-voltage to the output end.
9. gate drive apparatus according to claim 2, which is characterized in that kept for the stage in a voltage, second electricity
Adjuster being switched on according to the reverse frequency signal period property is pressed, and is periodically charged to the first control signal, institute
It states first voltage adjuster to maintain to be cut off, the 4th voltage adjuster being led according to the reverse frequency signal period property
It is logical, and periodically charge to the second control signal.
10. gate drive apparatus according to claim 9, which is characterized in that keep stage, the output in the voltage
Grade circuit provides the gate high-voltage according to the second control signal.
11. gate drive apparatus according to claim 1, which is characterized in that the output-stage circuit includes:
One second transistor, the first end receive the grid low-voltage, and the second end of the second transistor is coupled to institute
Output end is stated, the control terminal of the second transistor receives the first control signal；And
One third transistor, first end are coupled to the output end, and the second end of the third transistor receives the gate high-voltage,
The control terminal of the third transistor receives the second control signal.
12. gate drive apparatus according to claim 1, which is characterized in that the first voltage adjuster includes:
One second transistor, first end receive the grid low-voltage, and the second end of the second transistor is coupled to described first
The control terminal of control terminal, the second transistor receives the first mode selection signal；And
An at least third transistor is coupled between first control terminal and the gate high-voltage, and an at least third is brilliant
The control terminal of body pipe receives the second mode selection signal.
13. gate drive apparatus according to claim 1, which is characterized in that the second voltage adjuster includes:
One second transistor, first end receive the prime gate drive signal or the initial pulse signal, second crystalline substance
Body pipe controls and receives the reverse frequency signal；And
One third transistor, first end are coupled to the second end of the second transistor, the second end coupling of the third transistor
It is connected to first control terminal, the control terminal of the third transistor receives the switching signal.
14. gate drive apparatus according to claim 1, which is characterized in that the tertiary voltage adjuster includes:
One second transistor, first end receive the grid low-voltage, and the second end of the second transistor is coupled to described the
The control terminal of two control terminals, the second transistor receives the second mode selection signal；
One third transistor, first end are coupled to second control terminal, and the second end of the third transistor receives the grid
The control terminal of very high voltage, the third transistor receives the first control signal；
One the 4th transistor, first end are coupled to first control terminal, and the control terminal of the 4th transistor is coupled to described
Second control terminal；And
One the 5th transistor, first end are coupled to the second end of the 4th transistor, the second termination of the 5th transistor
The gate high-voltage is received, the control terminal of the 5th transistor is coupled to second control terminal.
15. gate drive apparatus according to claim 1, which is characterized in that the 4th voltage adjuster includes:
One diode, cathode receive the reverse frequency signal, and anode is coupled to second control terminal.
16. gate drive apparatus according to claim 15, which is characterized in that the diode includes:
One second transistor, first end and control terminal receive the reverse frequency signal；And
One third transistor, first end are coupled to the second end of the second transistor, the second end coupling of the third transistor
It is connected to second control terminal, the control terminal of the third transistor receives the reverse frequency signal.
17. gate drive apparatus according to claim 1, which is characterized in that in a compensated stage, the gate driving letter
It number is enabled simultaneously, in a write phase, the gate drive signal is sequentially enabled, and keeps stage, the grid in a voltage
Pole driving signal is maintained at the voltage value being disabled；
Wherein, the compensated stage, write phase and voltage are kept for the stage sequentially occur.
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| US201862684913P | 2018-06-14 | 2018-06-14 | |
| US62/684,913 | 2018-06-14 | ||
| TW107141167 | 2018-11-20 | ||
| TW107141167A TWI673704B (en) | 2018-06-14 | 2018-11-20 | Gate driving apparatus |
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| CN110060620A true CN110060620A (en) | 2019-07-26 |
| CN110060620B CN110060620B (en) | 2022-10-25 |
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