CN108831401B - Grid driving unit, grid driving circuit and display system - Google Patents
Grid driving unit, grid driving circuit and display system Download PDFInfo
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- CN108831401B CN108831401B CN201810955289.0A CN201810955289A CN108831401B CN 108831401 B CN108831401 B CN 108831401B CN 201810955289 A CN201810955289 A CN 201810955289A CN 108831401 B CN108831401 B CN 108831401B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
Abstract
The invention discloses a grid driving unit, and belongs to the technical field of thin film liquid crystal displays. The grid driving unit comprises a starting unit, a resetting unit, an auxiliary unit, a pull-up unit and a pull-down unit, wherein the starting unit is electrically connected with the resetting unit, the auxiliary unit and the pull-up unit respectively, and the auxiliary unit is electrically connected with the pull-down unit; the pull-up unit comprises a seventh thin film transistor and a capacitor, the grid electrode of the seventh thin film transistor is electrically connected with the starting unit, the reset unit, the auxiliary unit and one end of the capacitor respectively, the drain electrode is connected to the CLK end, and the source electrode is electrically connected with the other end of the capacitor and the pull-down unit respectively and is connected with the output end GOUT. The invention further provides a gate driving circuit, which comprises the gate driving unit. In addition, a display system is also provided, and the display system comprises the grid drive circuit.
Description
Technical Field
The invention belongs to the technical field of thin film liquid crystal displays, and particularly relates to a grid driving unit, a grid driving circuit and a display system.
Background
In recent years, with the development of Display technology, Thin Film Transistor Liquid Crystal displays (TFT-LCDs) have become mainstream Display products in the market due to their advantages of small size, fine appearance, low power consumption, and the like. The thin film transistor liquid crystal display system mainly comprises a driver and a pixel display area. The driver is divided into a grid driver and a source driver, and the grid driver controls the on-off of the pixel driving TFT device so as to determine the on-off state of the scanning line; the data driver inputs video data to the pixel electrode under the condition that the corresponding scanning line is opened, and the video data and the COM electrode form an electric field to control the deflection of the liquid crystal, so that the transmittance is controlled. As the resolution of small and medium-sized displays becomes higher and higher, the number of scan lines and data lines is increased sharply in a conventional wiring manner, which increases the cost of the driving IC; on the other hand the border of the product becomes larger. Therefore, the same process technology as that of the TFT is adopted, the design of the grid drive circuit is integrated into the glass, the product cost is saved, meanwhile, an ultra-narrow frame can be realized, and the delicate appearance is obtained.
However, the current amorphous silicon gate drivers all have the following two problems: 1. the size of the frame is difficult to further reduce on the metal wiring; 2. the stability of the gate voltage output to the thin film transistor is insufficient, resulting in leakage current and poor display effect.
Disclosure of Invention
In view of the above, it is desirable to provide a gate driving unit, a gate driving circuit and a display system, in which the gate driving circuit can reduce the space for the wiring of the gate circuit, improve the power consumption of the circuit, and improve the stability of the circuit when a sufficient charging voltage is supplied to the scan line.
The technical scheme adopted by the invention is as follows:
a gate drive circuit comprises a starting unit, a reset unit, an auxiliary unit, a pull-up unit and a pull-down unit, wherein the starting unit is electrically connected with the reset unit, the auxiliary unit and the pull-up unit respectively, and the auxiliary unit is electrically connected with the pull-down unit;
the pull-up unit comprises a seventh thin film transistor T7 and a capacitor C, wherein the gate of the seventh thin film transistor T7 is electrically connected with the start unit, the reset unit, the auxiliary unit and one end of the capacitor respectively, the drain is connected to the CLK terminal, and the source is electrically connected with the other end of the capacitor C and the pull-down unit respectively and connected with the output GOUT.
Further, the start unit includes a first thin film transistor T1, the gate of the first thin film transistor T1 is connected to the start signal STV, the drain is connected to the XCLK terminal, and the source is electrically connected to the reset unit, the auxiliary unit and the pull-up unit
And (4) connecting.
Further, the reset unit includes a second thin film transistor T2, a gate of the second thin film transistor T2 is connected to a reset signal REST, a drain is connected to a CLK terminal, and a source is electrically connected to the auxiliary unit and the pull-up unit.
Further, the auxiliary unit includes a third thin film transistor T3, a fourth thin film transistor T4, and an eighth thin film transistor T8, a gate and a drain of the eighth thin film transistor T8 are respectively connected to a clock signal CLK and electrically connected to the pull-up unit, a source is respectively connected to a gate of the third thin film transistor T3, a drain of the fourth thin film transistor T4, and the pull-down unit, a drain of the third thin film transistor T3 is respectively connected to a source of the first thin film transistor T1, a source of the second thin film transistor T2, a gate of the fourth thin film transistor T4, and the pull-up unit, and a source is respectively connected to a source of the fourth thin film transistor T4, the pull-down unit, and is connected to a negative power input signal VGL.
Further, the gate of the seventh thin film transistor T7 is electrically connected to the source of the first thin film transistor T1, the source of the second thin film transistor T2, the drain of the third thin film transistor T3 and one end of the capacitor C, respectively, the drain is connected to the always signal CLK, and the source is electrically connected to the other end of the capacitor C and the pull-down unit, respectively, and is connected to the output terminal GOUT.
Further, the pull-down unit includes a fifth thin film transistor T5 and a sixth thin film transistor T6, a gate of the fifth thin film transistor T5 is electrically connected to the gate of the third thin film transistor T3, a drain is electrically connected to the drain of the sixth thin film transistor T6, a source is electrically connected to the sixth thin film transistor T6, and a negative power input signal VGL is inputted.
In addition, the invention also provides a gate driving circuit which is composed of four groups of 320 rows of cascade units of the gate driving unit.
In addition, the invention also provides a display system, which comprises a pixel display area, a grid driver, a data driver, a signal controller and a gray scale voltage generator; the gate driver comprises the gate driving circuit; the input end of the signal controller is connected with an external signal end, the first control end and the data end are connected with the data driver, and the second control end is connected with the grid driver; the STV end, the CLK end, the XCLK end and the RSET end of the gate driver are all connected to an external signal end, and the output end of the gate driver is connected to the gate driving circuit unit; the input end of the data driver is also connected with a gray scale voltage generator, and the input end of the gray scale voltage generator is connected with an external signal end.
The technical scheme of the invention has the following advantages:
1. through setting up the combination of 1 thin-film transistor and 1 electric capacity as novel pull-up unit, improved gate drive circuit's driving capability and the stability of signal output.
2. The display device provided by the invention optimizes two main problems of the current amorphous silicon gate drive circuit, and can be directly suitable for the production of high-resolution medium-small-size display products.
3. The amorphous silicon gate driving circuit can optimize the design structure of the panel and realize the design of a display product with low cost and ultra-narrow frame.
Drawings
FIG. 1 is a block diagram of a gate driving unit according to the present invention;
FIG. 2 is a circuit diagram of a gate driving unit according to the present invention;
FIG. 3 is a schematic diagram of a gate driving circuit according to the present invention;
FIG. 4 is a schematic diagram of a display system according to the present invention;
FIG. 5 is a schematic diagram of a driving signal according to the present invention;
description of the main elements
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The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is to be understood that the terminology used in the embodiments of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The terms "comprising" and "having," and any variations thereof, in the description and claims of this invention and the above-described drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, product, or apparatus.
It is noted that the following detailed description describes embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Referring to fig. 1, an embodiment of the invention provides a gate driving unit, which includes an initiation unit 10, a reset unit 20, an auxiliary unit 30, a pull-up unit 40, and a pull-down unit 50.
The starting unit 10 is electrically connected to the resetting unit 20, the auxiliary unit 30, and the pull-up unit 40, the pull-up unit 40 is electrically connected to the auxiliary unit 30 and the pull-down unit 50, and the auxiliary unit 30 is electrically connected to the pull-down unit 50.
Referring to fig. 2, more specifically, the start unit 10 includes a first thin film transistor T1, a gate of the first thin film transistor T1 is connected to a start signal STV, a drain of the first thin film transistor T1 is connected to an XCLK terminal, a source of the first thin film transistor T, the reset unit 20, and the auxiliary unit
30 and the pull-up unit 40 are electrically connected.
The reset unit 20 includes a second thin film transistor T2, a gate of the second thin film transistor T2 is connected to a reset signal REST, a drain is connected to a CLK terminal, and a source is electrically connected to the auxiliary unit 30 and the pull-up unit 40.
Referring to fig. 2, the auxiliary unit 30 includes a third tft T3, a fourth tft T4 and an eighth tft T8, a gate and a drain of the eighth tft T8 are respectively connected to a clock signal CLK and electrically connected to the pull-up unit 40, and a source of the eighth tft T8 is respectively electrically connected to the gate of the third tft T3, the drain of the fourth tft T4 and the pull-down unit 50.
The drain of the third tft T3 is electrically connected to the source of the first tft T1, the source of the second tft T2, the gate of the fourth tft T4 and the pull-up unit 40, and the source is electrically connected to the source of the fourth tft T4, the pull-down unit 50 and the negative power input signal VGL.
The pull-up unit 40 includes a seventh thin film transistor T7 and a capacitor C, a gate of the seventh thin film transistor T7 is electrically connected to a source of the first thin film transistor T1, a source of the second thin film transistor T2, a drain of the third thin film transistor T3, and one end of the capacitor C, respectively, a drain is connected to a constant signal CLK, and a source is electrically connected to the other end of the capacitor C and the pull-down unit 50, and is connected to the output terminal GOUT.
The pull-down unit 50 includes a fifth thin film transistor T5 and a sixth thin film transistor T6, wherein a gate of the fifth thin film transistor T5 is electrically connected to a gate of the third thin film transistor T3, a drain of the fifth thin film transistor T5 is electrically connected to a drain of the sixth thin film transistor T6, and a source of the fifth thin film transistor T6 is electrically connected to the negative power input signal VGL.
In addition, a connection point of the gate electrode of the third thin film transistor T3, the drain electrode of the fourth thin film transistor T4, the gate electrode of the fifth thin film transistor T5, and the source electrode of the eighth thin film transistor T8 is marked as a point P; the source of the first thin film transistor T1, the source of the second thin film transistor T2, the drain of the third thin film transistor T3, and the seventh thin film transistor connection point are marked as point a.
The gate driving circuit in this embodiment is a 720(RGB) X1280 glass gate driving circuit, and the gate driving circuit is formed by cascading 320 stages of cascade units, each cascade unit includes four sets of the gate driving units, the left and right sides of each cascade unit are respectively divided into two sets to respectively generate two rows of odd-numbered and even-numbered gate driving signals, and the signal control line includes two sets of STV signals, two sets of RSET signals, and two sets of CLK and XCLK signals.
The present embodiment defines that the driving signal shown in fig. 5 drives the gate driving circuit. The driving waveforms of the first 2 stages of the 320-stage cascade structure adopt the driving waveforms as shown in fig. 5. Wherein:
stage TP 1: STV high, CLK1 low, XCLK1 high; t1 is turned on, the potential at point A is raised to VGH-Vth,
the potential at the point P is at a low level, and the signal at the SG (1) terminal is turned on by T6 to output a low level.
Stage TP 2: CLK high, XCLK low; the potential of the point A is further raised to about VGH-Vth +. Δ V due to the coupling action of the T7, the T7, SG (1) outputs high level, the potential of the point P is turned on due to the T4, the W/L of the T4 is forced to be pulled down to VGL because the W/L is larger than that of the T8 (meanwhile, the GOUT1 signal of the first stage is used as the STV signal of the second stage unit, and the second stage unit is used as the STV signal of the second stage unit
Process "TP 1") is performed.
Stage TP 3: CLK1 low, XCLK1 high; the SG (1) -terminal signal outputs a low level due to the conduction of T6 (meanwhile, SG (5) of the second-stage unit outputs a high level as the RSET signal of the first-stage unit, the potential of the point a is pulled down to VGL, and the point P keeps on keeping a low point).
Stage TP 4: CLK1 is high, XCLK1 is low, and the potential at point P is raised to VGH-Vth due to the T8 being turned on, and the signal at the SG (1) terminal continues to maintain the low state because point A is low.
Stage TP 5: CLK1 is low, XCLK1 is high, T8 is turned off, and P is kept high at VGH-Vth, while A is kept low, and T6 is turned on to keep SG (1) terminal low.
Before the STV signal of the next frame comes, the first stage unit always loops the processes of "TP 4 phase" and "TP 5 phase",
meanwhile, the 320 th stage of the first and second stages … … outputs SG (1), SG (3), SG (5), SG (7) … … SG (1277), SG (1279) in sequence.
In addition, the inversion function of the display product can be determined by setting the timing of STV, CLK, XCLK, RSET of the odd and even stages on the left and right sides.
In the display system provided by this embodiment, as shown in fig. 4, the display system includes a pixel display region, a gate driver, a data driver, a signal controller, and a gray scale voltage generator; the gate driver comprises the gate driving circuit; the input end of the signal controller is connected with an external signal end, the first control end and the data end are connected with the data driver, and the second control end is connected with the grid driver; the STV end, the CLK end, the XCLK end and the RSET end of the gate driver are all connected to an external signal end, and the output end of the gate driver is connected to the gate driving circuit unit; the input end of the data driver is also connected with a gray scale voltage generator, and the input end of the gray scale voltage generator is connected with an external signal end.
Wherein the gate driver controls the switching of the pixel driving TFT device to determine the on-off state of the scan line; the data driver inputs video data to the pixel electrode under the condition that the corresponding scanning line is opened, and the video data and the COM electrode form an electric field to control the deflection of the liquid crystal, so that the transmittance is controlled.
Claims (7)
1. A gate drive unit, characterized by: the grid driving unit comprises a starting unit, a resetting unit, an auxiliary unit, a pull-up unit and a pull-down unit, wherein the starting unit is electrically connected with the resetting unit, the auxiliary unit and the pull-up unit respectively, and the auxiliary unit is electrically connected with the pull-down unit; the pull-up unit comprises a seventh thin film transistor and a capacitor, the grid electrode of the seventh thin film transistor is electrically connected with the starting unit, the reset unit, the auxiliary unit and one end of the capacitor respectively, the drain electrode is connected to the CLK end, and the source electrode is electrically connected with the other end of the capacitor and the pull-down unit respectively and is connected with the output end GOUT;
the auxiliary unit comprises a third thin film transistor, a fourth thin film transistor and an eighth thin film transistor, wherein a grid electrode and a drain electrode of the eighth thin film transistor are respectively connected with a clock signal CLK and are electrically connected with the pull-up unit, a source electrode is respectively electrically connected with a grid electrode of the third thin film transistor, a drain electrode of the fourth thin film transistor and the pull-down unit, a drain electrode of the third thin film transistor is respectively electrically connected with a source electrode of the first thin film transistor, a source electrode of the second thin film transistor, a grid electrode of the fourth thin film transistor and the pull-up unit, and a source electrode is respectively electrically connected with a source electrode of the fourth thin film transistor, the pull-down unit and is connected with a negative power input signal VGL.
2. A gate drive unit as claimed in claim 1, wherein: the starting unit comprises a first thin film transistor, the grid electrode of the first thin film transistor is connected with a starting signal STV, the drain electrode of the first thin film transistor is connected with an XCLK end, and the source electrode of the first thin film transistor is electrically connected with the resetting unit, the auxiliary unit and the pull-up unit.
3. A gate drive unit as claimed in claim 2, wherein: the reset unit comprises a second thin film transistor, the grid electrode of the second thin film transistor is connected with a reset signal REST, the drain electrode of the second thin film transistor is connected with a CLK end, and the source electrode of the second thin film transistor is electrically connected with the auxiliary unit and the pull-up unit.
4. A gate drive unit as claimed in claim 1, wherein: the grid electrode of the seventh thin film transistor is electrically connected with the source electrode of the first thin film transistor, the source electrode of the second thin film transistor, the drain electrode of the third thin film transistor and one end of the capacitor respectively, the drain electrode is connected with a constant signal CLK, and the source electrode is electrically connected with the other end of the capacitor C and the pull-down unit respectively and is connected with an output end GOUT.
5. A gate drive unit as claimed in claim 4, wherein: the pull-down unit comprises a fifth thin film transistor and a sixth thin film transistor, wherein the grid electrode of the fifth thin film transistor is electrically connected with the grid electrode of the third thin film transistor, the drain electrode of the fifth thin film transistor is electrically connected with the drain electrode of the sixth thin film transistor, and the source electrode of the fifth thin film transistor is electrically connected with the sixth thin film transistor and is connected with a negative power supply input signal VGL.
6. A gate drive circuit, comprising: the gate driving circuit is composed of four sets of 320 rows of cascaded cells of the gate driving unit of any one of claims 1-5.
7. A display system, characterized by: the display system comprises a pixel display area, a grid driver, a data driver, a signal controller and a gray scale voltage generator; the gate driver includes the gate driving circuit as claimed in claim 6; the input end of the signal controller is connected with an external signal end, the first control end and the data end are connected with the data driver, and the second control end is connected with the grid driver; the STV end, the CLK end, the XCLK end and the RSET end of the gate driver are all connected to an external signal end, and the output end of the gate driver is connected to the gate driving circuit unit; the input end of the data driver is also connected with a gray scale voltage generator, and the input end of the gray scale voltage generator is connected with an external signal end.
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| CN201810955289.0A CN108831401B (en) | 2018-08-21 | 2018-08-21 | Grid driving unit, grid driving circuit and display system |
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| CN201810955289.0A CN108831401B (en) | 2018-08-21 | 2018-08-21 | Grid driving unit, grid driving circuit and display system |
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| CN108831401B true CN108831401B (en) | 2020-12-22 |
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| CN110223656B (en) * | 2019-06-28 | 2022-05-06 | 信利(仁寿)高端显示科技有限公司 | GOA circuit with reset function and array substrate |
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| CN101242178A (en) * | 2007-02-07 | 2008-08-13 | 三菱电机株式会社 | Semiconductor device and shift register circuit |
| CN102819998A (en) * | 2012-07-30 | 2012-12-12 | 京东方科技集团股份有限公司 | Shift register unit, shift register and display device |
| CN106448588A (en) * | 2016-10-09 | 2017-02-22 | 深圳市华星光电技术有限公司 | GOA drive circuit and liquid crystal display device |
| US9734918B2 (en) * | 2011-11-28 | 2017-08-15 | Boe Technology Group Co., Ltd. | Shift register and the driving method thereof, gate driving apparatus and display apparatus |
| CN108257575A (en) * | 2018-03-26 | 2018-07-06 | 信利半导体有限公司 | A kind of gate driving circuit and display device |
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| CN101242178A (en) * | 2007-02-07 | 2008-08-13 | 三菱电机株式会社 | Semiconductor device and shift register circuit |
| US9734918B2 (en) * | 2011-11-28 | 2017-08-15 | Boe Technology Group Co., Ltd. | Shift register and the driving method thereof, gate driving apparatus and display apparatus |
| CN102819998A (en) * | 2012-07-30 | 2012-12-12 | 京东方科技集团股份有限公司 | Shift register unit, shift register and display device |
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