CN110058465A - Display panel - Google Patents
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- CN110058465A CN110058465A CN201810047180.7A CN201810047180A CN110058465A CN 110058465 A CN110058465 A CN 110058465A CN 201810047180 A CN201810047180 A CN 201810047180A CN 110058465 A CN110058465 A CN 110058465A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a kind of display panels, the peripheral region with viewing area and outside viewing area, and display panel includes with boundary and in the display area with the first substrate of multiple pixel units.It is set at least one connection structure on first substrate and being located in peripheral region, connection structure includes the first metal layer, the first insulating layer, second metal layer, second insulating layer, and it is set to the conductive layer in second insulating layer, conductive layer directly contacts the first metal layer via the first perforation and directly contacts second metal layer via the second perforation, wherein each of the first perforation and the second perforation are at least 220 microns apart from boundary.The second substrate being arranged oppositely with first substrate.And it is set to the frame glue between first substrate and the second substrate and being located in peripheral region, frame glue is extended towards viewing area by boundary in peripheral region and covers at least one of at least one connection structure on display base plate.Display panel of the invention can delay the intrusion time of external aqueous vapor.
Description
Technical field
The present invention relates to a kind of display panels, and more particularly to the display panel that one kind can delay external water gas cut to enter.
Background technique
With thin film transistor (TFT) (thin film transistor；TFT) LCD technology is constantly progressive, and will be driven
The technology, such as system combination formula glass panel etc. of circuit (such as gate driving circuit) integration on a display panel, gradually
It is widely used in display device now, to minimize the size of display device product and promote the efficiency of display device.However,
For system combination formula glass panel, driving circuit is typically fabricated at substrate boundaries, causes to be easy by outside
The corrosion of aqueous vapor, and generate the integrity problem of display device and the shortening of display device service life.
Summary of the invention
The purpose of the invention is to provide a kind of display panels, and external water gas cut can be delayed to enter to display panel
Time, avoid the electronic component and signal lead etc. in corrosion driving circuit, and then promote the reliability of display panel and prolong
The service life of long display panel.
Purpose according to the present invention proposes a kind of display panel, this display panel has viewing area and is located at display
Peripheral region outside area and include first substrate, connection structure, the second substrate and frame glue.First substrate has boundary, and is showing
There are multiple pixel units in area.Connection structure be set on first substrate and be located at peripheral region in, it includes the first metal layer,
First insulating layer, second metal layer, second insulating layer and conductive layer.The first metal layer is set on first substrate.First insulation
Layer is set on first substrate and the first metal layer.Second metal layer is set on the first insulating layer.Second insulating layer is set to
On first insulating layer and second metal layer, wherein the combination of the first insulating layer and second insulating layer has the first perforation, and second
Insulating layer also has the second perforation, and the first perforation exposes the first metal layer, and the second perforation exposes second metal layer.It leads
Electric layer is set in second insulating layer, is directly contacted the first metal layer via the first perforation and is directly contacted via the second perforation
Second metal layer, wherein the first perforation is at least 220 microns apart from boundary with the second perforation.The second substrate is and first substrate
It is arranged oppositely.Frame glue is set between first substrate and the second substrate and is located in peripheral region, this frame glue is in peripheral region by side
Boundary extends towards viewing area and covers connection structure on display base plate.
An embodiment according to the present invention, boundary of the connection structure apart from first substrate are at most the width of peripheral region
0.9 times.
Another embodiment according to the present invention, the width of the peripheral region are at least 0.8 millimeter.
Another embodiment according to the present invention, the conductive layer are transparency conducting layers.
Another embodiment according to the present invention, each pixel unit include thin film transistor (TFT), this thin film transistor (TFT) includes grid
Pole, source electrode and drain electrode.One in grid and the first metal layer and second metal layer belongs to same layer, and source electrode, drain electrode and the
Another in one metal layer and second metal layer belongs to same layer.
Another embodiment according to the present invention, each pixel unit include pixel electrode and common electrode.Pixel electrode with
One in common electrode belongs to same layer with conductive layer.
Another embodiment according to the present invention, the display panel also include that signal lead, connection cabling and electricity meet this company
Connect the electronic component of cabling.A part for signal lead in the first metal layer and the second metal layer, and
Another of the first metal layer and the second metal layer are a part for connecting cabling.
Another embodiment according to the present invention, the driving circuit also include thin film transistor (TFT), this thin film transistor (TFT) includes
Grid, source electrode and drain electrode.Wherein, one in grid and the first metal layer and the second metal layer belongs to same layer,
Another in source electrode, drain electrode and the first metal layer and the second metal layer belongs to same layer, and one in source electrode and drain electrode
It is a to be electrically connected to grid via the connection structure.
Another embodiment according to the present invention, the driving circuit also include first film transistor and the second film crystal
Pipe, wherein first film transistor includes first grid, the first source electrode and the first drain electrode, and the second thin film transistor (TFT) includes second
Grid, the second source electrode and the second drain electrode.In first grid, second grid and the first metal layer and the second metal layer
One belongs to same layer, the first source electrode, the first drain electrode, the second source electrode, the second drain electrode and the first metal layer and described second
Another in metal layer belongs to same layer, and the first source electrode electrically connects with one in the first drain electrode via the connection structure
It is connected to second grid.
It is an advantage of the current invention that display panel of the invention can delay external water gas cut enter to display panel when
Between, electronic component and the signal lead etc. in corrosion driving circuit are avoided, and then promote the reliability of display panel and extend aobvious
Show the service life of panel.
Detailed description of the invention
In order to more completely understand embodiment and its advantage, following description is done referring now to and in conjunction with attached drawing, in which:
Fig. 1 is the schematic diagram of the display device of some embodiments according to the present invention；
Fig. 2 is the partial cutaway schematic of the display panel of Fig. 1；
Fig. 3 is the schematic diagram of the gate driving circuit of some embodiments according to the present invention；
Fig. 4 is the schematic equivalent circuit of the shift register of Fig. 3；
Fig. 5 is the circuit layout schematic diagram of the shift register of Fig. 3；And
Fig. 6 is the diagrammatic cross-section of the connection structure of some embodiments according to the present invention.
Specific embodiment
The embodiment of the present invention is hashed out below.It is understood, however, that embodiment offer is many applicable general
It reads, may be implemented in miscellaneous specific content.It discusses, revealed embodiment only for illustrating, is not limited to this
The range of invention.
Although it is to be understood that can be used herein " first ", the terms such as " second " come describe various elements, part,
Region and/or part, but these terms should not limit these elements, part, region and/or part.These terms are only to area
An other element, part, region and/or part and another element, part, region and/or part.
" coupling " word used in herein, can refer to two or more elements and mutually directly makees entity or be electrically connected with
Touching, or body or in electrical contact is mutually put into effect indirectly, and " coupling " also can refer to two or more element mutual operations or movement.
Fig. 1 is please referred to, the schematic diagram of display device 100 is painted.Display device 100 includes display panel 110, source electrode drive
Dynamic device 120 and gate drivers 130.Display panel 110 can be such as twisted nematic (twisted nematic；TN) type, water
(in-plane switching is changed in truncation；IPS) type, fringe field switch (fringe-field switching；FFS) type or
Vertical orientation (vertical alignment；VA) various types of liquid crystal display panels such as type or Organic Light Emitting Diode
(organic light-emitting diode；OLED) display panel etc..Source electrode driver 120 is electrically connected to display panel
110, image data is converted to source drive signal, and source drive signal is transmitted to display panel 110.Grid
Driver 130 is transmitted to display panel 110 to generate gate drive signal, and by gate drive signal.Display panel 110 has
There are viewing area AA and peripheral region PA, wherein viewing area AA has the multiple data being formed on the lower substrate 111 of display panel 110
Line DL, multiple grid line SL and multiple pixel PX for being arranged in array, these pixels PX are jointly subjected to source drive signal and grid
The driving of pole driving signal and show image, and peripheral region PA has multiple wirings (figure be not painted), is respectively coupled to source electrode drive
It moves device 120 and gate drivers 130 and is respectively coupled to multiple data line DL and grid line SL in the AA of viewing area, respectively by source
Pole driving signal and gate drive signal are sent to the thin film transistor (TFT) TFT on lower substrate 111 and positioned at respective pixel PX, so that
Pixel PX by thin film transistor (TFT) TFT switch control and show corresponding grayscale in specific time.
Display device 100 of the invention is system combination formula glass panel (system on glass；SOG), that is,
It says, in the present invention, gate drivers 130 are produced in display panel 110.In this way, which same process can be used
The electronic component in display panel 110, source electrode driver 120 and gate drivers 130 is made simultaneously.For example, grid drives
Thin film transistor (TFT) in dynamic device 130 can use same process with the thin film transistor (TFT) being located in the AA of viewing area in display panel 110
Come while making.In other embodiments, source electrode driver 120 can also be produced in the peripheral region PA of display panel 110, and can
Made simultaneously using same process electronic component in display panel 110, source electrode driver 120 and gate drivers 130 and
Wiring.
Referring to figure 2., it is painted the fragmentary cross-sectional view of the display panel 110 of Fig. 1.In Fig. 2, display panel 110 includes
Lower substrate 111 (or thin film transistor base plate) and upper substrate 112 (or colored optical filtering substrates), and display panel 110 has
Viewing area AA and peripheral region PA.In the viewing area AA of display panel 110, active member layer 113 and pixel electrode layer 114 are arranged
In on lower substrate 111, BM is set on upper substrate 112, and liquid crystal for chromatic filter layer 115 and black matrix" (black matrix)
Layer 116 is between pixel electrode layer 114 and chromatic filter layer 115.Liquid crystal layer 116 includes multiple liquid crystal molecules LC, these liquid
The effect of internal electric field of the brilliant molecule L C by display panel 110 and correspond to torsion.The inside of display panel 110 also includes common
Electrode layer (figure is not painted), generates internal electric field to interact with pixel electrode layer 114, so that in liquid crystal layer 116
In liquid crystal molecule LC by internal electric field effect and correspond to torsion.In each pixel PX, active member layer 113 includes thin
Film transistor TFT is coupled to pixel electrode layer 114.By controlling the switch state of thin film transistor (TFT) TFT, pixel can be changed
The current potential of electrode layer 114, and then change the intensity distribution of face internal electric field.Common electrode layer (figure is not painted) can be according to display panel
110 type and different positions is set.For example, if display panel 110 be torsion nematic liquid crystal display panel or
Vertical alignment-type liquid crystal display panel, then common electrode layer (figure is not painted) is located at the phase of liquid crystal layer 116 with pixel electrode layer 114
To two sides；If display panel 110 is that horizontal cutting is remodeled liquid crystal display panel or fringe field switch type liquid crystal display panel, altogether
Same electrode layer (figure is not painted) is located at the same side of liquid crystal layer 116 with pixel electrode layer 114.
In the peripheral region PA of display panel 110, driving circuit 117 is set on lower substrate 111, and shielding layer 118 is arranged
In on upper substrate 112, and frame glue 119 is set between driving circuit 117 and shielding layer 118 and by the boundary of lower substrate 111
111A towards viewing area AA extend, can by light irradiation and solidify, to group lower substrate 111 and upper substrate 112.Driving
Circuit 117 can be the source electrode driver 120 of Fig. 1, gate drivers 130 or other any may be provided on lower substrate 111
Driving circuit.Shielding layer 118 to reflect the light for solidified frame 119 and this light stopped to penetrate to upper substrate 112, into
And increase the solidification effect of frame glue 119.In addition, in other embodiments of the present invention, the material of shielding layer 118 can be with black square
The material of battle array BM is identical.In some embodiments, shielding layer 118 is a part of black matrix" BM.It should be noted that although
In Fig. 2, driving circuit 117 is completely covered in frame glue 119, but invention is not limited thereto, and frame glue 119 can also only cover driving electricity
The part on road 117.In addition, the width of peripheral region PA is at least 0.8 millimeter, to provide driving circuit 117, shielding layer 118 and frame
The enough planar configuration spaces of glue 119.
Referring to figure 3., it is painted the schematic diagram of gate driving circuit 200 according to an embodiment of the present invention.Gate driving electricity
Road 200 is suitable for the display device 100 or other similar display devices of Fig. 1.Below to be set to the display for being used in Fig. 1
Illustrate for device 100.Gate driving circuit 200 be gate drivers 130 a part, it includes clock cable L1~
L4, initial signal line SL1, end signal line SL2, RL1, RL2 and N grades of shift-register circuits 210 (1) of control signal wire~
210 (N), wherein N is the positive integer more than or equal to 5.In some embodiments, more multiples that N is 4.Clock cable L1~
L4 is to provide clock signal C1~C4 to corresponding shift-register circuit 210 (1)~210 (N).In Fig. 3, clock signal
Line L1~L4 provides clock signal C1~C4 to corresponding shift-register circuit 210 (1)~210 (N) respectively.In addition, starting
Signal wire SL1 provides initial signal STV1 to the 1st, 2 grades of shift-register circuits 210 (1), 210 (2), and end signal line SL2 is mentioned
For end signal STV2 to (N-1), N grades of shift-register circuits 210 (N-1), 210 (N), and control signal wire RL1, RL2
Drop-down control signal GPW1, GPW2 is provided respectively to all shift-register circuit 210 (1)~210 (N).Shift register
Circuit 210 (1)~210 (N) generate scanning signal OUT (1)~OUT (N) respectively.Wherein, scanning signal OUT (1), OUT (2) points
It is not input to the 3rd, 4 grade of shift-register circuit 210 (3), 210 (4), scanning signal OUT (N-1), OUT (N) are separately input into
(N-3), (N-2) grade shift-register circuit 210 (N-3), 210 (N-2), and other scanning signals OUT (3)~OUT (N-2)
Each scanning signal be input to the shift-register circuit of its upper and lower second level.For example, scanning signal OUT (3) is input to displacement
Register circuit 210 (1) and shift-register circuit 210 (5).
Fig. 4 is painted the circuit box of i-stage shift-register circuit 210 (i) in the gate driving circuit 200 according to Fig. 3
Figure, the positive integer that wherein i is 1 to N.I-stage shift-register circuit 210 (i) includes precharge unit 310, pull-up unit
320, the first drop-down unit 330 and the second drop-down unit 340.
Precharge unit 310 receives input signal IN1, IN2, and is exported according to input signal IN1, IN2 by nodes X 1
Precharging signal PC (i).Precharge unit 310 includes transistor M1, M2.In the present embodiment, gate driving circuit 200 is double
To the driving circuit of scanning, and in i-stage shift-register circuit 210 (i), the grid of transistor M1 receives input signal
The source electrode of IN1, transistor M1 receive forward input signal FW, and the drain electrode couple nodes X1 of transistor M1；The grid of transistor M2
Pole receives input signal IN2, and the source electrode of transistor M2 receives reversed input signal BW, and the drain electrode couple nodes of transistor M2
X1。
If shift-register circuit 210 (i) is the 1st, 2 grade of shift-register circuit (i.e. i is 1,2), input signal IN1
For initial signal STV1, and input signal IN2 is the scanning signal of (i+2) grade shift-register circuit 210 (i+2) output
OUT(i+2).If shift-register circuit 210 (i) be the 3rd to (N-2) grade shift-register circuit (i.e. i be 3 to (N-2) just
Integer), then input signal IN1 is the scanning signal OUT (i-2) of (i-2) grade shift-register circuit 210 (i-2) output, and
Input signal IN2 is the scanning signal OUT (i+2) of (i+2) grade shift-register circuit 210 (i+2) output.If shift LD
Device circuit 210 (i) is (N-1), N grades of shift-register circuits (i.e. i is (N-1), N), then input signal IN1 is (i-2)
The scanning signal OUT (i-2) that grade shift-register circuit 210 (i-2) exports, and input signal IN2 is end signal STV2.
The coupling precharge unit 310 of pull-up unit 320, reception precharging signal PC (i) and clock signal CN, and according to
Precharging signal PC (i) and clock signal CN exports scanning signal OUT (i) by nodes X 2, and wherein clock signal CN is clock letter
One in number C1~C4.N be 4 more multiples embodiment in, if i be 1,5 ..., (N-3), when clock signal CN is
Clock signal C1；If i be 2,6 ..., (N-2), clock signal CN be clock signal C2；If i be 3,7 ..., (N-1), clock
Signal CN is clock signal C3；If i be 4,8 ..., N, clock signal CN be clock signal C4.
Pull-up unit 320 includes transistor M3 and capacitor Cx.The grid couple nodes X1 of transistor M3, the source of transistor M3
Pole receives clock signal CN, and the drain electrode couple nodes X2 of transistor M3.The both ends of capacitor Cx are respectively coupled to the grid of transistor M3
Pole and drain electrode.
First drop-down unit 330 couples precharge unit 310 and pull-up unit 320, receive precharging signal PC (i) and
Drop-down control signal GPW1, GPW2, and controlled whether according to precharging signal PC (i) and drop-down control signal GPW1, GPW2
Scanning signal OUT (i) is pulled down to reference potential VGL.Scanning signal OUT (i) is pulled down to reference in the first drop-down unit 330
After current potential VGL, scanning signal OUT (i) is maintained reference potential VGL by the first drop-down unit 330.
First drop-down unit 330 includes transistor M4~M8.Grid and source electrode the input drop-down control signal of transistor M4
GPW1.The source electrode of grid input drop-down control the signal GPW2, transistor M5 of transistor M5 couple reference potential VGL, and crystal
The drain electrode of the drain electrode coupling transistors M4 of pipe M5.The source electrode of grid the couple nodes X1, transistor M6 of transistor M6 couple reference
Current potential VGL, and the drain electrode of the drain electrode coupling transistors M4 of transistor M6.The drain electrode of the grid coupling transistors M6 of transistor M7,
The source electrode of transistor M7 couples reference potential VGL, and the drain electrode couple nodes X1 of transistor M7.The grid of transistor M8 couples brilliant
The drain electrode of body pipe M6, the source electrode of transistor M8 couple reference potential VGL, and the drain electrode couple nodes X2 of transistor M8.It is pulling down
When control signal GPW1 is low potential and drop-down control signal GPW2 is high potential, node P is in low-potential state, and is pulling down
When control signal GPW1 is high potential and drop-down control signal GPW2 is low potential, node P is in high potential state.
Second drop-down unit 340 couples precharge unit 310 and pull-up unit 320, receive precharging signal PC (i) and
Drop-down control signal GPW1, GPW2, and controlled whether according to precharging signal PC (i) and drop-down control signal GPW1, GPW2
Scanning signal OUT (i) is pulled down to reference potential VGL.Scanning signal OUT (i) is pulled down to reference in the second drop-down unit 340
After current potential VGL, scanning signal OUT (i) is maintained reference potential VGL by the second drop-down unit 340.
Grid and source electrode input drop-down control the signal GPW2 of transistor M9.The grid input drop-down control of transistor M10
The source electrode of signal GPW1, transistor M10 couple reference potential VGL, and the drain electrode of the drain electrode coupling transistors M9 of transistor M10.
The source electrode of grid the couple nodes X1, transistor M11 of transistor M11 couple reference potential VGL, and the drain electrode coupling of transistor M11
Connect the drain electrode of transistor M9.The drain electrode of the grid coupling transistors M11 of transistor M12, the source electrode coupling of transistor M12 is with reference to electricity
Position VGL, and the drain electrode couple nodes X1 of transistor M12.The drain electrode of the grid coupling transistors M11 of transistor M13, transistor
The source electrode of M13 couples reference potential VGL, and the drain electrode couple nodes X2 of transistor M13.It is low electricity in drop-down control signal GPW1
Position and when drop-down control signal GPW2 is high potential, node Q is in high potential state, and is high electricity in drop-down control signal GPW1
Position and drop-down control signal GPW2 be low potential when, node Q is in low-potential state.
It is lifted in gate drivers 130 in relation to the layout of shift-register circuit 210 (1)~210 (N) and coherent signal cabling
Under such as.Referring to figure 5., Fig. 5 is the layout of the shift-register circuit of some embodiments and signal lead according to the present invention.
For convenience of description, Fig. 5 only shows (j+1), (j+2) grade shift-register circuit 210 (j+1), 210 (j+2) of Fig. 3, wherein j
For 4 positive multiple.However, those skilled in the art can should directly deduce remaining from the content of layout shown in fig. 5 and Fig. 3,4
The layout type of shift register.In Fig. 5, ground line GL (it provides reference potential VGL), initial signal line SL1, terminate letter
The signal leads such as number line SL2, control signal wire PL1, PL2 and clock cable L1~L4 are located at close to the boundary of lower substrate 111
111A and along longitudinal extension, output end (its of (j+1), (j+2) grade shift register circuit 210 (j+1), 210 (j+2)
Scanning signal OUT (j+1), OUT (j+2) are exported respectively) it is located at the AA of viewing area.
As shown in figure 5, (j+1), (j+2) grade shift register circuit 210 (j+1), the layout areas of 210 (j+2) are equal
Comprising transistor M1~M13 and capacitor Cx, it is located at signal lead (i.e. ground line GL, initial signal line SL1, end signal line
SL2, control signal wire PL1, PL2 and clock cable L1~L4 etc.) with shift register circuit 210 (j+1), 210 (j+2)
Between output end.In addition, the layout of Fig. 5 also includes the electrically conducting transparent cabling TL on lower substrate 111 and in the PA of peripheral region
With multiple connection structure C, wherein electrically conducting transparent cabling TL is cyclic structure on lower substrate 111, is used for electrostatic discharge protective,
Electrostatic surging is avoided to directly affect the pixel PX of the AA in viewing area, and these connection structures C belongs to different gold as connection
Belong to the medium of the element of layer.These connection structures C may include the connection structure positioned at signal lead and the junction for connecting cabling
(such as connection structure of the junction of the connection cabling CW of the source electrode of clock cable L1 and connection transistor M3), positioned at identical
Connection structure (such as the connection grid of transistor M4 and connecing for source electrode of the junction of the grid and source/drain of transistor
Point), positioned at different crystal pipe junction connection structure (such as connection transistor M6 drain electrode and transistor M7 grid
The connection structure of junction) and belong to comprising any connection different metal layer element junction connection structure.It should be noted that
, to simplify accompanying drawing content, Fig. 5 only indicates two connection structure C；As shown in the above description, with thick wire mark in Fig. 5
The part shown is also connection structure C.
Fig. 6 is the diagrammatic cross-section of the connection structure 400 of some embodiments according to the present invention, this connection structure 400 is Fig. 5
Either one or two of these connection structures C.As shown in fig. 6, the first metal layer 420 is formed first on substrate 410, then in substrate
410 and the first metal layer 420 on depositing gate insulating layer 430.Later, second metal layer is formed on gate insulating layer 430
440.Then, passivation layer 450 is formed on gate insulating layer 430 and second metal layer 440.Later, using etch process right
It answers and forms perforation 460A and 460B in the gate insulating layer 430 and passivation layer 450 of position, to expose the first metal layer 420 respectively
And second metal layer 440.Finally, conductive layer 470 is formed on the first metal layer 420, second metal layer 440 and passivation layer 450,
The first metal layer 420 and second metal layer 440 are electrically connected in a manner of bridging in the filling perforation of conductive layer 470 460A and 460B.
Conductive layer 470 can be including, for example, indium tin oxide (indium tin oxide；) or indium-zinc oxide (indium ITO
zinc oxide；IZO transparency conducting layer).
In Fig. 6, the corresponding lower substrate 111 into Fig. 5 of substrate 410, the first metal layer 420 and second metal layer 440 can
Respectively in thin film transistor (TFT) M1~M13 of Fig. 5 grid and source/drain formed via identical technique, conductive layer 470 can
It is formed with the electrode of the capacitor Cx of Fig. 4 and/or the electrically conducting transparent cabling TL of Fig. 5 via identical technique, and the first metal layer 420
With second metal layer 440 and non-direct contact, but it is electrically connected by conductive layer 470.The first metal layer 420 and the second metal
Layer 440 can also be respectively with the grid of the thin film transistor (TFT) TFT in the AA of viewing area and source/drain via identical technique shape
At.In addition, conductive layer 470 can be formed with the pixel electrode or common electrode being located in the AA of viewing area using identical technique, i.e.,
Conductive layer 470 can belong to same layer with the pixel electrode or common electrode being located in the AA of viewing area.The perforation of each connection structure C
460A and 460B is at least 220 microns at a distance from the boundary 111A of lower substrate 111, to delay external water gas cut to enter to perforation
The time of 460A and 460B avoids electronic component and signal lead etc. in corrosion gate drivers 130.In addition, each connection
Structure C is at most 0.9 times of the width W of peripheral region AA at a distance from the boundary 111A of lower substrate 111.In some embodiments,
These connection structures C can be covered further by frame glue 119, further to promote the effect of aqueous vapor isolation.
In conclusion display panel of the invention can delay external water gas cut to enter the time to display panel, avoid
Corrode electronic component and the signal lead etc. in driving circuit, and then promotes the reliability of display panel and extend display panel
Service life.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
In technical staff, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore guarantor of the invention
Subject to shield range ought be defined depending on claim.
Claims (10)
1. a kind of display panel, which is characterized in that the display panel has viewing area and the periphery outside the viewing area
Area, and the display panel includes:
First substrate has multiple pixel units with boundary and in the viewing area；
At least one connection structure is set on the first substrate and is located in the peripheral region, at least one described connection
Structure includes:
The first metal layer is set on the first substrate；
First insulating layer is set on the first substrate and the first metal layer；
Second metal layer is set on first insulating layer；
Second insulating layer is set in first insulating layer and the second metal layer, wherein first insulating layer and institute
The combination for stating second insulating layer has the first perforation, and the second insulating layer also has the second perforation, and first perforation is sudden and violent
Expose the first metal layer, and second perforation exposes the second metal layer；And
Conductive layer is set in the second insulating layer, and the conductive layer directly contacts described first via first perforation
Metal layer and via it is described second perforation directly contact the second metal layer, wherein it is described first perforation with it is described second perforation
Each of be at least 220 microns apart from the boundary；
The second substrate, the second substrate are to be arranged oppositely with the first substrate；And
Frame glue is set between the first substrate and the second substrate and is located in the peripheral region, and the frame glue is in the week
Extended by the boundary towards the viewing area in border area and covers at least one described connection structure on the display base plate
At least one of.
2. display panel as described in claim 1, which is characterized in that each of at least one described connection structure distance
The boundary of the first substrate is at most 0.9 times of the width of the peripheral region.
3. display panel as claimed in claim 2, which is characterized in that the width of the peripheral region is at least 0.8 millimeter.
4. display panel as described in claim 1, which is characterized in that the conductive layer is transparency conducting layer.
5. display panel as claimed in claim 4, which is characterized in that each pixel unit includes thin film transistor (TFT), institute
Stating thin film transistor (TFT) includes grid, source electrode and drain electrode；
Wherein, one in the grid and the first metal layer and the second metal layer belongs to same layer, and the source
Another in pole, the drain electrode and the first metal layer and the second metal layer belongs to same layer.
6. display panel as claimed in claim 4, which is characterized in that each pixel unit is comprising pixel electrode and jointly
Electrode；
Wherein one in the pixel electrode and the common electrode and the conductive layer belong to same layer.
7. display panel as described in claim 1, which is characterized in that also include:
Driving circuit is set on the first substrate and is located in the peripheral region, the driving circuit include it is described at least
One connection structure.
8. display panel as claimed in claim 7, which is characterized in that the driving circuit also includes signal lead, connects
Line and the electronic component for connecting the connection cabling；
Wherein, one in the first metal layer and the second metal layer is a part of the signal lead, and described
Another in the first metal layer and the second metal layer is described a part for connecting cabling.
9. display panel as claimed in claim 7, which is characterized in that the driving circuit also includes thin film transistor (TFT), described
Thin film transistor (TFT) includes grid, source electrode and drain electrode；
Wherein, one in the grid and the first metal layer and the second metal layer belongs to same layer, the source electrode,
Another in the drain electrode and the first metal layer and the second metal layer belongs to same layer, and the source electrode with it is described
One in drain electrode is electrically connected to the grid via the connection structure.
10. display panel as claimed in claim 7, which is characterized in that the driving circuit also includes first film transistor
It is and described wherein the first film transistor includes first grid, the first source electrode and the first drain electrode with the second thin film transistor (TFT)
Second thin film transistor (TFT) includes second grid, the second source electrode and the second drain electrode；
Wherein the first grid, the second grid and the first metal layer belong to one in the second metal layer
Same layer, first source electrode, first drain electrode, second source electrode, it is described second drain electrode and the first metal layer with
Another in the second metal layer belongs to same layer, and one in first source electrode and first drain electrode is via institute
It states connection structure and is electrically connected to the second grid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810047180.7A CN110058465A (en) | 2018-01-18 | 2018-01-18 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810047180.7A CN110058465A (en) | 2018-01-18 | 2018-01-18 | Display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110058465A true CN110058465A (en) | 2019-07-26 |
Family
ID=67315031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810047180.7A Withdrawn CN110058465A (en) | 2018-01-18 | 2018-01-18 | Display panel |
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| Country | Link |
|---|---|
| CN (1) | CN110058465A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021072737A1 (en) * | 2019-10-18 | 2021-04-22 | 京东方科技集团股份有限公司 | Display panel |
| CN113219738A (en) * | 2021-04-20 | 2021-08-06 | 绵阳惠科光电科技有限公司 | Display panel and display device |
| CN113219740A (en) * | 2021-04-20 | 2021-08-06 | 绵阳惠科光电科技有限公司 | Display panel and display device |
| CN113359359A (en) * | 2021-04-20 | 2021-09-07 | 绵阳惠科光电科技有限公司 | Display panel and display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107134264A (en) * | 2016-02-26 | 2017-09-05 | 瀚宇彩晶股份有限公司 | Drive circuit and display device |
-
2018
- 2018-01-18 CN CN201810047180.7A patent/CN110058465A/en not_active Withdrawn
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107134264A (en) * | 2016-02-26 | 2017-09-05 | 瀚宇彩晶股份有限公司 | Drive circuit and display device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021072737A1 (en) * | 2019-10-18 | 2021-04-22 | 京东方科技集团股份有限公司 | Display panel |
| CN112997311A (en) * | 2019-10-18 | 2021-06-18 | 京东方科技集团股份有限公司 | Display panel |
| US11545069B2 (en) | 2019-10-18 | 2023-01-03 | Chongqing Boe Optoelectronics Technology Co., Ltd. | Display device having a shift register having interdigital transistor |
| CN112997311B (en) * | 2019-10-18 | 2023-06-20 | 京东方科技集团股份有限公司 | Display panel |
| CN113219738A (en) * | 2021-04-20 | 2021-08-06 | 绵阳惠科光电科技有限公司 | Display panel and display device |
| CN113219740A (en) * | 2021-04-20 | 2021-08-06 | 绵阳惠科光电科技有限公司 | Display panel and display device |
| CN113359359A (en) * | 2021-04-20 | 2021-09-07 | 绵阳惠科光电科技有限公司 | Display panel and display device |
| CN113359359B (en) * | 2021-04-20 | 2023-08-25 | 绵阳惠科光电科技有限公司 | Display panel and display device |
| CN113219740B (en) * | 2021-04-20 | 2023-08-29 | 绵阳惠科光电科技有限公司 | Display panel and display device |
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Application publication date: 20190726 |