CN110049331A - A kind of DVI unstrings system, method, equipment and storage medium - Google Patents
A kind of DVI unstrings system, method, equipment and storage medium Download PDFInfo
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- CN110049331A CN110049331A CN201910222688.0A CN201910222688A CN110049331A CN 110049331 A CN110049331 A CN 110049331A CN 201910222688 A CN201910222688 A CN 201910222688A CN 110049331 A CN110049331 A CN 110049331A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
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Abstract
The present invention provides a kind of DVI and unstrings system, method, and equipment and storage medium clock difference turn single-ended cell and receive DVI clock signal, and signal differential turns single-ended cell and receives DVI data-signal；Clock difference turns single-ended cell and carries out received clock signal to be converted into single-ended clock signal, sends PLL unit to；PLL unit carries out process of frequency multiplication to single-ended clock signal, obtains frequency multiplied clock signal, sends DDR unit to；Signal differential turns single-ended cell and receives differential signal, and differential signal is switched to single-ended signal, sends adjustable time delay unit to；Using the noiseproof feature of differential signal, the transmission of high-speed video ensure that.DVI vision signal is handled, the phase relation between clock signal and data-signal is adjusted, guarantees that clock is located at the center position of data, DDR unit is based on frequency multiplied clock signal and data-signal adjusted carries out processing of unstringing, and export, effective data de-serialization is to guarantee high-speed video transmission.
Description
Technical field
It unstrings system the present invention relates to digital video technology field more particularly to a kind of DVI, method, equipment and storage are situated between
Matter.
Background technique
Recently as the rapid development of video technique, parallel transmission rgb signal has been unable to meet actual demand.Very much
In, data serializing is needed to be transmitted using differential signal, it is most at present to use DVI agreement.DVI is to be based on
TMDS (Transition Minimized Differential Signaling, convert minimum differential signal) technology is transmitted
Digital signal.8bit data (every roadbed chrominance signal in R, G, B) are passed through minimum transition with advanced encryption algorithm by TMDS
It is encoded to 10bit data (comprising row field synchronization information, clock information, data DE, error correction etc.), after DC is balanced, using difference
Sub-signal transmits data, it has compared preferable Electro Magnetic Compatibility with LVDS, TTL, can be real with the private cable of low cost
Now long range, the digital data transmission of high quality.Here, DVI is a kind of interface standard of international openness, in PC, DVD, high definition
It is widely used in the equipment such as clear TV, high-resolution projector.
DVI agreement is exactly such a agreement, using the noiseproof feature of differential signal, carries out the transmission of high-speed video.
And when the DVI vision signal to such differential serial carries out image procossing, it usually needs it unstrings to differential signal, it is no
It is not available then.How to carry out effective data de-serialization is the premise for guaranteeing high-speed video transmission.
Summary of the invention
In order to overcome the deficiencies in the prior art described above, the present invention guarantees that high-speed video passes by effective data de-serialization
It is defeated, for this purpose, the present invention includes four aspect contents:
First aspect: it is related to a kind of DVI and unstrings system, comprising: clock difference turns single-ended cell, and signal differential turns single-ended list
Member, adjustable time delay unit, PLL unit and DDR unit；
Clock difference turns single-ended cell and is connect by PLL unit with DDR unit；
Clock difference turns single-ended cell for receiving clock signal, and received clock signal is carried out to be converted into single ended clock
Signal sends PLL unit to；PLL unit carries out process of frequency multiplication to single-ended clock signal, obtains frequency multiplied clock signal, sends to
DDR unit；
Signal differential turns single-ended cell and is connect by adjustable time delay unit with DDR unit；
Signal differential turns single-ended cell for receiving differential signal, and differential signal is switched to single-ended signal, is sent to adjustable
Delay unit；
Adjustable time delay unit is used to adjust the phase relation between clock signal and data-signal, guarantees that clock is located at data
Center position, then data-signal adjusted is sent to DDR unit；
DDR unit is based on frequency multiplied clock signal and data-signal adjusted carries out processing of unstringing, and exports.
It further illustrates, including multiple signal differentials turn single-ended cell, multiple adjustable time delay units and multiple DDR
Unit；
Each signal differential turns single-ended cell and provides the DVI interface of standard；
Signal differential turns single-ended cell, and it is logical that 10bit decoding parallel data is configured between adjustable time delay unit and DDR unit
Letter mode completes the work of unstringing of DVI, obtains available parallel data.
PLL unit is used to carry out 5 frequencys multiplication to TXC clock signal, generates TXC_5x signal, for the use of DDR unit.
5 frequency doubling clocks that DDR cell signal is used to that PLL unit to be cooperated to generate are generated using the double characteristic of DDR data
The data of 10 times of reference clocks, and the 10bit data flow after being unstringed.
Adjustable time delay unit is connected with delay trigger circuit；
Delay trigger circuit includes: resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, triode Q1 and
Triode Q2；
Triode Q1 base stage is connect with delay trigger circuit input terminal；
Triode Q1 collector is connect with resistance R11 second end and resistance R13 first end respectively；Resistance R11 first end and
Resistance R12 first end connects power supply respectively；Resistance R12 second end and triode Q2 collector connect delay trigger circuit output respectively
End；Resistance R13 second end and resistance R15 first end connect triode Q2 base stage, triode Q2 emitter and triode Q1 hair respectively
Emitter-base bandgap grading passes through resistance R14 respectively and is grounded；Resistance R15 second end ground connection.
Clock difference turns single-ended cell and also connect with delay trigger circuit, issues clock start signal to delay trigger circuit
Trigger signal, makes delay trigger circuit trigger adjustable time delay unit, and adjustable time delay unit is based on present clock difference and turns single-ended list
Member receives clock signal, adjusts the phase relation between clock signal and data-signal, guarantees that clock is located at the center position of data.
Second aspect of the present invention is related to: a kind of DVI unstrings method, and method includes:
Clock difference turns single-ended cell and receives DVI clock signal, and signal differential turns single-ended cell and receives DVI data-signal；
Clock difference turns single-ended cell and carries out received clock signal to be converted into single-ended clock signal, and it is mono- to send PLL to
Member；PLL unit carries out process of frequency multiplication to single-ended clock signal, obtains frequency multiplied clock signal, sends DDR unit to；
Signal differential turns single-ended cell and receives differential signal, and differential signal is switched to single-ended signal, sends adjustable delay to
Unit；
Adjustable time delay unit adjusts the phase relation between clock signal and data-signal, guarantees that clock is located at the center of data
Position, then data-signal adjusted is sent to DDR unit；
DDR unit is based on frequency multiplied clock signal and data-signal adjusted carries out processing of unstringing, and exports.
Third aspect present invention is related to: a kind of to unstring the equipment of system with DVI, comprising:
Memory, for storing computer program and DVI unstrings system；
Processor, for executing the computer program and DVI unstrings system, to realize that DVI unstrings system.
Fourth aspect present invention is related to: a kind of to unstring the computer readable storage medium of method with DVI, the computer
It is stored with computer program on readable storage medium storing program for executing, the computer program is executed by processor to realize that DVI unstrings method
Step.
As can be seen from the above technical solutions, the invention has the following advantages that
The present invention utilizes the noiseproof feature of differential signal, ensure that the transmission of high-speed video.DVI vision signal is carried out
Processing adjusts the phase relation between clock signal and data-signal, guarantees that clock is located at the center position of data, DDR unit base
Processing of unstringing is carried out in frequency multiplied clock signal and data-signal adjusted, and is exported, effective data de-serialization is to guarantee high speed
Transmission of video.
Detailed description of the invention
In order to illustrate more clearly of technical solution of the present invention, attached drawing needed in description will be made below simple
Ground introduction, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ordinary skill
For personnel, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is that DVI unstrings system embodiment schematic diagram；
Fig. 2 is single-ended signal processing circuit figure；
Fig. 3 is delay trigger circuit figure.
Specific embodiment
The present invention provides a kind of DVI and unstrings system, as shown in Figure 1, comprising: clock difference point turns single-ended cell 1, signal differential
Turn single-ended cell 2, adjustable time delay unit 3, PLL unit 4 and DDR unit 5；
Clock difference turns single-ended cell 1 and is connect by PLL unit 4 with DDR unit 5；
Clock difference turns single-ended cell 1 for receiving clock signal, when carrying out received clock signal to be converted into single-ended
Clock signal sends PLL unit 4 to；PLL unit 4 carries out process of frequency multiplication to single-ended clock signal, obtains frequency multiplied clock signal, passes
Give DDR unit 5；
Signal differential turns single-ended cell 2 and is connect by adjustable time delay unit 3 with DDR unit 5；Signal differential turns single-ended cell
Differential signal for receiving differential signal, is switched to single-ended signal, sends adjustable time delay unit to by 2；Adjustable time delay unit is used for
The phase relation between clock signal and data-signal is adjusted, guarantees that clock is located at the center position of data, then by number adjusted
It is believed that number being sent to DDR unit 5；DDR unit 5 is based on frequency multiplied clock signal and data-signal adjusted carries out processing of unstringing,
And it exports.
Technology as described herein may be implemented in hardware, software, firmware or any combination of them.The various spies
Sign is module, and unit or assembly may be implemented together in integration logic device or separately as discrete but interoperable logic
Device or other hardware devices.In some cases, the various features of electronic circuit may be implemented as one or more integrated
Circuit devcie, such as IC chip or chipset.
If realized within hardware, the present invention relates to a kind of devices, such as can be used as processor or integrated circuit dress
It sets, such as IC chip or chipset.Alternatively or additionally, if realized in software or firmware, the technology can
Realize at least partly by computer-readable data storage medium, including instruction, when implemented, make processor execute one or
More above methods.For example, computer-readable data storage medium can store the instruction such as executed by processor.
The present invention also provides a specific embodiment, system includes that multiple signal differentials turn single-ended cell 2, Duo Geke
Adjust delay unit 3 and multiple DDR units 5；Each signal differential turns single-ended cell 2 and provides the DVI interface of standard；Signal differential
Turn single-ended cell, 10bit is configured between adjustable time delay unit and DDR unit and decodes parallel data communication mode, completes DVI's
It unstrings work, obtains available parallel data.
Multiple signal differentials turn single-ended cell 2, and multiple adjustable time delay units 3 and multiple DDR units 5 are integrated in
FPGA.It can also include that one or more processors are executed by processing circuit, such as one or more digital signal processors
(DSP), general purpose microprocessor, application-specific integrated circuit (ASICs), field programmable gate array (FPGA) or other etc.
Valence object is integrated circuit or discrete logic.Therefore, term " processor, " is any aforementioned due to that can refer to as used herein
Structure or any other structure are more suitable for the technology as described herein realized.In addition, in some respects, being retouched in the disclosure
The function of stating can be provided in software module and hardware module.
Adjustable time delay unit is in the phase relation being adjusted between clock signal and data-signal, by delay trigger circuit
It is triggered, and clock difference turns single-ended cell and also connect with delay trigger circuit, issues clock signal to delay trigger circuit
Start trigger signal, delay trigger circuit is made to trigger adjustable time delay unit, adjustable time delay unit is based on present clock difference and turns single
End unit receives clock signal, adjusts the phase relation between clock signal and data-signal, guarantees that clock is located at the center of data
Position.Clock difference turns single-ended cell reception clock signal in this way, synchronizes and triggers delay trigger circuit, and then to adjustment clock
Phase relation between signal and data-signal plays positive response.As shown in figure 3,
Adjustable time delay unit is connected with delay trigger circuit；Delay trigger circuit includes: resistance R11, resistance R12, resistance
R13, resistance R14, resistance R15, triode Q1 and triode Q2；Triode Q1 base stage and delay trigger circuit input terminal connect
It connects；Triode Q1 collector is connect with resistance R11 second end and resistance R13 first end respectively；Resistance R11 first end and resistance
R12 first end connects power supply respectively；Resistance R12 second end and triode Q2 collector connect delay trigger circuit output end respectively；Electricity
Resistance R13 second end and resistance R15 first end connect triode Q2 base stage, triode Q2 emitter and triode Q1 emitter point respectively
It is not grounded by resistance R14；Resistance R15 second end ground connection.Delay trigger circuit with signal filter, it is anti-interference and to triggering believe
Number effect amplified.
PLL unit is used to carry out 5 frequencys multiplication to TXC clock signal, generates TXC_5x signal, for the use of DDR unit.DDR
5 frequency doubling clocks that cell signal is used to that PLL unit to be cooperated to generate, using the double characteristic of DDR data, when generating 10 times of benchmark
The data of clock, and the 10bit data flow after being unstringed.
It includes: single-ended signal processing circuit that further signal differential, which turns single-ended cell,；Signal differential turns single-ended cell and connects
While the differential signal of receipts is converted, also single-ended signal is handled.As shown in Fig. 2, single-ended signal processing circuit
It include: resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, transport and placing device U1, capacitor C1,
Capacitor C2 and capacitor C3；Resistance R1 first end and resistance R2 first end distinguish order end signal processing circuit input terminal；Resistance
R1 second end is connected with resistance R5 first end, capacitor C1 first end and capacitor C2 first end respectively；Resistance R2 second end difference
With resistance R5 second end, capacitor C1 second end and the connection of capacitor C3 first end；Capacitor C2 second end and resistance R3 first end connect
It connects；Capacitor C3 second end is connect with resistance R4 first end；Resistance R3 second end respectively with resistance R7 first end and transport and placing device U1 mono-
Foot connection；Resistance R4 second end is connect with bis- foot of transport and placing device U1 and resistance R6 first end respectively；The second termination power of resistance R6；Fortune
Tri- foot of device U1 ground connection is put, tetra- foot of transport and placing device U1 connects power supply；Resistance R7 second end respectively with five foot of transport and placing device U1, resistance R8 first
End, the connection of single-ended signal processing circuit output end；Resistance R8 second end ground connection；Resistance R1, resistance R2 and resistance R5 are for limiting
Stream, resistance R6 and resistance R7 adjust the gain range of single-ended signal；Capacitor C2 and resistance R3 play filter action；Capacitor C3 and electricity
Resistance R4 plays filter action；Resistance R8 plays filter action.It is based on DVI agreement in this way, improves the anti-interference spy of single-ended signal
Property, meet the transmission of high-speed video.Effective data de-serialization is to guarantee high-speed video transmission.
A preferred method provided by the invention are as follows: TXC is connected to DVI clock signal, by TXD0, TXD1, TXD2 connection
To DVI data-signal, signal turns single-ended cell by difference and is converted to single-ended signal, by adjustable time delay unit, adjusts data
With the phase relation of clock.Clock obtains the clock TXC_5x of 5 frequencys multiplication by PLL unit.Final data passes through DDR unit, benefit
With the double characteristic of DDR cell data rate, cooperates 5 frequency doubling clocks, obtain the de-serializing data of 10bit bit wide.
It unstrings method the present invention also provides a kind of DVI, method includes:
Clock difference turns single-ended cell and receives DVI clock signal, and signal differential turns single-ended cell and receives DVI data-signal；
Clock difference turns single-ended cell and carries out received clock signal to be converted into single-ended clock signal, and it is mono- to send PLL to
Member；PLL unit carries out process of frequency multiplication to single-ended clock signal, obtains frequency multiplied clock signal, sends DDR unit to；
Signal differential turns single-ended cell and receives differential signal, and differential signal is switched to single-ended signal, sends adjustable delay to
Unit；
Adjustable time delay unit adjusts the phase relation between clock signal and data-signal, guarantees that clock is located at the center of data
Position, then data-signal adjusted is sent to DDR unit；
DDR unit is based on frequency multiplied clock signal and data-signal adjusted carries out processing of unstringing, and exports.
It unstrings the equipment of system the present invention also provides a kind of with DVI, comprising:
Memory, for storing computer program and DVI unstrings system；
Processor, for executing the computer program and DVI unstrings system, to realize that DVI unstrings system.
It unstrings the computer readable storage medium of method the present invention also provides a kind of with DVI, it is described computer-readable to deposit
Be stored with computer program on storage media, the computer program be executed by processor with realize DVI unstring method the step of.
The computer program product of computer-readable medium can form a part, may include packaging material.Data
Computer-readable medium may include computer storage medium, such as random access memory (RAM), read-only memory
(ROM), nonvolatile RAM (NVRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory, magnetic or
Optical data carrier and analog.In some embodiments, a kind of manufacture product may include that one or more computers can
Read storage media.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
- The system 1. a kind of DVI unstrings characterized by comprising clock difference turns single-ended cell, and signal differential turns single-ended cell, Adjustable time delay unit, PLL unit and DDR unit；Clock difference turns single-ended cell and is connect by PLL unit with DDR unit；Clock difference turns single-ended cell for receiving clock signal, and received clock signal is carried out to be converted into single ended clock letter Number, send PLL unit to；PLL unit carries out process of frequency multiplication to single-ended clock signal, obtains frequency multiplied clock signal, sends DDR to Unit；Signal differential turns single-ended cell and is connect by adjustable time delay unit with DDR unit；Signal differential turns single-ended cell for receiving differential signal, and differential signal is switched to single-ended signal, sends adjustable delay to Unit；Adjustable time delay unit is used to adjust the phase relation between clock signal and data-signal, guarantees that clock is located at the center of data Position, then data-signal adjusted is sent to DDR unit；DDR unit is based on frequency multiplied clock signal and data-signal adjusted carries out processing of unstringing, and exports.
- The system 2. DVI according to claim 1 unstrings, which is characterized in thatIt includes: single-ended signal processing circuit that signal differential, which turns single-ended cell,；Single-ended signal processing circuit includes: resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, electricity Hinder R8, transport and placing device U1, capacitor C1, capacitor C2 and capacitor C3；Resistance R1 first end and resistance R2 first end distinguish order end signal processing circuit input terminal；Resistance R1 second end respectively with Resistance R5 first end, capacitor C1 first end and the connection of capacitor C2 first end；Resistance R2 second end is connected with resistance R5 second end, capacitor C1 second end and capacitor C3 first end respectively；Capacitor C2 Two ends are connect with resistance R3 first end；Capacitor C3 second end is connect with resistance R4 first end；Resistance R3 second end is connect with resistance R7 first end and mono- foot of transport and placing device U1 respectively；Resistance R4 second end respectively with transport and placing device Bis- foot of U1 is connected with resistance R6 first end；The second termination power of resistance R6；Tri- foot of transport and placing device U1 ground connection, tetra- foot of transport and placing device U1 connect electricity Source；Resistance R7 second end respectively with five foot of transport and placing device U1, resistance R8 first end, single-ended signal processing circuit output end connection；Electricity Hinder R8 second end ground connection；Resistance R1, resistance R2 and resistance R5 are used for current limliting, and resistance R6 and resistance R7 adjust the gain range of single-ended signal；Capacitor C2 and resistance R3 play filter action；Capacitor C3 and resistance R4 play filter action；Resistance R8 plays filter action.
- The system 3. DVI according to claim 1 or 2 unstrings, which is characterized in thatTurn single-ended cell, multiple adjustable time delay units and multiple DDR units including multiple signal differentials；Each signal differential turns single-ended cell and provides the DVI interface of standard；Signal differential turns single-ended cell, and 10bit is configured between adjustable time delay unit and DDR unit and decodes parallel data communication side Formula completes the work of unstringing of DVI, obtains available parallel data.
- The system 4. DVI according to claim 1 or 2 unstrings, which is characterized in thatPLL unit is used to carry out 5 frequencys multiplication to TXC clock signal, generates TXC_5x signal, for the use of DDR unit.
- The system 5. DVI according to claim 4 unstrings, which is characterized in that5 frequency doubling clocks that DDR cell signal is used to that PLL unit to be cooperated to generate generate 10 times using the double characteristic of DDR data 10bit data flow in the data of reference clock, and after being unstringed.
- The system 6. DVI according to claim 1 or 2 unstrings, which is characterized in thatAdjustable time delay unit is connected with delay trigger circuit；Delay trigger circuit includes: resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, triode Q1 and three poles Pipe Q2；Triode Q1 base stage is connect with delay trigger circuit input terminal；Triode Q1 collector is connect with resistance R11 second end and resistance R13 first end respectively；Resistance R11 first end and resistance R12 first end connects power supply respectively；Resistance R12 second end and triode Q2 collector connect delay trigger circuit output end respectively；Electricity Resistance R13 second end and resistance R15 first end connect triode Q2 base stage, triode Q2 emitter and triode Q1 emitter point respectively It is not grounded by resistance R14；Resistance R15 second end ground connection.
- The system 7. DVI according to claim 6 unstrings, which is characterized in thatClock difference turns single-ended cell and also connect with delay trigger circuit, issues clock start signal triggering to delay trigger circuit Signal, makes delay trigger circuit trigger adjustable time delay unit, and adjustable time delay unit turns single-ended cell based on present clock difference and connects Clock signal is received, the phase relation between clock signal and data-signal is adjusted, guarantees that clock is located at the center position of data.
- A kind of method 8. DVI unstrings, which is characterized in that method includes:Clock difference turns single-ended cell and receives DVI clock signal, and signal differential turns single-ended cell and receives DVI data-signal；Clock difference turns single-ended cell and carries out received clock signal to be converted into single-ended clock signal, sends PLL unit to； PLL unit carries out process of frequency multiplication to single-ended clock signal, obtains frequency multiplied clock signal, sends DDR unit to；Signal differential turns single-ended cell and receives differential signal, and differential signal is switched to single-ended signal, sends adjustable time delay unit to；Adjustable time delay unit adjusts the phase relation between clock signal and data-signal, guarantees that clock is located at the center position of data It sets, then data-signal adjusted is sent to DDR unit；DDR unit is based on frequency multiplied clock signal and data-signal adjusted carries out processing of unstringing, and exports.
- 9. a kind of unstring the equipment of system with DVI characterized by comprisingMemory, for storing computer program and DVI unstrings system；Processor, for executing the computer program and DVI unstrings system, to realize such as claim 1 to 7 any one institute DVI is stated to unstring system.
- 10. a kind of unstring the computer readable storage medium of method with DVI, which is characterized in that the computer-readable storage Computer program is stored on medium, the computer program is executed by processor to realize that DVI as claimed in claim 8 unstrings The step of method.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111858415A (en) * | 2020-07-30 | 2020-10-30 | 山东超越数控电子股份有限公司 | Multichannel and multiprotocol hardware acceleration method for data receiving and storing |
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| CN104954721A (en) * | 2015-06-15 | 2015-09-30 | 中国航空无线电电子研究所 | FPGA (Field Programmable Gate Array)-based DVI (Digital Visual Interface) video receiving and decoding method |
| CN106126380A (en) * | 2016-06-21 | 2016-11-16 | 福州瑞芯微电子股份有限公司 | A kind of LVDS interface method of testing based on FPGA and system |
| CN106454187A (en) * | 2016-11-17 | 2017-02-22 | 凌云光技术集团有限责任公司 | FPGA system having Camera Link interface |
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| CN111858415A (en) * | 2020-07-30 | 2020-10-30 | 山东超越数控电子股份有限公司 | Multichannel and multiprotocol hardware acceleration method for data receiving and storing |
| CN111858415B (en) * | 2020-07-30 | 2024-03-15 | 超越科技股份有限公司 | Multi-channel multi-protocol hardware acceleration method for data receiving and storing |
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