201011547 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種單傳輸線傳輸介面(Single_ wke Transmission Interface)與單傳輸線傳輸方法，特別θ指一 - 能夠傳送位址與資料的單傳輸線傳輸介面與方法。7C曰 【先前技術】 目前之通訊介面如I2C，SPI，SMBUS中，均需要至少 兩條傳輸線，一條傳輸資料、一條傳輸時脈。如果能以單 一傳輸線來達成資料和時脈的傳輸，將可減少接腳數目， 特別是對於低接腳數目的積體電路而言，更顯重要。因此， 先前技術如美國專利第7127631號案和第7〇8祕號案 中丄提出單線序列傳輸方式，其方法如第1圖所示.，係利 =單-傳輸線上所傳輸之EN/SET訊號的長時間高位準、長 時間低位準、以及高低轉交㈣化來分職表三種狀 態^接收端侧到EN/SET訊號上升緣時即被致能開始接 收#料（如波形Enable所示），並根據ΕΝ/SET訊號而對應 產生時脈（如雜波形所示），_減端的計數器開始針 對ΕΝ/SET訊號的上升緣進行計數（1〜n)。當接收端債測 到ΕΝ/SET訊號下降緣時即開始啟動計時’若在時限内未偵 ' 綱*""上升緣時’卿歧能訊號Enable，並將計數歸 零’且時脈也隨之停止。 上述，前技術中’並不清楚應如何傳遞資料「0」，且 二任-人貝料傳遞的時間長度並不固定，致能訊號如祕 自啟始至停止之間科間長_視射相絲蚊.；此對 201011547 於某些應用場合而言並不理想。 面與方法 種=父發日脚針耻述騎齡之不足，提出 =在固咖内傳送位址與資料的單傳輪線傳= 【發明内容】 目的在提供一種單傳輸線傳輸介面。201011547 Nine, invention description: [Technical field of the invention] The present invention relates to a single transmission line transmission interface (Single_Wke Transmission Interface) and a single transmission line transmission method, in particular θ refers to a single transmission line transmission interface capable of transmitting address and data And method. 7C曰 [Prior Art] Currently, the communication interface, such as I2C, SPI, SMBUS, requires at least two transmission lines, one transmission data and one transmission clock. If the data and clock transmission can be achieved with a single transmission line, the number of pins can be reduced, especially for integrated circuits with a low number of pins. Therefore, the prior art, such as the U.S. Patent No. 7,276,631 and the No. 7-8 secret file, proposes a single-line serial transmission method, which is shown in Fig. 1. The EN/SET transmitted on the single-transmission line The long-term high level of the signal, the long time low level, and the high and low turnover (four) are divided into three states: the receiving end side is enabled to start receiving when the EN/SET signal rises (as shown by the waveform Enable) And according to the ΕΝ / SET signal corresponding to the generation of the clock (as shown in the hybrid waveform), the counter of the _ subtraction starts counting (1 ~ n) for the rising edge of the ΕΝ / SET signal. When the receiver's debt detects the falling edge of the SET/SET signal, it starts the timing. If it is not detected within the time limit, the program will be able to "zero" and clock the count. It also stopped. As mentioned above, in the prior art, it is not clear how the data "0" should be transmitted, and the length of time for the transmission of the two-person-baked materials is not fixed. The signal can be transmitted from the beginning to the end of the period. Phase silk mosquitoes; this pair 201011547 is not ideal for some applications. Face and method Kind = father hair pin and foot masochism, lack of riding age, proposed = single pass transmission in the solid coffee transfer address and data transmission = [Summary] The purpose is to provide a single transmission line transmission interface.
號的方法 " —目的在提供—種彻單傳輸線來傳輸訊 面 ，:、之目的’本發明提供了—種單傳輸線傳輸介 …G3 ·解；Iff ’供接收由—單傳輸線而來之單傳 磁’並根據料傳輸線峨而解碼產生 1 該解碼 及計^器，根據該單傳齡峨之上升或下降之其中二 ，計算固定之第一時限以決定-傳輸期間，其中 器僅在該傳輸期間内解碼產生資訊。 人此外，根據本發明，也提供了一種單傳輸線傳輸方法， 匕含.藉由一單傳輸線提供單傳輸線訊號；以及僅在該單 傳輸線訊號之上升或下降之其中—緣發生後-段固定之第 —時限内傳輸資訊，該第一時限定義一傳輸期間。. 上述傳輸介面與上述方法中，可在每次傳輸期間内傳 輸一個二進位位元的資訊，或以一次傳輸期間中該單傳輸 線訊號之位準狀態出現次數表示資訊。 上述傳輸介面與上述方法中，可將多次傳輸期間内傳 輪的貧訊構成資訊組合，每一資訊組合可包括位址與資料。 201011547 上述傳輸介面與上述方法中，可在該單傳輸線訊號之 上升或下降之另-緣發生後計算一固定之第二時限，若在 此時間内該單傳輪線訊號之位準不變化，則在該第二時限 結束後緊接之次一傳輸期間中所傳輸的資訊為位址。 ' 此外，亦可在該第二_結輕產生-致能訊號。 底下藉由具體實施例詳加說明，當更容易瞭解本發明 之目的、技術内容、特點及其所達成之功效。 ^ 【實施方式】 請參考第2圖，在本發明中，同樣將在單傳輸線上傳 輸的訊號稱為ΕΝ/SET訊號。接收端之積體電路1〇〇中包含 傳輸介面10、暫存器20與核心電路30。傳輸介面1〇接收 ΕΝ/SET訊號’將其解碼產生資訊（包含位址及/或資料）； 資。il傳送至暫存器20十對應的位址内，再由積體電路1〇〇 使用來作各種用途，例如設定核心電路3〇之過電壓保護上 限值、發光二極體的電流量、等等，視積體電路1〇〇的功 能而定。 請參考第3圖，傳輸介面1〇中包含解碼器12和計時 器14。解碼器12將所收到的ΕΝ/SET訊號予以解碼，且計 時器14根據ΕΝ/SET訊號而啟動計時；解碼與計時器時限 - 之間的關係請見第4圖。根據ΕΝ/SET訊號的下降緣，計時 器14啟動計時一段固定長度的時間τ，在此時間中，EN/ s Ε τ 訊號即可傳輸資訊（如第4圖中的虛線所示）；而當到達計 時時限T之後’ ΕΝ/SET訊號即不再傳輸資訊，直到解碼器 201011547 12偵測到ΕΝ/SET訊號的下降緣，並再次啟動計時器 14 :十時。在本發明中’任-次資訊（含位址及/或資料） 的傳輸時間長度是固定的，即計時時限丁。 =在上述架構下，可以有各種傳輸協定方式來傳輸資 訊明參考第5圖之實施例，在本實施例中於每一次傳輸 期間内僅傳輸一個二進位位元的資訊，當在計時時限τ内 並未出現1¾位準時即表示〇 ’出現高位树即表示卜如採 紐傳輪協定，則可使好次傳輸來表示多個位元的資 糝 3孔’或使用多次傳輸來分別對多個暫存器傳輸資訊；第6 f表^傳輸刪的資訊，或對三個暫存器各別傳輸0, 1，0。 圖中之厂1」以上下兩波形皆可表示。對接收端而言， 不論前後兩次EN/SET訊號的下降緣間隔多久，例如圖中之 緣61與62'62與63、63與64之間的時間長度皆不 一致，但接收端僅需要在固定的計時時限τ嶋收資訊即 可。 =再參閱第7圖’其中顯示本發g⑽另—個實施例， ❹ 在本貫知例中係於每一次傳輸期間内視ΕΝ/SET訊號的高 位準出現次數來表示資訊的内容，例如圖中第一次傳輸期 間y，傳輸的資訊是「3」，第二次傳輸期間τ所傳輸的資 — 訊=5」。與前一實施例相同地，若在傳輸期間Τ内未出 現南位準’則表示〇。如使用此種傳輪協定，則每一次傳輸 ，間内所傳輸㈣訊’便不是二驗的—她元。在傳輸 ”面之解碼器12内可設置計數器（未示出），便可將 ΕΝ/SET訊號的高位準出現次數轉換為二進位數字。 8 201011547 若暫存器20中含有多個儲存位址（例如，各位址儲存 不同的資料，用以控制積體電路100中的不同功能），則根 據本發明，可利用ΕΝ/SET訊號來對不同的功能進行設定， 方即"T透過EN/SET 虎的傳輸’將不同的資料儲存於不同 的暫存器位址。請參閱第8圖，其中顯示本發明的另—個 實施例，在本實施例中係於每一次傳輸期間内對不同的暫 存器位址依序儲存資料，例如圖中第一次傳輸期間T係對 第一儲存位址傳輸資料「3」，第二次傳輸期間τ係對第二 參 儲存位址傳輸資料「4」’次一傳輸期間再對次一儲存位址 傳輸資料。 另一種方式請參見第9圖的實施例，在本實施例中係 在其中一次傳輸期間先傳輸位址，緊接著下次傳輸期間則 傳輸對應於該位址的資料，因傳輸中定義了所欲儲存的暫 存器位址，故可以不必依暫存器的位址次序來傳輸。如圖 所示，第一次傳輸期間Τ係對儲存位址⑶傳輸資料「4」， 第二次傳輸期間Τ係對儲存位址(2)傳輸資料「3」，以兩次 參 傳輸期間分別定義「位址」與「資料」。至於接收端如何辨 識本次傳輸是位址或資料？有各種方法可行，圖中舉一 例，可自ΕΝ/SET訊號的上升緣開始計算時間，當其停留在 高位準超過預設時限t時，即表示次一下降緣後所傳輸的資 - 訊為位址，並繼續依據「位址」、「資料」、「位址」、「資料」 的格式傳遞f訊或者，為了安全起見，也可在每次傳輸 位址之前提供訊號t，亦即在波段65的位置，也可使EN/SET 訊號停留在高位準的時間超過預設時限t，以確保接收端認 201011547 知本次傳輸是位址。 請再參見第10圖的實施例並對照第1丨圖，在本實施 例中傳輸介面10 (或其解碼器12)採取序進並出 (serial-in-parallel-out)的方式將資訊傳遞給暫存器2()。 ΕΝ/SET訊號使用n次傳輸期間傳輸^個二進位位元的資料 (位元0〜位元(η-1))，之後ΕΝ/SET訊號停留在高位準超過 預設時限t。傳輸介面10對此解碼，在其位元〇至位元(η-1) 的傳輸線上閂鎖住對應的資料，但暫存器2〇尚未接收，直 Φ 到傳輸介面10根據超過時間t的高位準而產生致能訊號 enable，暫存器20才受致能而將位元〇至位元(n_1}的資料 一次寫入其中。 對照第9圖與第11圖，可發現兩實施例中時限t的作 用並不相同，但這兩種作用（「定義位址」與「致能暫存器 2〇」）彼此並不衝突。請參見第12圖的實施例並對照第η 圖’在本實施例中併用前兩實施例的協定，當EN/SET訊號 停留在高位準超過預設時限t時，傳輸介面1〇產生致能訊 ❹ 號enable ’並將次一下降緣後的資訊認定為位址（本例中為 位址(3))’但再次一下降緣後的資訊則認定為位元〇至位元 (n-1)的資料’之後等到ΕΝ/SET訊號再次停留在高位準超過 預設時限t時，便將位元0至位元(η_ι)的資料寫入暫存器 ' 20的位址(3)中。當然，在此過程中，傳輸介面1〇的解碼 器12可此需將位址(3)轉換為二進位碼，才能透過位址傳輸 線傳送給暫存器20。 因暫存器的位址數目通常較低，而資料的内容數目則 201011547 可能較大’故如本例所示’在一次傳輸期間中以en/set 訊號的尚位準出現次數來表示位址，但在多次傳輸期間中 以二進位方式來表示資料，不失為一種較佳的方式。 請再參見第14圖的實施例並對照第15圖，在本實施 例中傳輸介面10係透過傳輸線依序對多個暫存器位址傳送 資料。本圖實施例與第8圖實施例相似，差別在於暫存器 20僅在受致能時才同時寫入多筆資料。請注意在暫存器 受致能的時段中，EN/SET訊號的下降緣並不被視為傳輸期 φ 間的起始，以避免混淆。當EN/SET訊號停留在低位準超過 時限T之後’致能訊號enable即回復至低位準，此後en/set Λ號的下降緣才被視為傳輸期間的起始。此安排的目的是 確保致能訊號enable的時間夠長，使暫存器20有足夠的寫 入時間。如無此顧慮’則當然亦可如第13圖的左方，使致 能訊號enable跟隨EN/SET訊號的下降緣而回復至低位準。 請再參見第16圖的實施例並對照第17圖，本實施例 與第12、13圖的實施例相似，但在本實施例中EN/SET訊The method of "number" is intended to provide a single transmission line for transmitting signals, and the purpose of the present invention is to provide a single transmission line transmission ... G3 · solution; Iff 'for receiving by a single transmission line Single-transmission 'and decoding according to the material transmission line 产生 to generate 1 the decoding and counting device, according to the rise or fall of the single-age age ,, calculate a fixed first time limit to determine - the transmission period, wherein the device is only in the transmission Decoding during the period generates information. In addition, according to the present invention, a single transmission line transmission method is also provided, which comprises: providing a single transmission line signal by a single transmission line; and only after the rising or falling of the single transmission line signal - after the edge occurs - the segment is fixed The information is transmitted within the first time limit, and the first time limit defines a transmission period. In the above transmission interface and the above method, information of one binary bit may be transmitted during each transmission period, or information may be represented by the number of occurrences of the level state of the single transmission line signal in one transmission period. In the above transmission interface and the above method, the information of the poor traffic in the multiple transmission period may be combined, and each information combination may include the address and the data. 201011547 The above transmission interface and the above method may calculate a fixed second time limit after the occurrence of another rise or fall of the single transmission line signal, if the level of the single transmission line signal does not change during this time, The information transmitted during the next transmission period immediately after the end of the second time limit is an address. In addition, it is also possible to generate a signal at the second _ junction. The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments. [Embodiment] Please refer to Fig. 2. In the present invention, the signal transmitted on the single transmission line is also referred to as a ΕΝ/SET signal. The integrated circuit 1 接收 of the receiving end includes a transmission interface 10, a register 20 and a core circuit 30. The transmission interface 1 receives the ΕΝ/SET signal 'decodes it to generate information (including address and/or data); Il is transmitted to the address corresponding to the tenter 20 and used by the integrated circuit 1 for various purposes, such as setting the upper limit of the overvoltage protection of the core circuit 3, the amount of current of the LED, Etc., depending on the function of the integrated circuit. Referring to Figure 3, the decoder 12 and the timer 14 are included in the transmission interface 1A. The decoder 12 decodes the received ΕΝ/SET signal, and the timer 14 starts timing according to the ΕΝ/SET signal; the relationship between decoding and the timer time limit is shown in Fig. 4. According to the falling edge of the SET/SET signal, the timer 14 starts timing for a fixed length of time τ, during which time the EN/s Ε τ signal can transmit information (as indicated by the dashed line in Fig. 4); After the time limit T is reached, the ΕΝ/SET signal will no longer transmit information until the decoder 201011547 12 detects the falling edge of the SET/SET signal and starts the timer 14 again: ten o'clock. In the present invention, the transmission time length of the 'any-time information (including the address and/or the data) is fixed, that is, the timing time limit. In the above architecture, there may be various transmission protocol manners for transmitting information. Referring to the embodiment of FIG. 5, in this embodiment, only one binary bit information is transmitted during each transmission period, when the timing time τ is The absence of a 13⁄4 digit punctuality means that the occurrence of a high-level tree means that the Buru-Nu-Nan transmission agreement can transfer a good number of times to indicate the number of resources of a plurality of bits or use multiple transmissions to respectively Multiple registers store information; the 6th f table transmits the deleted information, or transmits 0, 1, 0 to each of the three registers. The two waveforms above and below the factory can be represented. For the receiving end, no matter how long the edge of the EN/SET signal is separated, for example, the lengths of the edges 61 and 62'62 and 63, 63 and 64 are inconsistent, but the receiving end only needs to A fixed timing time τ can be collected. = Referring again to Figure 7, which shows another embodiment of the present invention, ❹ In the present example, the content of the information is represented by the number of high-order occurrences of the ΕΝ/SET signal during each transmission period, for example, In the first transmission period y, the transmitted information is "3", and the information transmitted by τ during the second transmission period = 5". As in the previous embodiment, if the south level is not displayed within the transmission period, it means 〇. If such a transfer agreement is used, then every time the transmission is transmitted, the (four) message transmitted in the room is not the second test. A counter (not shown) can be set in the decoder 12 of the transmission face to convert the high level of occurrence of the SET/SET signal into a binary number. 8 201011547 If the register 20 contains multiple storage addresses (For example, the address stores different data for controlling different functions in the integrated circuit 100), according to the present invention, the ΕΝ/SET signal can be used to set different functions, that is, "T through EN/ The SET Tiger's transmission 'stores different data in different scratchpad addresses. Please refer to Figure 8, which shows another embodiment of the present invention, which in this embodiment is different for each transmission period. The scratchpad address stores data sequentially. For example, in the first transmission period, T transmits data "3" to the first storage address, and during the second transmission period, τ transmits data to the second storage address. 4" 'Transfer data to the next storage address during the next transmission. For another method, please refer to the embodiment of FIG. 9. In this embodiment, the address is transmitted first during one transmission, and the data corresponding to the address is transmitted during the next transmission, because the transmission defines the location. The address of the scratchpad to be stored, so it is not necessary to transfer according to the address order of the scratchpad. As shown in the figure, during the first transmission period, the data "4" is transmitted to the storage address (3), and during the second transmission period, the data "3" is transmitted to the storage address (2), respectively. Define "address" and "data". As for how the receiver recognizes that the transmission is a address or data? There are various methods available. For example, the time can be calculated from the rising edge of the SET/SET signal. When it stays at the high level and exceeds the preset time limit t, it means that the information transmitted after the next falling edge is Address, and continue to transmit the message according to the format of "address", "data", "address", "data" or, for security reasons, the signal t can be provided before each transmission address, ie In the position of the band 65, the EN/SET signal can also stay at the high level for more than the preset time limit t to ensure that the receiving end recognizes that the transmission is the address. Referring again to the embodiment of FIG. 10 and referring to FIG. 1, in the present embodiment, the transmission interface 10 (or its decoder 12) adopts a serial-in-parallel-out manner to transmit information. Give the scratchpad 2(). The ΕΝ/SET signal uses the data of the binary bits (bit 0~bit (η-1)) during n transmissions, and then the ΕΝ/SET signal stays at the high level for more than the preset time limit t. The transmission interface 10 decodes this, latching the corresponding data on the transmission line of its bit 〇 to the bit (η-1), but the buffer 2 〇 has not been received, and the Φ is transmitted to the transmission interface 10 according to the time t The high level generates the enable signal enable, and the register 20 is enabled to write the data of the bit to the bit (n_1} once. Compared with the 9th and 11th, it can be found in the two embodiments. The effect of the time limit t is not the same, but the two roles ("Definition Address" and "Enable Register 2") do not conflict with each other. Please refer to the embodiment of Figure 12 and compare it with the η figure' In the embodiment, the agreement of the first two embodiments is used. When the EN/SET signal stays at a high level and exceeds the preset time limit t, the transmission interface 1 generates an enable signal and enables the information after the next falling edge. For the address (in this case, the address (3))', but the information after the falling edge is determined as the data from the bit 〇 to the bit (n-1), and wait until the SET/SET signal stays high again. When the preset time limit t is exceeded, the data of the bit 0 to the bit (η_ι) is written into the address (3) of the temporary register '20. However, in this process, the decoder 12 of the transmission interface 1b can convert the address (3) into a binary code to be transmitted to the register 20 through the address transmission line. The number of addresses of the register Usually lower, and the number of contents of the data may be larger at 201011547. Therefore, as shown in this example, the address is represented by the number of occurrences of the en/set signal during a transmission period, but during multiple transmissions. It is a better way to represent the data in a binary manner. Please refer to the embodiment of Fig. 14 and refer to Fig. 15, in this embodiment, the transmission interface 10 sequentially transmits a plurality of temporary storage locations through the transmission line. The data is transmitted in the same manner as the embodiment in Fig. 8. The difference is that the register 20 writes multiple data at the same time only when enabled. Please note that during the period when the register is enabled, EN The falling edge of the /SET signal is not considered to be the beginning of the transmission period φ to avoid confusion. When the EN/SET signal stays at the low level and exceeds the time limit T, the enable signal is returned to the low level, after which en/ The falling edge of the set apostrophe is considered to be during transmission. The purpose of this arrangement is to ensure that the enable signal is enabled for a long time, so that the register 20 has sufficient write time. If there is no such concern, then of course, as shown in the left side of Figure 13, the enable signal The enable returns to the low level following the falling edge of the EN/SET signal. Referring again to the embodiment of Fig. 16 and referring to Fig. 17, this embodiment is similar to the embodiment of Figs. 12 and 13, but in this embodiment EN/SET News
• 號以二進位方式定義位址和資料。如圖所示，在EN/SET 訊號停留在高位準超過時限t之後，傳輸介面1〇的解碼器 12認知接下來所要傳送的訊號格式是η位元的位址和m位 元的資料，便在接續的n+m個傳輸期間進行對應的解碼， 並將解碼所得的資訊問鎖在位址和資料傳輸線上。接著， EN/SET訊號拉高至高位準並停留超過時限t，於是傳輸介 面10發出致能訊號enable致能暫存器20,將資料寫入所定 的位址中。 11 201011547 在如述所有實施例中’不僅任一次資訊（含位址及/ 或寅料）的傳輪時間長度τ是固定的，且接收端接收完整 的每組「位址」+「資料」之資訊時間長度也是固定的， 對於許多應用而言，較為便利。 以上已針對較佳實施例來說明本發明，唯以上所述 者，僅係為使熟悉本技術者易於了解本發明的内容而已， 並非用來限定本發明之權利範圍。對於熟悉本技術者，當 可在本發明精神内，立即思及各種等效變化；例如，各實 « ，例中高低位準的定義可以互換；又如，第3圖顯示計時 =。14是透過解碼器12接收ΕΝ/SET訊號而啟動計時，但計 時器14亦可直接接收EN/SET訊號而啟動計時，等等。故 凡依本發敗概念與精神所狀鱗變化或料，均應包 括於本發明之申請專利範圍内。 一 【圖式簡單說明】 圖式說明： • 第1圖示出先前技術中之單線序列傳輸方式。 第2圖與第3圖示出本發明之硬體結構實施例。 帛4圖說明根據計時時限τ來定義傳輸時間長度。 第5圖示出本發明的其中一個實施例。 又 6圖表不傳輸〇 1 〇的資訊，或對三個暫存器各別傳輸， 第7圖示出本發明的另-個實施例。 卜”’在每-人傳輸期間内對不同的暫存器位址依序 12 201011547 儲存資料。 第9圖示出本發明的另一個實施例。 第10圖與第11圖示出本發明的又另一個實施例。 ' 第12圖與第13圖示出本發明的再一個實施例。 ' 第14圖與第15圖示出本發明的另一個實施例。 第16圖與第17圖示出本發明的又另一個實施例。 參 【主要元件符號說明】 10傳輸介面 12解碼器 14計時器 20暫存器 30核心電路 61-65訊號波段 100接收端積體電路 ΕΝ/SET單傳輸線訊號 T時限 t時限• The number defines the address and data in binary mode. As shown in the figure, after the EN/SET signal stays at the high level and exceeds the time limit t, the decoder 12 of the transmission interface 1 recognizes that the signal format to be transmitted next is the address of the n-bit and the data of the m-bit, Corresponding decoding is performed during successive n+m transmissions, and the decoded information is locked on the address and data transmission lines. Then, the EN/SET signal is pulled high to the high level and stays longer than the time limit t, so the transmission interface 10 sends an enable signal enable enable register 20 to write the data into the specified address. 11 201011547 In all the embodiments described above, the transmission time length τ of not only one information (including address and/or data) is fixed, and the receiving end receives the complete set of "address" + "data". The length of the information is also fixed, which is convenient for many applications. The present invention has been described above with reference to the preferred embodiments, and the present invention is not intended to limit the scope of the present invention. For those skilled in the art, various equivalent changes can be immediately considered within the spirit of the present invention; for example, the definitions of the high and low levels in the actual «, in the example, can be interchanged; for example, the third figure shows the timing =. 14 is to start the timing by receiving the ΕΝ/SET signal through the decoder 12, but the timer 14 can also directly receive the EN/SET signal to start the timing, and the like. Therefore, all changes or materials according to the concept and spirit of this failure should be included in the scope of the patent application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS [FIG. 1] FIG. 1 shows a single-line sequence transmission method in the prior art. 2 and 3 show an embodiment of the hardware structure of the present invention. The 帛4 diagram illustrates the definition of the transmission time length based on the timing time τ. Figure 5 shows one of the embodiments of the present invention. Further, the chart does not transmit the information of 〇 1 ,, or transmits to each of the three registers, and FIG. 7 shows another embodiment of the present invention. </ RTI> "Storing data for different scratchpad addresses in sequence 12 201011547 during the per-person transmission period. Figure 9 shows another embodiment of the present invention. Figures 10 and 11 show the present invention. Still another embodiment. Fig. 12 and Fig. 13 show still another embodiment of the present invention. 'Fourteenth and fifteenth drawings show another embodiment of the present invention. Fig. 16 and Fig. 17 Still another embodiment of the present invention. [Main component symbol description] 10 transmission interface 12 decoder 14 timer 20 register 30 core circuit 61-65 signal band 100 receiving end integrated circuit ΕΝ / SET single transmission line signal T time limit t time limit