CN110032262A - One kind being based on JESD204B interface high-speed figure receive-transmit system power on configuration method - Google Patents
One kind being based on JESD204B interface high-speed figure receive-transmit system power on configuration method Download PDFInfo
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- CN110032262A CN110032262A CN201910308325.9A CN201910308325A CN110032262A CN 110032262 A CN110032262 A CN 110032262A CN 201910308325 A CN201910308325 A CN 201910308325A CN 110032262 A CN110032262 A CN 110032262A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
Abstract
The present invention discloses a kind of based on JESD204B interface high-speed figure receive-transmit system power on configuration method, this method includes connection high-speed figure receive-transmit system and powers on, and carries out hardware reset to ADC chip, DAC chip, LMK04828_AD clock chip and LMK04828_DA clock chip；First time register configuration is carried out to LMK04828_AD clock chip and LMK04828_DA clock chip, send SYNC synchronization signal and second of register configuration is carried out to LMK04828_AD clock chip and LMK04828_DA clock chip；And the JESD204B interface module of FPGA programmable logic device is resetted, parameter configuration, and starting Simultaneous Monitoring program are carried out to ADC chip, DAC chip register.Specification of the present invention high-speed figure receive-transmit system power on configuration process, it avoids the occurrence of clock and hits edge, the situation that system electrification is asynchronous or link is unstable, Simultaneous Monitoring program is added simultaneously, it avoids since the foundation of JESD204B interface link unsuccessfully leads to system crash, so that system has very high stability, anti-interference, reliability and environmental suitability.
Description
Technical field
The present invention relates to a kind of high-speed figure receive-transmit system power on configuration methods.It is based on more particularly, to one kind
JESD204B interface high-speed figure receive-transmit system power on configuration method.
Background technique
In our daily life, the demand of data service is increasing, thereupon for the band of communications facility etc.
Width require it is higher and higher, this just need to use in some equipment high speed data acquisition and data processing.
ADC/DAC chip mostly uses greatly traditional CMOS and LVDS interface at present, but companion chip sampling rate is not
It is disconnected to improve, particularly with the ADC/DAC chip of 500MSPS or more, it can generally reach the data throughput of tens G, it is traditional
Data transmission interface is difficult to meet design requirement.Moreover, the digital interface overwhelming majority of digital analog converter is connecing for difference LVDS
Mouthful, this has resulted in the difficulty of fabric swatch, just need to increase when the density of PCB is very big plate layer to cause printed board at
This rising.
JESD204B interface is a kind of novel ADC/DAC data transmission interface based on high speed SERDES, main at present
Connection between high speed analog-digital conversion signal conversion chip (ADCs and DACs) and logical device chip (FPGAs or ASICs),
There is strict requirement to the sequential relationship between device clock and synchronised clock.With digital analog converter conversion rate increasingly
Height is widely used on digital analog converter more and more.
Mainly have at 4 points using the benefit of JESD204B interface:
(1) simplify system design.When using traditional interface, if there are many port number of ADC, between ADC and FPGA
Wiring will be very intensive, and need the length of arrangement wire in each channel identical, and --- this point is realized relatively cumbersome --- otherwise will
It may make data quality-degradation.The wiring between ADC and FPGA can be then greatly simplified with JESD204B.
(2) number of pins is reduced.It is compared with traditional interface, number of pins can be greatly decreased in JESD204B, to reduce
The cost of fabric swatch.
(3) since wiring is simpler, number of pins is smaller, use JESD204B that encapsulation will be made smaller, simpler
It is single.
(4) the data transfer rate advantage of JESD204B will bring big bandwidth.
Fpga chip, ADC chip and DAC chip etc., FPGA and ADC/DAC are usually contained for high-speed figure receive-transmit system
Chip uses JESD204B interface protocol, and JESD204B agreement is higher for clock quality requirements, generally uses dedicated clock
Chip, so as to cause system configuration process complexity, be easy to appear clock hit along, system electrification is asynchronous or link is unstable
Situation, it is serious to directly result in system crash.
Accordingly, it is desirable to provide being based on JESD204B interface high-speed figure receive-transmit system power on configuration method.
Summary of the invention
The purpose of the present invention is to provide one kind to be based on JESD204B interface high-speed figure receive-transmit system power on configuration method,
Can specification high-speed figure receive-transmit system power on configuration process, avoid the occurrence of clock and hit along, system electrification is asynchronous or link
Unstable situation, while avoiding unsuccessfully leading to system crash due to the foundation of JESD204B interface link, so that system has
There are very high stability, anti-interference, reliability and environmental suitability.
In order to achieve the above objectives, the present invention adopts the following technical solutions:
One kind being based on JESD204B interface high-speed figure receive-transmit system power on configuration method, and this method is applied to high-speed figure
In receive-transmit system, which includes FPGA programmable logic device, ADC chip, DAC chip, LMK04828_AD
Clock chip, LMK04828_DA clock chip and clock distribute chip；Wherein
FPGA programmable logic device includes JESD204B interface module, ADC Simultaneous Monitoring module, ADC register configuration mould
Block, system reset module, DAC register configuration module, LMK04828 configuration generation module and LMK04828 register configuration
Module, wherein system reset module is electrically connected with ADC chip and DAC chip respectively by JESD204B interface module, and ADC is same
Step monitoring modular is electrically connected by JESD204B interface module with ADC chip, and system reset module passes through ADC register configuration mould
Block is electrically connected with ADC chip, and system reset module is electrically connected by DAC register configuration module with DAC chip, system reset mould
Block also configures generation module with ADC Simultaneous Monitoring module LMK04828 and LMK04828 register configuration module is electrically connected respectively
It connects, LMK04828 configuration generation module is electrically connected with LMK04828 register configuration module, LMK04828 register configuration module
It is interconnected with LMK04828_AD clock chip and LMK04828_DA clock chip by PCB trace；
FPGA programmable logic device is connect with host computer by optical fiber；
LMK04828_AD clock chip is electrically connected with ADC chip；
LMK04828_DA clock chip is electrically connected with DAC chip；
Clock distribution chip is electrically connected with LMK04828_AD clock chip and LMK04828_DA clock chip；And
Signal is derived from host computer and clock distribution chip electrical connection；
The high-speed figure receive-transmit system power on configuration method includes:
Step S1: connection high-speed figure receive-transmit system simultaneously powers on, to ADC chip, DAC chip, LMK04828_AD clock core
Piece and LMK04828_DA clock chip carry out hardware reset；
Step S2: first time register is carried out to LMK04828_AD clock chip and LMK04828_DA clock chip and is matched
It sets, send SYNC synchronization signal and LMK04828_AD clock chip and LMK04828_DA clock chip is posted for the second time
Storage configuration；And
Step S3: the JESD204B interface module of FPGA programmable logic device is resetted, to ADC chip, DAC chip
Register carries out parameter configuration, and starting Simultaneous Monitoring program.
Preferably, step S1 is specifically included:
Step S101: signal source inputs the homologous clock of 100M, the homologous clock of 200M and the homologous clock of 400M, and wherein 200M is same
Source clock is that the clock of LMK04828_AD clock chip inputs, and the homologous clock of 400M is the clock of LMK04828_DA clock chip
Input, the homologous clock of 100M enter the phaselocked loop of FPGA programmable logic device；
Step S102:FPGA programmable logic device carries out frequency dividing locking phase to the homologous clock of 100M, wherein the frequency-dividing clock of 10M
When reset and configuration as ADC chip, DAC chip, LMK04828_AD clock chip and LMK04828_DA clock chip
Clock；
Step S103: carrying out locking instruction after clock lock, when locking signal is high level, starts reset count, the
Terminate the hardware reset of DAC chip, LMK04828_AD clock chip and LMK04828_DA clock chip after one preset time；
Step S104: ADC chip is resetted using impulse form；And
Step S105: terminate the software reset of FPGA programmable logic device internal processes after the second preset time.
It is further preferred that the first preset time is 2 seconds.
It is further preferred that the second preset time is 3 seconds.
Preferably, step S2 is specifically included:
When step S201:FPGA programmable logic device internal processes terminate software reset, to LMK04828_AD clock chip
And LMK04828_DA clock chip carries out first time register configuration；
Step S202:LMK04828_AD clock chip and LMK04828_DA clock chip export sampling clock；
Step S203: receiving host computer and send after optical synchronous signal after third preset time, LMK04828_AD clock chip
Starting LMKAD_SYNC synchronization pulse, LMK04828_DA clock chip starts LMKDA_SYNC synchronization pulse,
LMKAD_SYNC synchronization pulse is the synchronization reset signal of LMK04828_AD clock chip, LMKDA_SYNC lock-out pulse
Signal is the synchronization reset signal of LMK04828_DA clock chip；
Step S204: after the 4th preset time after starting LMKDA_SYNC synchronization pulse, when to LMK04828_AD
Clock chip and LMK04828_DA clock chip carry out second of register configuration；And
Step S205:LMK04828_AD clock chip and LMK04828_DA clock chip export reference clock.
It is further preferred that third preset time is 16 milliseconds.
It is further preferred that the 4th preset time is 20 microseconds.
Preferably, step S3 is specifically included:
Step S301: second of register is carried out to LMK04828_AD clock chip and LMK04828_DA clock chip and is matched
It postpones, cancels the software reset of ADC register configuration module and JESD204B interface module；
Step S302: cancel the software reset of DAC register configuration module；
Step S303:JESD204B interface module carries out link setup；
Step S304:FPGA programmable logic device enters synchronous detecting state；And
Step S305: when there is synchronous failure, then start Simultaneous Monitoring program, activation system resets.
Beneficial effects of the present invention are as follows:
It is a kind of in the present invention to be based on JESD204B interface high-speed figure receive-transmit system power on configuration method, standardize high speed number
Word receive-transmit system power on configuration process avoids the occurrence of clock and hits edge, the situation that system electrification is asynchronous or link is unstable, together
When be added Simultaneous Monitoring program, avoid due to JESD204B interface link foundation unsuccessfully lead to system crash so that being
System has very high stability, anti-interference, reliability and environmental suitability.
Detailed description of the invention
Specific embodiments of the present invention will be described in further detail with reference to the accompanying drawing.
Fig. 1 shows the system block diagram based on JESD204B interface high-speed figure receive-transmit system in the present invention.
Fig. 2 shows the step processes based on JESD204B interface high-speed figure receive-transmit system power on configuration method in the present invention
Figure.
Fig. 3 shows the timing diagram based on JESD204B interface high-speed figure receive-transmit system power on configuration in invention.
Specific embodiment
In order to illustrate more clearly of the present invention, the present invention is done further below with reference to preferred embodiments and drawings
It is bright.Similar component is indicated in attached drawing with identical appended drawing reference.It will be appreciated by those skilled in the art that institute is specific below
The content of description is illustrative and be not restrictive, and should not be limited the scope of the invention with this.
It should be noted that belonging to " first ", " second " in description and claims of this specification and above-mentioned attached drawing
Etc. being not use to describe a particular order for distinguishing different objects.In addition, term " includes " and " having " and they
Any deformation, it is intended that cover and non-exclusive include.Such as contain the process, method of a series of steps or units, system,
Product or equipment are not limited to listed step or unit, but optionally further comprising the step of not listing or unit,
Or optionally further comprising the gas step intrinsic for these process, methods or equipment or unit.
One kind is disclosed based on JESD204B interface high-speed figure receive-transmit system power on configuration method, and this method is answered in the present invention
For in high-speed figure receive-transmit system, which to include FPGA programmable logic device, ADC chip, DAC core
Piece, LMK04828_AD clock chip, LMK04828_DA clock chip and clock distribute chip；Wherein FPGA programmable logic device
Including JESD204B interface module, ADC Simultaneous Monitoring module, ADC register configuration module, system reset module, DAC register
Configuration module, LMK04828 configuration generation module and LMK04828 register configuration module, wherein system reset module passes through
JESD204B interface module is electrically connected with ADC chip and DAC chip respectively, and ADC Simultaneous Monitoring module passes through JESD204B interface
Module is electrically connected with ADC chip, and system reset module is electrically connected by ADC register configuration module with ADC chip, system reset
Module is electrically connected by DAC register configuration module with DAC chip, system reset module also with ADC Simultaneous Monitoring module
LMK04828 configuration generation module and LMK04828 register configuration module are electrically connected, and LMK04828 configures generation module
Be electrically connected with LMK04828 register configuration module, LMK04828 register configuration module and LMK04828_AD clock chip and
LMK04828_DA clock chip is interconnected by PCB trace；FPGA programmable logic device is connect with host computer by optical fiber；
LMK04828_AD clock chip is electrically connected with ADC chip；LMK04828_DA clock chip is electrically connected with DAC chip；Clock point
Hair chip is electrically connected with LMK04828_AD clock chip and LMK04828_DA clock chip；And signal is derived from host computer and clock
Distribute chip electrical connection；The high-speed figure receive-transmit system power on configuration method includes:
Step S1: connection high-speed figure receive-transmit system simultaneously powers on, to ADC chip, DAC chip, LMK04828_AD clock core
Piece and LMK04828_DA clock chip carry out hardware reset；
Step S2: first time register is carried out to LMK04828_AD clock chip and LMK04828_DA clock chip and is matched
It sets, send SYNC synchronization signal and LMK04828_AD clock chip and LMK04828_DA clock chip is posted for the second time
Storage configuration；And
Step S3: the JESD204B interface module of FPGA programmable logic device is resetted, to ADC chip, DAC chip
Register carries out parameter configuration, and starting Simultaneous Monitoring program.
It is disclosed by the invention a kind of based on JESD204B interface high-speed figure receive-transmit system power on configuration method, standardize height
Speed digital receive-transmit system power on configuration process avoids the occurrence of clock and hits edge, the feelings that system electrification is asynchronous or link is unstable
Condition, while Simultaneous Monitoring program is added, it avoids since the foundation of JESD204B interface link unsuccessfully leads to system crash, to make
The system of obtaining has very high stability, anti-interference, reliability and environmental suitability.
It is illustrated combined with specific embodiments below
As shown in Figure 1, high speed digital transmitting and receiving system of the present invention includes FPGA programmable logic device, ADC chip, DAC core
Piece, LMK04828_AD clock chip, LMK04828_DA clock chip and clock distribute chip.
FPGA programmable logic device (i.e. fpga chip in Fig. 1) includes JESD204B interface module, ADC Simultaneous Monitoring mould
Block, ADC register configuration module, system reset module, DAC register configuration module, LMK04828 configuration generation module and
LMK04828 register configuration module, wherein system reset module by JESD204B interface module respectively with ADC chip and
DAC chip electrical connection, ADC Simultaneous Monitoring module are electrically connected by JESD204B interface module with ADC chip, system reset module
It is electrically connected by ADC register configuration module with ADC chip, system reset module passes through DAC register configuration module and DAC core
Piece electrical connection, generation module is also configured with ADC Simultaneous Monitoring module LMK04828 for system reset module and LMK04828 is deposited
Device configuration module is electrically connected, and LMK04828 configuration generation module is electrically connected with LMK04828 register configuration module,
LMK04828 register configuration module is mutual by PCB trace with LMK04828_AD clock chip and LMK04828_DA clock chip
Connection；FPGA programmable logic device is connect with host computer by optical fiber；LMK04828_AD clock chip is electrically connected with ADC chip；
LMK04828_DA clock chip is electrically connected with DAC chip；Clock distribute chip and LMK04828_AD clock chip and
The electrical connection of LMK04828_DA clock chip；And signal is derived from host computer and clock distribution chip electrical connection.
In the embodiment of the present invention, FPGA programmable logic device is connect with host computer by optical fiber；FPGA programmable logic device
It is interconnected using JESD204B interface by PCB trace with ADC chip, DAC chip；FPGA programmable logic device and two panels
LMK04828 chip is interconnected by PCB trace；ADC chip, DAC chip and LMK04828 chip are interconnected by PCB trace；Signal
Source is connected by SSMA interface in digital transmitting and receiving system with coaxial wire with clock distribution chip.
It should be noted that can high-speed figure receive-transmit system establish stable link, the configuration of system is depended not only on
Sequentially, it is more dependent upon the foundation of JESD204B interface synchronization link.If JESD204B interface synchronization closes between ADC chip and FPGA
System establishes failure, then link paralysis is directly resulted in, thus based on JESD204B interface high-speed figure receive-transmit system in the present invention
It joined ADC Simultaneous Monitoring function in electric configuration method, to ensure that ADC link works normally.
Specifically, Simultaneous Monitoring function is for during monitoring fpga chip and ADC chip JESD204B interface link setup
Rx_sync signal, under normal circumstances, after link is stablized, rx_sync signal can be stablized in high level, if link is unstable
Or link setup is unsuccessful, rx_sync signal will appear intermittent drag down or for a long time be low level situation.Simultaneous Monitoring program
The failing edge of main monitoring rx_sync signal is continuously the low level time, once detect that rx_sync signal occurs 3
The low level of secondary failing edge or continuous 500us or more time are then judged as that link establishment is unsuccessful, then activation system resets letter
Number, link is re-established, while FPGA can export the number that restarting resets, is used for malfunction monitoring.
As shown in Fig. 2, it is of the invention based on JESD204B interface high-speed figure receive-transmit system power on configuration method include it is more
A step:
1) system electrification, ADC chip, DAC chip and LMK04828 clock chip hardware reset；
2) LMK04828 clock chip first time register configuration, sends SYNC synchronization signal and second of register is matched
It sets；
3) JESD204B interface module resets in fpga chip, ADC chip, the configuration of DAC chip register parameters, and starting is same
Walk monitoring program.
It should be noted that LMK04828 clock chip includes LMK04828_AD clock chip and LMK04828_ in the present invention
DA clock chip.
As shown in figure 3, being illustrated below with reference to specific timing diagram
Complete power on configuration process:
(1) system electrification, ADC chip, DAC chip and LMK04828 clock chip hardware reset.
Firstly, carrying out system connection, system electrification is completed.By external stabilization signal source or locking phase module input 100M,
The homologous clock of 200M and 400M, wherein 200M is inputted as the clock of LMK04828_AD clock chip, 400M conduct
The clock of LMK04828_DA clock chip inputs, and 100M clock can enter the PLL (phaselocked loop) inside FPGA.
Frequency dividing locking phase is carried out to 100M by fpga chip, wherein the frequency-dividing clock of 10M as ADC chip, DAC chip and
The reset of LMK04828 clock chip and configurable clock generator, clock lock have locking instruction (locked), letter to be instructed later
It number draws high, starts reset count, terminate the hardware reset of two panels LMK04828 chip and DAC chip, i.e. LMKAD_ after 2s
The signal of Rst, LMKDA_Rst and SLEEP_DAC1~4 is lower by height, and the reset of ADC chip uses the suggestion side of chip handbook
Formula is resetted using impulse form, i.e., ADC1~2_Rst signal is lower again by low get higher, and terminates journey inside FPGA after 3s
The software reset of sequence, i.e. RESET_in signal are lower by height.
(2) LMK04828 clock chip first time register configuration, SYNC synchronization signal is sent and second of register
Configuration.
Start LMK04828 first time register configuration, i.e. LMK_ while terminating FPGA internal processes software reset
1st_config is lower by height, is completed in LMK04828 first time register configuration, i.e., LMK_1st_config_done signal is drawn
After height, LMK04828 exports DCLK (sampling clock) at this time, waits host computer to send optical synchronous signal, is receiving first light
16ms starts LMKAD_SYNC and LMKDA_SYNC synchronization pulse after synchronous rising edge, as LMK04828 clock
The synchronization reset signal of chip, 20us starts second of configuration signal of LMK04828 chip after LMKDA_SYNC, i.e.,
LMK_2nd_config is lower by height, and LMK04828 exports SCLK (reference clock) at this time.
(3) fpga chip JESD204B module resets, ADC chip, the configuration of DAC chip register parameters, starting is same later
Walk monitoring program.
Completion is configured for the second time in LMK04828 clock chip, i.e. LMK_2nd_config_done signal takes after drawing high
The software reset of the ADC chip register that disappears configuration and the software reset of JESD204B Interface IP Core finally cancel DAC chip and post
The software reset of storage configuration, the JESD204B interface between subsequent ADC and FPGA can complete link setup process, while FPGA also can
Into Simultaneous Monitoring state, once rx_sync breaks down, Simultaneous Monitoring program will be started, activation system resets, and system will
It can be re-executed again from (1).
Used herein a specific example illustrates the principle and implementation of the invention, and above embodiments are said
It is bright to be merely used to help understand method and its core concept of the invention.It should be pointed out that for the ordinary skill of the art
, without departing from the principle of the present invention, can be with several improvements and modifications are made to the present invention for personnel, these improvement
It is also fallen within the protection scope of the claims of the present invention with modification.
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair
The restriction of embodiments of the present invention may be used also on the basis of the above description for those of ordinary skill in the art
To make other variations or changes in different ways, all embodiments can not be exhaustive here, it is all to belong to this hair
The obvious changes or variations that bright technical solution is extended out are still in the scope of protection of the present invention.
Claims (8)
1. one kind is based on JESD204B interface high-speed figure receive-transmit system power on configuration method, which is characterized in that the high speed number
Word receive-transmit system includes FPGA programmable logic device, ADC chip, DAC chip, LMK04828_AD clock chip, LMK04828_
DA clock chip and clock distribute chip；Wherein the FPGA programmable logic device includes JESD204B interface module, ADC synchronization
Monitoring modular, ADC register configuration module, system reset module, DAC register configuration module, LMK04828 configuration generate mould
Block and LMK04828 register configuration module, wherein the system reset module passes through the JESD204B interface module point
It is not electrically connected with the ADC chip and the DAC chip, the ADC Simultaneous Monitoring module passes through the JESD204B interface mould
Block is electrically connected with the ADC chip, and the system reset module passes through the ADC register configuration module and the ADC chip
Electrical connection, the system reset module are electrically connected by the DAC register configuration module with the DAC chip, the system
Reseting module also configures generation module and the LMK04828 register with LMK04828 described in the ADC Simultaneous Monitoring module
Configuration module is electrically connected, and the LMK04828 configuration generation module is electrically connected with the LMK04828 register configuration module
It connects, the LMK04828 register configuration module and the LMK04828_AD clock chip and the LMK04828_DA clock core
Piece is interconnected by PCB trace；The FPGA programmable logic device is connect with host computer by optical fiber；When the LMK04828_AD
Clock chip is electrically connected with the ADC chip；The LMK04828_DA clock chip is electrically connected with the DAC chip；The clock
Distribution chip is electrically connected with the LMK04828_AD clock chip and the LMK04828_DA clock chip；And the signal source
In the host computer and clock distribution chip electrical connection；
The high-speed figure receive-transmit system power on configuration method includes:
Step S1: it connects the high-speed figure receive-transmit system and powers on, to the ADC chip, the DAC chip, LMK04828_
AD clock chip and the LMK04828_DA clock chip carry out hardware reset；
Step S2: first time register is carried out to the LMK04828_AD clock chip and the LMK04828_DA clock chip
Configuration, send SYNC synchronization signal and to the LMK04828_AD clock chip and the LMK04828_DA clock chip into
Second of register configuration of row；And
Step S3: the JESD204B interface module of the FPGA programmable logic device is resetted, to the ADC core
Piece, the DAC chip register carry out parameter configuration, and starting Simultaneous Monitoring program.
2. power on configuration method according to claim 1, which is characterized in that the step S1 is specifically included:
Step S101: the signal source inputs the homologous clock of 100M, the homologous clock of 200M and the homologous clock of 400M, and wherein 200M is same
Source clock is that the clock of the LMK04828_AD clock chip inputs, when the homologous clock of 400M is the LMK04828_DA
The clock of clock chip inputs, and the homologous clock of 100M enters the phaselocked loop of the FPGA programmable logic device；
Step S102: the FPGA programmable logic device carries out frequency dividing locking phase to the homologous clock of the 100M, wherein the frequency dividing of 10M
Clock is as the ADC chip, the DAC chip, the LMK04828_AD clock chip and the LMK04828_DA clock
The reset of chip and configurable clock generator；
Step S103: carrying out locking instruction after clock lock, when locking signal is high level, starts reset count, first is pre-
If terminating the hard of the DAC chip, the LMK04828_AD clock chip and the LMK04828_DA clock chip after the time
Part resets；
Step S104: the ADC chip is resetted using impulse form；And
Step S105: terminate the software reset of the FPGA programmable logic device internal processes after the second preset time.
3. power on configuration method according to claim 2, which is characterized in that first preset time is 2 seconds.
4. power on configuration method according to claim 2, which is characterized in that second preset time is 3 seconds.
5. power on configuration method according to claim 2, which is characterized in that the step S2 is specifically included:
Step S201: when the FPGA programmable logic device internal processes terminate software reset, to the LMK04828_AD clock
Chip and the LMK04828_DA clock chip carry out first time register configuration；
Step S202: the LMK04828_AD clock chip and the LMK04828_DA clock chip export sampling clock；
Step S203: receiving host computer and send after optical synchronous signal after third preset time, the LMK04828_AD clock chip
Starting LMKAD_SYNC synchronization pulse, the LMK04828_DA clock chip starts LMKDA_SYNC synchronization pulse,
The LMKAD_SYNC synchronization pulse is the synchronization reset signal of the LMK04828_AD clock chip, the LMKDA_
SYNC synchronization pulse is the synchronization reset signal of the LMK04828_DA clock chip；
Step S204: after the 4th preset time after starting the LMKDA_SYNC synchronization pulse, to the LMK04828_
AD clock chip and the LMK04828_DA clock chip carry out second of register configuration；And
Step S205: the LMK04828_AD clock chip and the LMK04828_DA clock chip export reference clock.
6. power on configuration method according to claim 5, which is characterized in that the third preset time is 16 milliseconds.
7. power on configuration method according to claim 5, which is characterized in that the 4th preset time is 20 microseconds.
8. power on configuration method according to claim 1, which is characterized in that the step S3 is specifically included:
Step S301: second is carried out to the LMK04828_AD clock chip and the LMK04828_DA clock chip and is deposited
Device cancels the software reset of the ADC register configuration module and the JESD204B interface module with postponing；
Step S302: cancel the software reset of the DAC register configuration module；
Step S303: the JESD204B interface module carries out link setup；
Step S304: the FPGA programmable logic device enters synchronous detecting state；And
Step S305: when there is synchronous failure, then start Simultaneous Monitoring program, activation system resets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910308325.9A CN110032262B (en) | 2019-04-17 | 2019-04-17 | High-speed digital transceiver system power-on configuration method based on JESD204B interface |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910308325.9A CN110032262B (en) | 2019-04-17 | 2019-04-17 | High-speed digital transceiver system power-on configuration method based on JESD204B interface |
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| Publication Number | Publication Date |
|---|---|
| CN110032262A true CN110032262A (en) | 2019-07-19 |
| CN110032262B CN110032262B (en) | 2020-09-18 |
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| CN117194132B (en) * | 2023-11-06 | 2024-02-02 | 成都芯盟微科技有限公司 | JESD204B link establishment reliability pressure test method and system |
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