CN110021677A - 光学电压源 - Google Patents

光学电压源 Download PDF

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CN110021677A
CN110021677A CN201811530916.2A CN201811530916A CN110021677A CN 110021677 A CN110021677 A CN 110021677A CN 201811530916 A CN201811530916 A CN 201811530916A CN 110021677 A CN110021677 A CN 110021677A
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semiconductor diode
voltage source
output equipment
optical voltage
coupling output
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CN110021677B (zh
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G·凯勒
D·富尔曼
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Azur Space Solar Power GmbH
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Abstract

本发明涉及一种光学电压源和一种耦合输出设备,该光学电压源具有数量N个彼此串联连接的半导体二极管(D1,DN),该半导体二极管分别具有pn结,半导体二极管(D1,D2,DN)一起单片地集成并且共同构成第一堆叠(ST1),该第一堆叠具有上侧和下侧,并且该第一堆叠(ST1)的半导体二极管的数量N大于等于2,所述耦合输出设备具有另外的半导体二极管(Dpin),所述另外的半导体二极管具有pin结,所述另外的半导体二极管与第一堆叠的半导体二极管反向串联连接,另外的半导体二极管的下侧与所述第一堆叠的上侧材料锁合地连接,并且所述另外的半导体二极管与所述第一堆叠一起构成总堆叠(STG)。

Description

光学电压源
技术领域
本发明涉及一种光学电压源。
背景技术
为了在例如由于高压或爆炸危险导致的暴露周围环境中给传感器供电,已知的是:光学地传输能量并且例如借助光伏转换器转换成电能。为此,需要具有尽可能高的输出电压的光学电压源——例如由EP 2 983 213 A1所已知的那样的高压二极管。
由Arthur Christoph Poloczek的博士论文《Gestapelte PIN-Dioden undResonanztunneldioden in optoelektronischenhoherFunktionsdichte》(2011年第一版)公开一种具有高功能密度的光电接收器电路。
发明内容
在所述背景下,本发明的任务在于说明一种扩展现有技术的设备。
所述任务通过根据本发明的技术方案的一种光学电压源来解决。在说明书中描述了本发明的有利构型。
根据本发明的主题,提供一种光学电压源以及一种耦合输出设备。
所述光学电压源具有数量N个彼此串联连接的半导体二极管,这些半导体二极管分别具有pn结,其中,这些半导体二极管一起单片地集成并且共同构成具有上侧和下侧的第一堆叠。
第一堆叠的半导体二极管的数量N大于等于2。
耦合输出设备具有一个另外的半导体二极管,其中,所述另外的半导体二极管包括pin结。
所述另外的半导体二极管与第一堆叠的半导体二极管反向串联连接,其中,所述另外的半导体二极管的下侧与第一堆叠的上侧材料锁合地连接,并且所述另外的半导体二极管与第一堆叠一起构成共同的总堆叠。
应说明,第一堆叠的二极管一起构成所谓的多结光电二极管或高压二极管并且代表光学电压源。
因此,提供了一种光学的、电隔离的能量供给。第一堆叠的半导体二极管和/或所述另外的半导体二极管优选由III-V族半导体构成——特别优选由GaAs构成。
尤其III-V族半导体(例如GaAs)将具有合适波长的光非常高效地转换成电能。
所述另外的二极管也被称为PIN二极管或称为快速光电二极管。应说明,所述另外的二极管由多个堆叠状的半导体层构成并且构成第二堆叠。优选地,第一堆叠ST1和第二堆叠ST2单片地集成。
通过所述另外的二极管与第一堆叠的半导体二极管的反向串联连接,借助第一堆叠的或光学电压源的源电压将所述另外的二极管在截止方向上或反向上偏置。
借助反向偏置电压(即反向偏置),使所述另外的半导体二极管的电容最小化,从而与第一堆叠或光学电压源相比,所述另外的二极管在工作点中具有特别低的电容。由此,能够实现光电二极管的快速数据传输或快速切换。
为了进行传输,将数据信号调制成用于功率传输的光学信号。替代地,借助特定波长来传输数据信号,其中,用于数据传输的特定波长与所有用于功率传输的波长不同。
因此,根据本发明将高压二极管作为高效的和电隔离的能量供给与用于(例如控制信号的)数据传输的快速功率二极管进行组合。
因此,根据本发明的这种组合的一个优点是:除了电隔离的功率传输以外,总设备还能够实现快速的数据传输。
在一种替代的实施方式中,所述另外的半导体二极管在垂直于第一堆叠的上侧的投影中覆盖第一堆叠的上侧的至多50%或至多30%或至多10%。
在一种扩展方案中,所述另外的半导体二极管具有至多10pF的电容。在此,电容值与运行电压相关。优选地,运行电压处于1伏至10伏的范围内——最优选2伏至5伏的范围内。
根据另一扩展方案,所述半导体二极管和所述另外的半导体二极管一起单片地集成。
在另一实施方式中,第一接通部(例如作为接通面)布置在第一堆叠的上侧上并且具有相对于所述另外的二极管的间距。优选地,第一接通部与所述另外的半导体二极管的阴极并且与邻接第一堆叠的上侧的半导体二极管的阴极能够导电地连接。
根据另一实施方式,第二接通部(例如作为接通面)布置在所述另外的二极管的上侧上。
在另一实施方式中,第三接通部(例如接通面)布置在第一堆叠的下侧上,或者,第一堆叠的下侧与载体衬底的上侧材料锁合地连接,并且第三接通部(例如接通面)布置在载体衬底的下侧上。
根据一种扩展方案,总堆叠包括载体衬底,其中,第一堆叠的下侧与载体衬底的上侧或者与完全覆盖载体衬底的上侧的能够导电的中间层材料锁合地连接。
优选地,载体衬底在垂直于第一堆叠的上侧的投影中构成围绕第一堆叠的环绕的边沿。换言之,通过该环绕的边沿构成带有台阶面的台阶。在另一扩展方案中,第三接通面布置在载体衬底的环绕的边沿上或台阶面上。
优选地,在载体衬底的下侧上构造有整面的接通层作为第三接通面。在一种扩展方案中,第三接通面与邻接第一堆叠的下侧的半导体二极管的阳极能够导电地连接。
在另一扩展方案中,在第一部分堆叠的分别两个彼此相继的半导体二极管之间构造有隧道二极管。
在一种实施方式中,第一堆叠(ST1)的至少两个半导体二极管(D1,D2,DN)具有相同的半导体层序列,其中,这两个半导体二极管(D1,D2,DN)的相应的彼此对应的层具有相同的化学计量。
在一种扩展方案中,所述另外的半导体二极管(Dpin)具有堆叠状布置的半导体层序列,其中,所述序列与所述第一堆叠的半导体二极管(D1,D2,DN)中的一个的半导体层序列相同或不相同。优选地,在相同的情况下,这两个半导体二极管(D1,D2,DN,DPIN)的分别彼此对应的层具有相同的化学计量。
在一种扩展方案中,所述另外的二极管具有高于250kHz的截止频率。优选地,该截止频率处于1MHz至1GHz之间的范围内,最优选地,该截止频率处于2MHz至100MHz的范围内。
附图说明
以下参照附图更详细地描述本发明。在此,相同类型的部分标注有相同的附图标记。所示出的实施方式是高度示意性的,也就是说,距离以及横向和纵向的延伸不是成比例的,并且只要未特别说明,则彼此也不具有可推导的几何关系。在此示出:
图1示出光学电压源和耦合输出设备的根据本发明的第一实施方式的电路图;
图2示出图1的电压源和耦合输出设备的根据本发明的第一实施方式的示意性剖视图;
图3示出图2的实施方式的示意性俯视图。
具体实施方式
图1的图像示意性示出光学电压源和耦合输出设备的第一实施方式的电路图。
光学电压源包括数量N个彼此串联连接的半导体二极管D1、D2至DN。半导体二极管D1、D2和DN构成第一堆叠ST1。在第一堆叠ST1上布置有第二堆叠ST2。第二堆叠ST2包括一个另外的半导体二极管DPIN。优选地,第一堆叠ST1和第二堆叠ST2单片地集成。
耦合输出设备包括所述另外的半导体二极管DPIN和RC环节,所述RC环节由电阻RD和电容器C构成并且用于截取数据信号Vdata。所述另外的半导体二极管DPIN通过第一电接通部K1相对于半导体二极管D1、D2至DN反向串联地连接,也就是说,所述另外的半导体二极管的阴极以及第一堆叠ST1的最上部的半导体二极管D1的阴极与第一接通点K1能够导电地连接。
第一堆叠ST1的最下部的半导体二极管DN的阳极与第三电接通部K3能够导电地连接。所述另外的半导体二极管Dpin的阳极通过第二电接通部K2和电阻RD与第三接通部K3能够导电地连接,由此,所述另外的半导体二极管Dpin通过光学电压源的源电压Vsup在截止方向上被偏置。
通过电容器C,在第二接通部K2上相对于第三接通部K3截取数据信号Vdata。
在图2的图像中示出作为集成构件的、光学电压源与耦合输出设备的一部分的第一实施方式。图3的图像示出根据图2的实施方式的集成构件的俯视图。以下仅阐述与图1的图像的区别。
N个彼此串联连接的半导体二极管D1、D2至DN构成第一堆叠ST1。在第一堆叠ST1的上侧上彼此间隔开地布置有另外的二极管Dpin以及作为接通部K1的接通面。所述另外的二极管Dpin以下侧与第一堆叠ST1的上侧材料锁合地连接并且与第一堆叠ST1一起构成总堆叠STG。在所述另外的二极管Dpin的上侧上布置有第二接通面K2。
第一堆叠ST1的下侧与载体衬底SUB的上侧材料锁合地连接,所述载体衬底作为总堆叠STG的另外的层,其中,载体衬底SUB在垂直于第一堆叠的上侧的投影中构成围绕第一堆叠ST1的环绕的边沿UR。能够导电的涂层作为第三接通部K3覆盖载体衬底SUB的下侧。
根据所述实施方式,图1中的其他部件(例如RC环节)在外部实现。

Claims (18)

1.一种光学电压源以及耦合输出设备,其中,
所述光学电压源具有数量N个彼此串联连接的半导体二极管(D1,DN),所述半导体二极管分别具有pn结,
所述半导体二极管(D1,D2,DN)一起单片地集成并且共同构成第一堆叠(ST1),所述第一堆叠具有上侧和下侧,
所述第一堆叠(ST1)的半导体二极管(D1,D2,DN)的数量N大于等于2,
其特征在于,
所述耦合输出设备具有第二堆叠(ST2),所述第二堆叠具有一个另外的半导体二极管(Dpin),
所述另外的半导体二极管(Dpin)具有pin结,
所述另外的半导体二极管(Dpin)与所述第一堆叠(ST1)的半导体二极管(D1,D2,DN)反向串联地连接,
所述另外的半导体二极管(Dpin)的下侧与所述第一堆叠(ST1)的上侧材料锁合地连接,
具有所述另外的半导体二极管(Dpin)的所述第二堆叠(ST2)与所述第一堆叠(ST1)一起构成总堆叠(STG)。
2.根据权利要求1所述的光学电压源以及耦合输出设备,其特征在于,所述另外的半导体二极管(Dpin)在垂直于所述第一堆叠(ST1)的上侧的投影中覆盖所述第一堆叠(ST1)的上侧的至多50%或至多30%或至多10%。
3.根据权利要求1或2所述的光学电压源以及耦合输出设备,其特征在于,所述另外的半导体二极管(Dpin)具有至多10pF的电容。
4.根据权利要求1至3中任一项所述的光学电压源以及耦合输出设备,其特征在于,所述半导体二极管(D1,D2,DN)和所述另外的半导体二极管(Dpin)一起单片地集成。
5.根据权利要求1至4中任一项所述的光学电压源以及耦合输出设备,其特征在于,第一电接通部(K1)布置在所述第一堆叠(ST1)的上侧上并且具有相对于所述另外的二极管(Dpin)的间距。
6.根据权利要求5所述的光学电压源以及耦合输出设备,其特征在于,所述第一电接通部(K1)与所述另外的半导体二极管(Dpin)的阴极并且与邻接所述第一堆叠(ST1)的上侧的半导体二极管(D1)的阴极能够导电地连接。
7.根据权利要求1至6中任一项所述的光学电压源以及耦合输出设备,其特征在于,在所述另外的半导体二极管(Dpin)的上侧上布置有第二接通部(K2)。
8.根据权利要求1至7中任一项所述的光学电压源以及耦合输出设备,其特征在于,在所述第一堆叠(ST1)的下侧上布置有第三接通面(K3),或者,所述第一堆叠(ST1)的下侧与载体衬底(SUB)的上侧材料锁合地连接,并且第三接通部(K3)布置在所述载体衬底(SUB)的下侧上。
9.根据权利要求1至8中任一项所述的光学电压源以及耦合输出设备,其特征在于,所述总堆叠(STG)包括载体衬底(SUB),其中,所述第一堆叠(ST1)的下侧与所述载体衬底(SUB)的上侧或者与完全覆盖所述载体衬底(SUB)的上侧的能够导电的中间层材料锁合地连接。
10.根据权利要求9所述的光学电压源以及耦合输出设备,其特征在于,所述载体衬底(SUB)在垂直于所述第一堆叠(ST1)的上侧的投影中构成围绕所述第一堆叠(ST1)的环绕的边沿(UR)。
11.根据权利要求10所述的光学电压源以及耦合输出设备,其特征在于,第三接通面布置在所述载体衬底(SUB)的环绕的边沿(UR)上。
12.根据权利要求8或11所述的光学电压源以及耦合输出设备,其特征在于,所述第三接通部(K3)与邻接所述第一堆叠(ST1)的下侧的半导体二极管(DN)的阳极能够导电地连接。
13.根据权利要求1至12中任一项所述的光学电压源以及耦合输出设备,其特征在于,所述第一堆叠(ST1)的半导体二极管(D1,D2,DN)和/或所述另外的半导体二极管(Dpin)包括III-V族半导体材料或者由III-V族半导体材料构成。
14.根据权利要求13所述的光学电压源以及耦合输出设备,其特征在于,所述III-V族半导体材料是GaAs。
15.根据权利要求1至14中任一项所述的光学电压源以及耦合输出设备,其特征在于,在所述第一堆叠(ST1)的分别两个彼此相继的半导体二极管(D1,D2,DN)之间构造有隧道二极管。
16.根据权利要求1至15中任一项所述的光学电压源以及耦合输出设备,其特征在于,所述第一堆叠(ST1)的至少两个半导体二极管(D1,D2,DN)具有相同的半导体层序列,其中,这两个半导体二极管(D1,D2,DN)的相应的彼此对应的层具有相同的化学计量。
17.根据权利要求1至16中任一项所述的光学电压源以及耦合输出设备,其特征在于,所述另外的半导体二极管(Dpin)具有堆叠状布置的半导体层序列,并且所述序列与所述第一堆叠的半导体二极管(D1,D2,DN)中的一个的半导体层序列相同或不相同。
18.根据权利要求1至17中任一项所述的光学电压源以及耦合输出设备,其特征在于,所述另外的半导体二极管(Dpin)具有高于250kHz的截止频率。
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