CN110007635B - Analog-digital signal hybrid synchronous acquisition system - Google Patents
Analog-digital signal hybrid synchronous acquisition system Download PDFInfo
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Abstract
The invention discloses an analog-digital signal hybrid synchronous acquisition system, and relates to the technical field of signal acquisition and processing devices. The acquisition system comprises a signal acquisition adapter, a digital signal playback adapter, a plurality of digital signal environment analog cards, an analog signal acquisition card, a digital signal storage playback card, a bus module, a controller, a man-machine interaction module and a power module, wherein one digital signal environment analog card is used as a master card, the rest digital signal environment analog cards are used as slave cards, the controller provides clock signals for the digital signal environment analog cards used as the master cards, and the digital signal environment analog cards used as the master cards provide synchronous clock signals for the digital signal environment analog cards used as the slave cards and the analog signal acquisition cards. The same clock module is arranged on different acquisition cards, one of the acquisition cards is used as a master card, the other acquisition cards are used as slave cards, and the master card and the slave cards are used for keeping time base synchronization among the boards through a synchronous clock sharing link.
Description
Technical Field
The invention relates to the technical field of signal acquisition and processing devices, in particular to an analog-digital signal hybrid synchronous acquisition system.
Background
In the localization of some imported missile equipment electronic spare parts and other electronic equipment repair and background, signal input consistent with the environment of a mounting signal needs to be provided in the laboratory test process of electronic components, and the test process cannot influence the normal working state of equipment or cause the service life of the equipment to be reduced or even damaged. In order to solve the problem, key technologies of missile equipment electronic component signal environment simulation need to be researched, and software and hardware systems need to be developed.
At present, the general technical scheme is that a 'host and adapter' structure is adopted, but the system for constructing the existing board shelf products has the following problems: 1. the existing analog signal acquisition board card and digital signal acquisition board card can not share the same synchronous sampling clock, so that analog-digital mixed synchronous sampling of electronic components of the large complex weapon system is realized; 2. the built-in timing and synchronization functions of the PXIe platform are directly utilized to realize the synchronization between boards, software parameters are required to be modified again when boards are increased or reduced in the test system, and random expansion of a system sampling channel cannot be realized.
Disclosure of Invention
The invention aims to provide an analog-digital signal hybrid synchronous acquisition system which can realize clock synchronization and further realize accurate synchronization among all acquisition cards.
In order to solve the technical problems, the invention adopts the following technical scheme: the analog-digital signal hybrid synchronous acquisition system is characterized in that: the system comprises a signal acquisition adapter, a digital signal playback adapter, a plurality of digital signal environment analog cards, an analog signal acquisition card, a digital signal storage playback card, a bus module, a controller, a man-machine interaction module and a power module, wherein a signal input end of the signal acquisition adapter receives signals sent by an equipment system, a signal output end of the signal acquisition adapter is respectively connected with the digital signal environment analog cards and the signal input end of the analog signal acquisition card, the digital signal environment analog cards and the analog signal acquisition card are in bidirectional connection with the controller through the bus module, the digital signal storage playback card is in bidirectional connection with the controller through the bus module, a signal output end of the digital signal storage playback card is connected with the signal input end of the digital signal playback adapter, an output end of the digital signal playback adapter is a signal output end of the system, and the digital signal environment analog cards, the analog signal acquisition cards and the digital signal storage playback card are controlled by the controller and are used for processing data under the control of the controller, and the power module is used for providing power supply for the power supply module which needs to be connected with the power supply input end in the analog system; the man-machine interaction module is connected with the controller in a two-way and is used for inputting control commands and displaying output data; one digital signal environment analog card is used as a master card, the other digital signal environment analog cards are used as slave cards, the controller provides clock signals for the digital signal environment analog card used as the master card, and the digital signal environment analog card used as the master card provides synchronous clock signals for the digital signal environment analog card used as the slave card and the analog signal acquisition card.
The further technical proposal is that: the digital signal environment simulation card comprises a first external interface module, a level conversion module, a first control unit, a first storage unit, a first clock unit, a first power supply unit and a first bus unit, wherein the first external interface module is in bidirectional connection with the level conversion module, and the first external interface module is used for being connected with peripheral equipment; the level conversion module is in bidirectional connection with the first control unit and is used for realizing level conversion; the first storage unit is connected with the first control unit in a bidirectional way and is used for storing data; the first clock unit is used for providing a working clock for the first control unit; the first power supply unit is connected with a power supply input end of a module needing power supply in the digital signal environment simulation card and is used for providing working power supply for the module needing power supply; the first bus unit is connected with the first control unit in a bidirectional way and is used for carrying out data exchange with the controller in the bidirectional way.
The further technical proposal is that: the analog signal acquisition card comprises a second external interface module, an AD acquisition circuit, a second control unit, a second storage unit, a second clock unit, a second power supply unit and a second bus unit, wherein the signal output end of the second external interface module is connected with the signal input end of the AD acquisition circuit, and the first external interface module is used for being connected with peripheral equipment; the AD acquisition circuit is in bidirectional connection with the second control unit and is used for analog-to-digital conversion; the second storage unit is connected with the second control unit in a bidirectional way and is used for storing data; the second clock unit is used for providing a working clock for the second control unit and the AD acquisition circuit; the second power supply unit is connected with a power supply input end of a module needing power supply in the analog signal acquisition card and is used for providing working power supply for the module needing power supply; the second bus unit is connected with the second control unit in a bidirectional way and is used for carrying out data exchange with the controller in the bidirectional way.
The further technical proposal is that: the first clock unit comprises a first system synchronous clock module and a first controller clock distribution module, and the system synchronous clock module comprises a SIT9102 crystal oscillator chip U53, and a DC blocking filter and an impedance matching circuit at the periphery of the crystal oscillator chip U53.
The further technical proposal is that: the first clock unit comprises an analog signal acquisition card clock distribution module, the clock distribution module comprises a CY2305SC type clock buffer U7, a pin 1 of the U7 is connected with a relevant output end of the second controller through a resistor R56, a pin 2, a pin 3, a pin 5 and a pin 7 of the U7 are respectively clock signal output ends of the clock distribution module, a pin 4 of the U7 is grounded, a pin 6 of the U7 is divided into three paths, the first path is grounded through a capacitor C339, the second path is grounded through a capacitor C338, the third path is connected with a 3.3V power supply through an inductor L6, and a pin 8 of the U7 is suspended.
The further technical proposal is that: the first clock unit and the second clock unit further comprise a memory synchronous clock module and a memory clock distribution module.
The further technical proposal is that: the memory synchronous clock module comprises a CDCLVP1102RGT type clock buffer chip U51, 1 pin, 16 pin and 17 pin of the U51 are grounded, 2-4 pin and 13-15 pin of the U51 are suspended, 9-12 pin of the U51 is a clock signal output end, 3.3V power supply is connected with 5 pin of the U51 after passing through an inductor B2, a filter capacitor C321, a capacitor C252 and a capacitor C264 are connected in parallel with the input end of the 3.3V power supply, 8 pin of the U51 is grounded through a capacitor C322 and a capacitor C323 respectively, 1 pin of a SIT9102 crystal oscillator chip U52 is connected with 3.3V power supply, 2 pin of the U52 is suspended, 3 pin of the U52 is grounded, 4 pin and 5 pin of the U52 are respectively connected with 6 pin and 7 pin of the U51 after passing through a capacitor C326 and a capacitor C327, one end of a resistor R is connected with 4 pin of the U52, and the other end of the resistor R465 is connected with 5 pin of the U52.
The beneficial effects of adopting above-mentioned technical scheme to produce lie in: the system comprises an analog signal acquisition card and a digital signal environment analog card based on a CPCIe bus, and a synchronous clock sharing link is added on the basis of the CPCIe. The same clock module is arranged on different acquisition cards, one of the acquisition cards is used as a master card, the other acquisition cards are used as slave cards, and the master card and the slave cards are used for keeping time base synchronization among the boards through a synchronous clock sharing link. Under the condition of sharing synchronous time base, DDR3 is utilized to store digital signals which can be obtained by synchronously caching the front-end circuits of the digital card and the analog card, and the digital signals are rapidly transmitted to a storage module of the main control computer in a RocketIO GTX mode through a CPCIe bus.
The developed acquisition card is used as an important component of a missile equipment electronic component signal environment simulation system and is arranged in an NI PXIe-1075 type PXIe chassis, the NI PXIe-8840 type main control computer is used for controlling, and the chassis and the main control computer are compatible with a CPCIe bus protocol. The system main control computer is connected with other board cards through a backboard in the case, and the self-grinding digital signal environment simulation card and the simulation signal acquisition card which are installed in the case are all CPCIe buses, so that the system main control computer has more reliable and stable mechanical performance compared with PXIe. Through taking the first board card outside the 0 groove of the case as a master card, other board cards are taken as slave cards, clock synchronization signals of the master card are borrowed, and accurate synchronization between all the acquisition cards is realized.
Drawings
The invention will be described in further detail with reference to the drawings and the detailed description.
FIG. 1 is a schematic block diagram of a system according to an embodiment of the present invention;
FIG. 2 is a schematic block diagram of a digital signal environment simulation card in a system according to an embodiment of the present invention;
FIG. 3 is a schematic block diagram of an analog signal acquisition card in a system according to an embodiment of the invention;
FIG. 4 is a diagram of a trigger bus and acquisition clock configuration in a system according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a system synchronous clock module in a digital signal environment analog card according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a clock distribution module in a digital signal environment analog card according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a clock distribution module in an analog signal acquisition card according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a synchronous clock module of a memory module according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of clock distribution of a memory module according to an embodiment of the present invention;
FIG. 10 is a data flow control diagram of a system according to an embodiment of the present invention;
FIG. 11 is a schematic circuit diagram of a GTX high-speed transmission in a system according to an embodiment of the invention;
FIG. 12 is a schematic diagram of a GTX bus transmission connection in a system according to an embodiment of the invention;
fig. 13 is a schematic diagram of CPCIe bus data transmission in the system according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.
As shown in fig. 1, the embodiment of the invention discloses an analog digital signal hybrid synchronous acquisition system, which comprises a signal acquisition adapter, a digital signal playback adapter, a plurality of digital signal environment analog cards, an analog signal acquisition card, a digital signal storage playback card, a bus module, a controller, a man-machine interaction module and a power supply module, wherein the signal input end of the signal acquisition adapter receives signals sent by an equipment system, the signal output end of the signal acquisition adapter is respectively connected with the signal input ends of the digital signal environment analog cards and the analog signal acquisition card, the digital signal environment analog cards and the analog signal acquisition card are in bidirectional connection with the controller through the bus module, the signal output end of the digital signal storage playback card is connected with the signal input end of the digital signal playback adapter, the output end of the digital signal playback adapter is the signal output end of the system, the digital signal environment analog card, the analog signal acquisition card and the digital signal storage playback card are controlled by the controller, the digital signal storage playback card is used for being connected with the power supply module in a power supply system through the bus module, and the power supply module is required to be connected with the power supply module in the power supply system under control; the man-machine interaction module is connected with the controller in a two-way and is used for inputting control commands and displaying output data; one digital signal environment analog card is used as a master card, the other digital signal environment analog cards are used as slave cards, the controller provides clock signals for the digital signal environment analog card used as the master card, and the digital signal environment analog card used as the master card provides synchronous clock signals for the digital signal environment analog card used as the slave card and the analog signal acquisition card.
The system comprises an analog signal acquisition card and a digital signal environment analog card based on a CPCIe bus, and a synchronous clock sharing link is added on the basis of the CPCIe. The same clock module is arranged on different acquisition cards, one of the acquisition cards is used as a master card, the other acquisition cards are used as slave cards, and the master card and the slave cards are used for keeping time base synchronization among the boards through a synchronous clock sharing link. Under the condition of sharing synchronous time base, DDR3 is utilized to store digital signals which can be obtained by synchronously caching the front-end circuits of the digital card and the analog card, and the digital signals are rapidly transmitted to a storage module of the main control computer in a RocketIO GTX mode through a CPCIe bus.
The developed acquisition card is used as an important component of a missile equipment electronic component signal environment simulation system and is arranged in an NI PXIe-1075 type PXIe chassis, the NI PXIe-8840 type main control computer is used for controlling, and the chassis and the main control computer are compatible with a CPCIe bus protocol. The system main control computer is connected with other board cards through a backboard in the case, and the self-grinding digital signal environment simulation card and the simulation signal acquisition card which are installed in the case are all CPCIe buses, so that the system main control computer has more reliable and stable mechanical performance compared with PXIe. Through taking the first board card outside the 0 groove of the case as a master card, other board cards are taken as slave cards, clock synchronization signals of the master card are borrowed, and accurate synchronization between all the acquisition cards is realized.
When the signal is acquired, the acquisition adapter is used for acquiring the signal after conditioning the signal of the equipment through a digital signal acquisition playback card and an analog signal acquisition card in the system. And during digital signal playback, the controller controls the signal playback adapter to perform signal playback.
The digital signal environment simulation card comprises a first external interface module, a level conversion module, a first control unit, a first storage unit, a first clock unit, a first power supply unit and a first bus unit, wherein the first external interface module is in bidirectional connection with the level conversion module, and the first external interface module is used for being connected with peripheral equipment; the level conversion module is in bidirectional connection with the first control unit and is used for realizing level conversion; the first storage unit is connected with the first control unit in a bidirectional way and is used for storing data; the first clock unit is used for providing a working clock for the first control unit; the first power supply unit is connected with a power supply input end of a module needing power supply in the digital signal environment simulation card and is used for providing working power supply for the module needing power supply; the first bus unit is connected with the first control unit in a bidirectional way and is used for carrying out data exchange with the controller in the bidirectional way.
Further, as shown in fig. 2, the digital signal environment analog card mainly completes the functions of collecting and playing back the digital quantity of the electronic component of the missile equipment, and in practical application, the number of collecting channels can be configured according to requirements, and after the configuration is completed, the input digital quantity can be collected. The signals transmitted to the upper computer can be subjected to waveform display, data analysis, processing and the like.
The digital signals passing through the DB78 plug enter a 74LVC1T45 level conversion chip to uniformly convert 5V or 3.3V signals into 3.3V signals which can be adapted by an XC7K325T-2FFG900C type FPGA. During playback, the 3.3V signal output by the FPGA can be converted into a 5V or 3.3V signal, and then sent out through the DB 78. The 74LVC1T45 is a single bit, bipolar power supply, bi-directional level shifter with tri-state output, and the direction control input (DIR) provided by the FPGA controls the input and output directions of the chip, so that 6 output levels of 1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5.0V can be provided between 1.2 and 5.5V. A maximum 420Mbps data conversion rate can be realized when 3.3V to 5.5V level conversion is carried out, and the chip has high noise immunity.
During each acquisition, digital signals passing through the level conversion chip enter the X1_FPGA_B1-X1_FPGA_B32 ports of the FPGA, are converted into parallel data through the FPGA, enter MT41J64M16 type DDR3 from the DDR 3_A_A1-DDR 3_A_A32 ports, and are temporarily stored in DDR3 memory particles, the DDR3 memory particle capacity of the model is 1GB, and the system adopts two DDR3 memory particles to expand the total cache capacity to 2GB. After the acquisition is finished, the data is transmitted to a main control computer based on a WINDOWS 7 system through a CPCIe bus of a PXIe plug and is stored on a high-capacity hard disk.
In the playback process, the digital signal environment analog card mainly completes the output function of digital quantity. The board card outputs the data pre-stored in the DDR3 memory module from the DDR 3_A_A1-DDR 3_A_A32 ports to the FPGA, and the FPGA transmits the data to the level conversion chip through the X1_FPGA_B1-X1_FPGA_B32 ports according to the actual time sequence requirement. And then outputting the digital values to a tested electronic part component through a signal playback adapter, wherein the data in the storage module can be the data which is acquired before and directly stored, or can be the data which is further selected or processed by an upper computer, the data is quickly loaded into DDR3 storage particles in a RocketIO GTX mode through a CPCIe bus, the level conversion is carried out, the output is carried out through a DB78 plug, and the digital values are input into electronic components of missile equipment to be tested through the acquisition and playback adapter. DDR3 is used for buffering during acquisition and playback mainly to improve the acquisition and output rate of signals.
The analog signal acquisition card comprises a second external interface module, an AD acquisition circuit, a second control unit, a second storage unit, a second clock unit, a second power supply unit and a second bus unit, wherein the signal output end of the second external interface module is connected with the signal input end of the AD acquisition circuit, and the first external interface module is used for being connected with peripheral equipment; the AD acquisition circuit is in bidirectional connection with the second control unit and is used for analog-to-digital conversion; the second storage unit is connected with the second control unit in a bidirectional way and is used for storing data; the second clock unit is used for providing a working clock for the second control unit and the AD acquisition circuit; the second power supply unit is connected with a power supply input end of a module needing power supply in the analog signal acquisition card and is used for providing working power supply for the module needing power supply; the second bus unit is connected with the second control unit in a bidirectional way and is used for carrying out data exchange with the controller in the bidirectional way.
As shown in fig. 3, the analog signal acquisition card mainly completes the functions of acquisition and playback of analog quantity of electronic components of the missile weapon system, in practical application, the number of acquisition channels and the sampling rate can be configured according to requirements, the analog quantity can be acquired after the configuration is completed, the analog signal enters an AD9268 type ADC analog-digital conversion circuit after passing through a front-end impedance matching and filtering circuit, and then the data after a/D conversion is sent to a memory card for data storage. If the data is to be further analyzed, the data in the memory card can be quickly transmitted to an upper computer for storage, waveform display, data analysis, data processing and the like in a DMA mode through the CPCIe bus.
Similar to the acquisition process of digital signals, analog signals enter a board card through an SMA plug, and are sent to an FPGA after being converted by an operational amplifier and an AD chip. The FPGA temporarily stores the acquired data into DDR3 particles (2 GB capacity), and after the acquisition is completed, the acquired data is transmitted to the controller through the CPCIe bus.
The analog signal acquisition card and the digital signal environment analog card are the same in circuit, and the difference is that the analog-digital conversion module is used for the digital quantity function storage module. In consideration of expansibility of ADC acquisition channels, the module reserves a multichannel synchronous signal interface, so that multichannel AD can be conveniently and synchronously acquired according to external trigger signals, and acquisition control is realized under the control of FPGA.
An active low-pass filter formed by an ADA4938-2 differential driving chip is arranged between the SMA connector and the ADC, so that signal transmission distortion is avoided, and signal quality is ensured.
According to the sampling requirement and the sampling theorem, in order to make the signal undistorted, the sampling rate of the ADC cannot be lower than 100MHz, and the selected AD9268 chip is a 4-channel, 16-bit and capable of supporting a 100MSPS sampling rate analog-to-digital converter (ADC), and an external reference voltage source or a driving device is not needed in the application.
The synchronous acquisition signal of the multichannel ADC is a key point of the design of a large-scale data acquisition system, a synchronous signal input and output interface is reserved in the design, and when a single module works, the synchronous signal is useless; when the modules work cooperatively, any one of the modules can be set as a master card or a slave card, and the synchronous signal is output when the module is used as a master card, and the synchronous signal is input when the module is used as a slave card.
Multichannel digital/analog signal high-speed mixed sampling:
after passing through a 74LVC1T45 level conversion chip and an analog-to-digital conversion module on the acquisition card, synchronous parallel digital quantity is output, the digital quantity enters DDR3 cache particles through an FPGA logic control circuit under the control of the same clock, and the two cache chips can maintain all channels of the 4 acquisition cards to finish full-speed sampling for 3.6s at 100MB/s without overflowing.
In the actual sampling process, since the pulse repetition period of the radar is not more than 2ms, data information acquisition with more than 1800 pulse repetition periods can be ensured if DDR3 memory particles with 2GB memory space are needed. If pulse accumulation is calculated for 10 times, data fusion information is calculated according to target information after 15 times of accumulation, and 12 times of data fusion period information sampling can still be completed. In actual equipment detection, however, much less information is needed to sample. The 2GB DDR3 memory granule fully satisfies the test requirements in terms of capacity.
In order to realize the time sequence problem among the boards, a high-speed clock signal is adopted to synchronously control the boards, and the boards work under unified coordination. In addition, the system is also provided with an external trigger mode, can be set manually, can realize signal acquisition or playback through triggering when needed, and has strong flexibility. The synchronous clock architecture of the system can fully meet the synchronous acquisition requirement of analog signals and digital signals in the system and the synchronous and random expansion requirement of system acquisition. The configuration relationship between the system trigger bus and the acquisition clock is shown in fig. 4.
FPGA synchronous clock design:
the signal acquisition board card generates CPCIe bus trigger signals to complete sampling trigger, and after the main control computer program instruction issues the sampling trigger signals, each acquisition card can trigger sampling at the same time. The system host generates a 100MHz sampling clock through a main card in the PXIe case, one path is supplied to the main card for use, and the other three paths are supplied to sampling clocks required by other three acquisition cards.
The clock circuits of the digital signal environment analog card and the analog signal acquisition card are the same, and the system synchronous clock schematic diagram and the FPGA clock distribution schematic diagram are shown in fig. 5 and 6.
The clock circuit is composed of a SIT9102 crystal oscillator and an impedance matching circuit, the SIT9102 crystal oscillator on the PXI chassis main card forms a differential oscillation signal, the differential oscillation signal enters an XC7K325T-FFG900C type FPGA through SYS_REFCLK_C_P and SYS_REFCLK_C_N ports, and a phase-locked loop module in the FPGA is utilized to form an accurate 100MHz clock synchronization signal. The clock synchronization signals are input through CPCIE_C_REFCLK_P and CPCIE_C_REFCLK_N ports, and are output from the CPCIE_REFCLK_P port of the board card J3-E bus interface and the CPCIE_REFCLK_N port of the J3-F bus interface through a blocking filter and an impedance matching circuit.
The 100MHz synchronization clock output by the master card enters the slave card through the CPCIE_REFCLK_P port of the slave card J3-E bus interface and the CPCIE_REFCLK_N port of the J3-F bus interface. The slave card receives the synchronous clock signal from the bus interface, enters the CPCIE_C_REFCLK_P and CPCIE_C_REFCLK_N ports of the slave card FPGA through the blocking filter and the impedance matching circuit, and then realizes the clock frequency locking of the slave card to the master card through the slave card FPGA phase-locked loop module. The slave card and the master card form clock series connection, so that accurate clock synchronization among the cards is ensured.
The system FPGA clock synchronization modules of the analog signal acquisition card and the digital signal environment analog card are identical, and the clock signals of the board cards at all slots of the chassis are not controlled by a bus, so that the realization of the clock synchronization of the board cards and the random expansion function of the system is greatly simplified.
Sampling front-end clock design:
for a digital signal environment analog card, a clock is not needed when the acquisition and playback of signals pass through a 74LVC1T45 level conversion chip, and the FPGA uses the 100MHz synchronous clock of the FPGA when the converted 3.3V digital level signals are read and output.
For the analog signal acquisition card, the signal utilizes AD9268 to convert the analog signal into a 16-bit 3.3V digital level signal, and the clock distribution schematic diagram of the analog signal acquisition card is shown in FIG. 7.
The analog signals pass through an SMA interface, pass through an active low-pass filter constructed by an operational amplifier chip ADA4938 as a main element to form differential signals, and enter an AD9268 analog-to-digital converter. The 100MHz synchronous clock differential signals of the FPGA are output from FPGA_CLK_OUTP and FPGA_CLK_OUTN ports of the XCK325T-2FFG900 type FPGA, the signals output by CLK_AD0-CLK_AD3 are input to CLK < 0+ > -CLK < 3+ > ports of four AD9268 type AD conversion chips through equal-length wiring and impedance matching filter circuits by CY2305SC clock distribution driving chips, and CLK < 0- > to CLK < 3 > -grounding is carried out.
The FPGA uses the 100MHz synchronous clock of the FPGA when reading the converted 3.3V digital level signal.
DDR3 cache clock design:
the synchronous clock signal is required to be used when storing data into the DDR3 cache granule. The DDR3 synchronous clock schematic and DDR3 clock distribution schematic are shown in fig. 8 and 9.
The synchronous clock signal of DDR3 is generated by a SIT9102 crystal oscillator to generate an oscillation signal, and the oscillation signal enters a CDCLVP1102RGT type clock buffer through DDR3_CLK_P and DDR3_CLK_N ports after passing through an impedance matching and blocking filter circuit. The clock buffer allocates clocks, outputs from the DDR3_A_SYS_CLKP, DDR3_A_SYS_CLKN differential port and DDR3_B_SYS_CLKP, DDR3_B_SYS_CLKN differential port, and outputs FPGA from the DDR3_A_SYSCLK_ P, DDR3_A_SYSCLK_N differential port and DDR3_B_SYSCLK_ P, DDR3_B_SYSCLK_N differential port after passing through the impedance matching and blocking filter circuit again.
The FPGA firstly uses an internal phase-locked loop module to accurately lock an oscillation signal by 100HMz, then uses an internal frequency multiplication module to form an 800MHz synchronous clock signal, and inputs DDR3 cache from a DDR3_A_C0_ P, DDR3 _A_C0_N differential port and a DDR3_B_C0_ P, DDR3 _B_C0_N differential port respectively for clock synchronous control of DDR3 reading and writing.
High-speed data storage design:
the data flow control of the present system is shown in fig. 10. Data in the DDR3 cache in the slave card is transmitted to the master card through a RocketIO GTX high-speed storage technology, the master card directly receives control of the master control computer, and the data is transmitted to a hard disk of the master control computer through a CPCIe bus for cache.
The system has larger data volume in the process of realizing high-speed acquisition of digital quantity and analog quantity, the data writing and reading speed is at least 1600MByte/s, the time of data acquisition and playback is covered in the whole self-checking process of equipment, and the current high-speed storage equipment is difficult to reach the technical index requirements. In order to realize data acquisition of all parallel channels of the system at such a high speed and realize real-time high-speed storage under the condition of not losing any information, the system adopts two MT41J64M16 type DDR3 chips for data storage, and the chips are high-speed storage chips with the width of 16 bits of memory 1G. The two DDR3 work at the same time, the read-write speed can reach 6.4GB/S at least, the data collected by the 4-path ADC chip is more than enough to be stored, and the digital collection playback card with the clock distribution function of the higher sampling clock can also form a system, so that the applicability of the system is improved. In order to realize the storage technical index of high-speed and large data volume, FPGA is adopted to realize the read-write control of DDR3 chips. Because of the real-time writing in the parallel state and the high speed of the FPGA, the design can meet the requirements of high-speed storage and playback, but has high requirements on the firmware design of the FPGA.
The data volume is calculated under the condition that all channels are in a full-speed acquisition state, and is not acquired in the full-speed acquisition state in general, the highest acquisition rate of each channel can be set through software, and the channel for acquiring the low-frequency signals can acquire at a lower rate, so that the actual acquired data volume is far smaller than the calculated data.
RocketIO GTX high-speed storage design:
in order to meet the storage requirement of data up to 1600MByte/s, the data which needs DDR3 chip buffer data to be transmitted to a hard disk on a main controller through a CPCIe bus has high enough rate, and the system adopts a RocketIO GTX technology to realize data transmission between a main card and a slave card. The schematic diagram of the GTX high speed transmission circuit design is shown in fig. 11.
The synchronous clock signal of GTX high-speed transmission is generated by SIT9102 crystal oscillator, and enters a CDCLVP1102RGT clock buffer through GTX_CLK_P and GTX_CLK_N ports after passing through an impedance matching and blocking filter circuit. The clock register distributes clocks, outputs from the RIO_Q2_REFCLK_ P, RIO _Q2_REFCLK_N differential port and the RIO_Q3_REFCLK_ P, RIO _Q3_REFCLK_N differential port, and after passing through the impedance matching and blocking filter circuit again, outputs FPGA from the RIO_Q2_C_REFCLK_ P, RIO _Q2_C_REFCLK_N differential port and the RIO_Q3_C_REFCLK_ P, RIO _Q3_C_REFCLK_N differential port, and forms 100MHz synchronous clock by the FPGA built-in phase-locked loop.
When the slave card transmits signals to the master card through the GTX high-speed transmission channel, the transmission channels are in differential connection, and the slave cards RIO_C_TX 0_P-RIO_C_TX 7_P channels are connected with the master cards RIO_C_RX 0_P-RIO_C_RX 7_P channels through the backboard bus; when the master card transmits signals to the slave cards, the master cards RIO_C_TX 0_P-RIO_C_TX 7_P channels are connected with the slave cards RIO_C_RX 0_P-RIO_C_RX 7_P channels through the back board bus. And the control of signal transmission is to multiply the 100MHz synchronous clock through FPGA to form an 800MHz transmission clock. The highest data transmission rate of 6.4Gbps of the 8-path GTX channel is ensured.
As shown in FIG. 13, the transmission connection diagram of the GTX bus is that RIO_RX 0_P-RIO_RX 0_N of the main card J2 socket is connected with RIO_TX 0_P-RIO_TX 0_N of the slave card J2 socket through the back board bus, and RIO_TX 0_P-RIO_TX 0_N of the main card J2 socket is connected with RIO_RX 0_P-RIO_RX 0_N of the slave card J2 socket through the back board bus.
CPCIe data transmission design:
when the board card is used as a main card, all data are transmitted to the main control computer or a digital board card playback signal is received from the main control computer through the CPCIe bus. The schematic diagram of the CPCIe data transmission is shown in fig. 13. The 100MHz transmission signal of the main control computer enters a blocking filter and matching circuit through CPCIE_CLK100deg.M_C_P and CPCIE_CLK100deg.M_C_N ports of the board card J3 socket, enters an FPGA, and controls signal transmission according to a bus protocol of CPCIe. When signals are transmitted to the main control computer, the signals enter the FPGA from the DDR3 cache, and enter the main control computer through CPCIE_C_TX0_ P, CPCIE _C_TX 0_N-CPCIE_C_TX 7_ P, CPCIE _C_TX 7_N differential channels on the FPGA, through the blocking filter circuit and corresponding CPCIE_TX0_ P, CPCIE _TX 0_N-CPCIE_TX 7_ P, CPCIE _TX7_N ports on the J3 socket. When a signal is received from the main control computer, the signal enters the blocking filter circuit through the corresponding CPCIE_TX0_ P, CPCIE _TX 0_N-CPCIE_TX 7_ P, CPCIE _TX7_N ports on the socket of the digital card J3, enters the FPGA through the CPCIE_C_TX0_ P, CPCIE _C_TX 0_N-CPCIE_C_TX 7_ P, CPCIE _C_TX 7_N differential channel, and is transmitted to the DDR3 cache.
Expansibility and electromagnetic shielding: the board card adopts a clock bus in the XJ4 interface in the process of designing clock distribution, thereby ensuring the expansibility of the system, and being convenient for realizing the synchronization of digital signal playback and analog signal playback when further developing a DAC signal source or directly using CPCIE bus signal source board card shelf products. In order to ensure the effectiveness of the clock, a load driving circuit is added during clock distribution so as to ensure that the clock signal cannot normally drive other boards due to attenuation in the transmission process.
In order to reduce the crosstalk of signals during high-speed A/D synchronous acquisition and playback between different boards, the board and the bottom plate are designed with good shielding, reasonable circuit layout and wiring are performed, and meanwhile, the crosstalk signals are removed by software.
Claims (5)
1. The analog digital signal synchronous acquisition system is characterized in that: the system comprises a signal acquisition adapter, a digital signal playback adapter, a plurality of digital signal environment analog cards, an analog signal acquisition card, a digital signal storage playback card, a bus module, a controller, a man-machine interaction module and a power module, wherein a signal input end of the signal acquisition adapter receives signals sent by an equipment system, a signal output end of the signal acquisition adapter is respectively connected with the digital signal environment analog cards and the signal input end of the analog signal acquisition card, the digital signal environment analog cards and the analog signal acquisition card are in bidirectional connection with the controller through the bus module, the digital signal storage playback card is in bidirectional connection with the controller through the bus module, a signal output end of the digital signal storage playback card is connected with the signal input end of the digital signal playback adapter, an output end of the digital signal playback adapter is a signal output end of the system, and the digital signal environment analog cards, the analog signal acquisition cards and the digital signal storage playback card are controlled by the controller and are used for processing data under the control of the controller, and the power module is used for providing power supply for the power supply module which needs to be connected with the power supply input end in the analog system; the man-machine interaction module is connected with the controller in a two-way and is used for inputting control commands and displaying output data; one digital signal environment analog card is used as a master card, the rest digital signal environment analog cards are used as slave cards, the controller provides clock signals for the digital signal environment analog card used as the master card, and the digital signal environment analog card used as the master card provides synchronous clock signals for the digital signal environment analog card used as the slave card and the analog signal acquisition card;
the digital signal environment simulation card comprises a first external interface module, a level conversion module, a first control unit, a first storage unit, a first clock unit, a first power supply unit and a first bus unit, wherein the first external interface module is in bidirectional connection with the level conversion module, and the first external interface module is used for being connected with peripheral equipment; the level conversion module is in bidirectional connection with the first control unit and is used for realizing level conversion; the first storage unit is connected with the first control unit in a bidirectional way and is used for storing data; the first clock unit is used for providing a working clock for the first control unit; the first power supply unit is connected with a power supply input end of a module needing power supply in the digital signal environment simulation card and is used for providing working power supply for the module needing power supply; the first bus unit is in bidirectional connection with the first control unit and is used for carrying out data exchange;
the first clock unit comprises an analog signal acquisition card clock distribution module, the clock distribution module comprises a CY2305SC type clock buffer U7, a pin 1 of the U7 is connected with a relevant output end of the second controller through a resistor R56, a pin 2, a pin 3, a pin 5 and a pin 7 of the U7 are respectively clock signal output ends of the clock distribution module, a pin 4 of the U7 is grounded, a pin 6 of the U7 is divided into three paths, the first path is grounded through a capacitor C339, the second path is grounded through a capacitor C338, the third path is connected with a 3.3V power supply through an inductor L6, and a pin 8 of the U7 is suspended.
2. The analog-to-digital signal synchronous acquisition system of claim 1, wherein: the analog signal acquisition card comprises a second external interface module, an AD acquisition circuit, a second control unit, a second storage unit, a second clock unit, a second power supply unit and a second bus unit, wherein the signal output end of the second external interface module is connected with the signal input end of the AD acquisition circuit, and the first external interface module is used for being connected with peripheral equipment; the AD acquisition circuit is in bidirectional connection with the second control unit and is used for analog-to-digital conversion; the second storage unit is connected with the second control unit in a bidirectional way and is used for storing data; the second clock unit is used for providing a working clock for the second control unit and the AD acquisition circuit; the second power supply unit is connected with a power supply input end of a module needing power supply in the analog signal acquisition card and is used for providing working power supply for the module needing power supply; the second bus unit is connected with the second control unit in a bidirectional way and is used for carrying out data exchange with the controller in the bidirectional way.
3. The analog-to-digital signal synchronous acquisition system of claim 1, wherein: the first clock unit comprises a first system synchronous clock module and a first controller clock distribution module, and the system synchronous clock module comprises a SIT9102 crystal oscillator chip U53, and a DC blocking filter and an impedance matching circuit at the periphery of the crystal oscillator chip U53.
4. The analog-to-digital signal synchronous acquisition system of claim 1, wherein: the first clock unit and the second clock unit further comprise a memory synchronous clock module and a memory clock distribution module.
5. An analog to digital signal synchronous acquisition system as in claim 4, wherein: the memory synchronous clock module comprises a CDCLVP1102RGT type clock buffer chip U51, 1 pin, 16 pin and 17 pin of the U51 are grounded, 2-4 pin and 13-15 pin of the U51 are suspended, 9-12 pin of the U51 is a clock signal output end, 3.3V power supply is connected with 5 pin of the U51 after passing through an inductor B2, a filter capacitor C321, a capacitor C252 and a capacitor C264 are connected in parallel with the input end of the 3.3V power supply, 8 pin of the U51 is grounded through a capacitor C322 and a capacitor C323 respectively, 1 pin of a SIT9102 crystal oscillator chip U52 is connected with 3.3V power supply, 2 pin of the U52 is suspended, 3 pin of the U52 is grounded, 4 pin and 5 pin of the U52 are respectively connected with 6 pin and 7 pin of the U51 after passing through a capacitor C326 and a capacitor C327, one end of a resistor R is connected with 4 pin of the U52, and the other end of the resistor R465 is connected with 5 pin of the U52.
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| CN111077498A (en) * | 2019-11-28 | 2020-04-28 | 北京航天控制仪器研究所 | Synchronous signal acquisition and processing device based on optical fiber hydrophone array |
| RU2728493C1 (en) * | 2019-12-25 | 2020-07-29 | Акционерное общество "Корпорация "Тактическое ракетное вооружение" | Method of recording and processing information during testing of unmanned aerial vehicles and device for its implementation |
| CN112597097B (en) * | 2020-12-28 | 2022-11-22 | 山东浪潮科学研究院有限公司 | Communication system based on ADC data acquisition card, application method and medium thereof |
| CN112816810A (en) * | 2020-12-28 | 2021-05-18 | 国网北京市电力公司 | Data acquisition device and data acquisition method |
| CN113553280B (en) * | 2021-06-21 | 2023-04-28 | 上海机电工程研究所 | Based on I 2 Multi-module time-sharing power-on method and system for integrated electronic platform of C bus |
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