CN109994381A - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
- Publication number
- CN109994381A CN109994381A CN201711471524.9A CN201711471524A CN109994381A CN 109994381 A CN109994381 A CN 109994381A CN 201711471524 A CN201711471524 A CN 201711471524A CN 109994381 A CN109994381 A CN 109994381A
- Authority
- CN
- China
- Prior art keywords
- passivation layer
- termination environment
- semiconductor substrate
- production method
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000010410 layer Substances 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000002161 passivation Methods 0.000 claims abstract description 46
- 230000001413 cellular effect Effects 0.000 claims abstract description 41
- 239000011241 protective layer Substances 0.000 claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 claims abstract description 25
- 239000004642 Polyimide Substances 0.000 claims description 23
- 229920001721 polyimide Polymers 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 19
- 238000000227 grinding Methods 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229910001651 emery Inorganic materials 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 239000011469 building brick Substances 0.000 claims description 4
- 238000007711 solidification Methods 0.000 claims description 4
- 230000008023 solidification Effects 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims 1
- 238000011946 reduction process Methods 0.000 abstract description 10
- 239000012634 fragment Substances 0.000 abstract description 8
- 239000012212 insulator Substances 0.000 description 15
- 239000000463 material Substances 0.000 description 9
- 239000002184 metal Substances 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 238000004026 adhesive bonding Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic device, which comprises provides semiconductor substrate, the front of the semiconductor substrate is formed with cellular region and the termination environment around the cellular region；Passivation layer is formed on the termination environment；The back side of the semiconductor substrate is thinned；Protective layer is formed on the passivation layer.The production method of the semiconductor devices provided according to the present invention; by the way that the semiconductor substrate back side is first thinned after termination environment forms passivation layer; then protective layer is formed on the passivation layer again; to keep the difference in height of termination environment and cellular region during reduction process smaller; reduce the generation and appearance of fragment and micro-crack, and optimizes reduction process window.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technique
IGBT (Insu1ated Gate Bipo1ar Transistor, insulated gate bipolar transistor) is a kind of common
High-power discrete device, ideal IGBT have high-breakdown-voltage, low conduction voltage drop, the turn-off time is short, the resistance to shorting time is long
The advantages that.The static state (Vcesat) and dynamic (Eoff) power consumption that reduce device are always the developing direction of IGBT.Theoretically, static
It is (trade-off) mutually restricted with dynamic power consumption.It can by the way that thickness of detector is further thinned according to existing IGBT structure
Optimization is the developing way of IGBT of new generation while to realize static and dynamic power consumption.
But the thickness of the IGBT device (such as 600V IGBT) of mainstream is only 60 μm or so at present, is further thinned and needs
Thickness of detector is optimized to 55 μm or even 50 μm, this is for current technique manufacturing capacity, especially grinding (grinding) work
Skill is greatly to challenge.
Since there is also the areas (terminal) of the terminal as caused by protective layer and passivation layer structure and cellular in the front IGBT
(cell) difference in height in area, the presence of the difference in height will lead to chipping in grinding technics or generate micro-crack, and micro-crack
It is chipping in the subsequent process that defect can further result in wafer (wafer).
Therefore, it is necessary to the production method for proposing a kind of new semiconductor devices, to solve the above problems.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention provides a kind of production method of semiconductor devices, comprising the following steps:
Semiconductor substrate is provided, the front of the semiconductor substrate is formed with cellular region and the terminal around the cellular region
Area；
Passivation layer is formed on the termination environment；
The back side of the semiconductor substrate is thinned；
Protective layer is formed on the passivation layer.
Further, the semiconductor devices includes insulated gate bipolar transistor.
Further, the protective layer includes polyimide layer.
Further, further include the steps that carrying out the protective layer photoetching, solidification after forming the protective layer.
Further, using passivation layer described in chemical vapor deposition growth.
Further, mechanical emery wheel grinding is used so that the back side of the semiconductor substrate is thinned.
Further, after forming passivation layer on the termination environment, the model of the difference in height of the cellular region and the termination environment
Enclose is 2 μm -3 μm.
Further, after forming protective layer on the passivation layer, the model of the difference in height of the cellular region and the termination environment
Enclose is 12 μm -13 μm.
The present invention also provides a kind of semiconductor devices made according to the above method, comprising:
Semiconductor substrate, the front of the semiconductor substrate are formed with cellular region and the termination environment around the cellular region；
Passivation layer is formed on the termination environment；
Matcoveredn is formed on the passivation layer.
The present invention also provides a kind of electronic device, seven include above-mentioned semiconductor device and being connected with the semiconductor devices
The electronic building brick connect.
The production method of the semiconductor devices provided according to the present invention, by the way that half is first thinned after termination environment forms passivation layer
Then conductor substrate back forms protective layer on the passivation layer again, to make termination environment and cellular during reduction process
The difference in height in area is smaller, reduces the generation and appearance of fragment and micro-crack, and optimizes reduction process window.
Detailed description of the invention
The embodiment of the present invention is described in more detail in conjunction with the accompanying drawings, the above and other purposes of the present invention,
Feature and advantage will be apparent.Attached drawing is used to provide to further understand the embodiment of the present invention, and constitutes explanation
A part of book, is used to explain the present invention together with the embodiment of the present invention, is not construed as limiting the invention.In the accompanying drawings,
Identical reference label typically represents same parts or step.
In attached drawing:
Fig. 1 shows a kind of schematic flow of the production method of semiconductor devices according to an exemplary embodiment of the present invention
Figure.
Fig. 2A -2D shows the device obtained respectively the step of method according to an exemplary embodiment of the present invention is successively implemented
The schematic cross sectional view of part.
Fig. 3 shows the schematic diagram of electronic device according to an exemplary embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiments.
The thickness of the IGBT device (such as 600V IGBT) of mainstream is only 60 μm or so at present, is further thinned and needs device
To 55 μm or even 50 μm, this is thickness optimization for current technique manufacturing capacity, especially grinding (grinding) technique
Greatly challenge.
Since there is also the areas (terminal) of the terminal as caused by protective layer and passivation layer structure and cellular in the front IGBT
(cell) difference in height in area, the difference in height is even up to 13 μm or more sometimes, and the presence of the difference in height will lead in grinding technics
Fragment occurs or generates micro-crack, and micro-crack defect can further result in wafer (wafer) and fragment occurs in the subsequent process.
To solve the above-mentioned problems, it mostly uses greatly at present before grinding reduction process in 50 μm of IGBT device front attaching-
100 μm of soft organic film reduces fragment as buffer layer to reduce positive difference in height bring stress in grinding technics
With the generation and appearance of micro-crack.But the program needs to take organic film off after being thinned, and takes off film on the wafer after being thinned and deposits
In the risk of fragment；In addition, organic film is only capable of as buffer layer, cannot direct abatement device difference in height, make reduction process window
It is very narrow, and then limit and further improve device performance by being thinned.
Therefore, it is necessary to the production method for proposing a kind of new semiconductor devices, to solve the above problems.
In view of the deficiencies of the prior art, the present invention provides a kind of production method of semiconductor devices, comprising:
Semiconductor substrate is provided, the front of the semiconductor substrate is formed with cellular region and the terminal around the cellular region
Area；
Passivation layer is formed on the termination environment；
The back side of the semiconductor substrate is thinned；
Protective layer is formed on the passivation layer.
Wherein, the semiconductor devices includes insulated gate bipolar transistor；The protective layer includes polyimide layer；?
The protective layer is formed to further include the steps that carrying out the protective layer photoetching, solidification later；Using chemical vapor deposition growth
The passivation layer；Mechanical emery wheel grinding is used so that the back side of the semiconductor substrate is thinned；Passivation is formed on the termination environment
After layer, the range of the difference in height of the cellular region and the termination environment is 2 μm -3 μm；Protective layer is formed on the passivation layer
Afterwards, the range of the difference in height of the cellular region and the termination environment is 12 μm -13 μm.
The production method of the semiconductor devices provided according to the present invention, by the way that half is first thinned after termination environment forms passivation layer
Then conductor substrate back forms protective layer on the passivation layer again, to make termination environment and cellular during reduction process
The difference in height in area is smaller, reduces the generation and appearance of fragment and micro-crack, and optimizes reduction process window.
Below with reference to Fig. 1 and Fig. 2A -2D, one kind that wherein exemplary embodiment of the present one is shown in Fig. 1 is partly led
The schematic flow chart of the production method of body device.Fig. 2A -2D be according to an exemplary embodiment of the present one method it is successively real
The schematic cross sectional view for the device that the step of applying obtains respectively.
The present invention provides a kind of preparation method of semiconductor devices, as shown in Figure 1, the key step packet of the preparation method
It includes:
Step S101: providing semiconductor substrate, and the front of the semiconductor substrate is formed with cellular region and around the member
The termination environment in born of the same parents area；
Step S102: passivation layer is formed on the termination environment；
Step S103: the back side of the semiconductor substrate is thinned；
Step S104: protective layer is formed on the passivation layer.
In the following, being described in detail to the specific embodiment of the production method of semiconductor devices of the invention.
Firstly, executing step S101 provides semiconductor substrate 200, the semiconductor substrate 200 is just as shown in Figure 2 A
Face is formed with cellular region I and the termination environment II around the cellular region.
Illustratively, the semiconductor substrate 200 can be following at least one of the material being previously mentioned: monocrystalline silicon,
Silicon (SSOI) is laminated on silicon-on-insulator (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator are laminated on insulator
SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Illustratively, the semiconductor substrate 200 further includes the positive manufacturing process of semiconductor substrate, such as in semiconductor
Interlayer dielectric layer and metal electrode that the front of substrate 200 is formed etc..Specifically, in the present embodiment, the semiconductor device provided
Part is insulated gate bipolar transistor (Insu1ated Gate Bipo1ar Transistor, IGBT), in semiconductor substrate
200 fronts are formed with cellular region I and the termination environment II around the cellular region.Wherein, be formed in the cellular region I groove with
And the base region positioned at groove two sides, the cellular region I further includes grid and emitter；The termination environment II includes field ring region
201, Metal field plate 204 and the separation layer area between the field ring region and Metal field plate, the field ring region 201 are field oxidation
Layer, the separation layer area includes polysilicon layer 202 and interlayer dielectric layer 203 etc..
Next, executing step S102, as shown in Figure 2 B, passivation layer 205 is formed on the termination environment II.
Illustratively, any existing skill that the forming method of passivation layer 205 can be familiar with using those skilled in the art
Art, preferably chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD),
Fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD).As an example, the passivation
Layer 205 is silicon nitride layer, and specifically, when carrying out cvd silicon nitride, power 200W-400W, heating makes cavity
For interior temperature to 300 DEG C -400 DEG C, the intracorporal pressure of chamber is 2Torr-5Torr, the silane (SiH of use4) gas flow be
The gas flow of 100sccm-200sccm, He are 350sccm-450sccm, NH3Gas flow is 300sccm-500sccm, is sunk
The product time continues 3s-5s.
Referring to Fig. 2 B, after forming passivation layer 205 on the termination environment II, the height of the cellular region I and termination environment II
The range of poor h is 2 μm -3 μm.
Next, executing step S103 is thinned the back side of the semiconductor substrate 200 as shown in Figure 2 C.
Illustratively, carried out from the back side of the semiconductor substrate 200 it is thinned, to remove certain thickness backing material,
To achieve the purpose that thickness of detector optimizes.The method of the thinning back side can select method commonly used in the art, such as use machine
Tool emery wheel is ground (grinding).Specifically, by taking 600V IGBT device as an example, thickness is about 60 μm, using machine emery wheel
The semiconductor substrate 200 is thinned, so that IGBT device reaches target thickness, such as 55 μm -50 μm, until.
Next, executing step S104, as shown in Figure 2 D, protective layer 206 is formed on the passivation layer 205.
Illustratively, the material of the protective layer 206 is polyimides.It is coated with polyimide layer, it is normal that this field can be used
The method of static gluing or dynamic gluing.Static gluing is the center for polyimides being deposited in first semiconductor substrate,
Then low speed rotation spreads out polyimides, then high speed rotation gets rid of the polyimides being more than, when high speed rotation in polyimides
Solvent can volatilize a part；Dynamic gluing is that dynamic sprays polyimides, while semiconductor substrate low speed rotation, it is therefore an objective to be helped
The diffusion that polyimides is initial is helped, polyimides more evenly can be reached with less amount of polyimides in this way
Film, then high speed rotation completion finally require uniform and thin polyimide film.Illustratively, dynamic can be used in polyimide layer
Rotating coating is coated on substrate.
Referring to Fig. 2 D, after forming protective layer 206 on the passivation layer 205, the height of the cellular region I and termination environment II
The range of poor H is 12 μm -13 μm.
Next, further including carrying out the works such as photoetching, solidification to the protective layer 206 after forming the protective layer 206
Skill step.
Illustratively, photoetching process refers to being exposed to the polyimide layer, developing, to realize pattern
The process of change.Specifically, polyimide layer is exposed, in polyamides via photomask using the light source with predetermined close
Patterning is realized in imine layer.Illustratively, light source can select ultraviolet light, deep ultraviolet light, extreme ultraviolet light or electron beam, light
The dosage in source is greater than the critical energy value that polyimide layer can be made to be imaged.It is anti-that photochemistry occurs for the polyimides that exposure-processed is crossed
It answers, property is changed, and will occur to chemically react and remove with developer solution when development.Polyimides is as negative photoresist material
Material is not exposed region using what organic solvent dissolved polyimides during development treatment.It is formed patterned poly-
Imide layer.
Illustratively, curing process can effectively improve the surface compact degree of protective layer 206, avoid or reduce defect
It generates, to improve the corrosion resistance of protective layer 206.As an example, polyimide layer is subjected to the processing that is heating and curing,
The temperature range being heating and curing is 80 DEG C -180 DEG C, preferably 90 DEG C -170 DEG C, but the temperature being heating and curing and unlimited
In 80 DEG C -180 DEG C.The time being heating and curing can be 15s-300s, preferably 30s-120s.
2D with reference to the accompanying drawing, to the structure of the semiconductor devices provided in an embodiment of the present invention according to above method production
It is described.The semiconductor devices includes: semiconductor substrate 200, and the front of the semiconductor substrate is formed with cellular region I and ring
Around the termination environment II of the cellular region；Passivation layer 205 is formed on the termination environment；Matcoveredn is formed on the passivation layer
206。
Illustratively, the semiconductor substrate 200 can be following at least one of the material being previously mentioned: monocrystalline silicon,
Silicon (SSOI) is laminated on silicon-on-insulator (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator are laminated on insulator
SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Illustratively, the semiconductor substrate 200 further includes the positive manufacturing process of semiconductor substrate, such as in semiconductor
Interlayer dielectric layer and metal electrode that the front of substrate 200 is formed etc..Specifically, in the present embodiment, the semiconductor device provided
Part is insulated gate bipolar transistor (Insu1ated Gate Bipo1ar Transistor, IGBT), in semiconductor substrate
200 fronts are formed with cellular region I and the termination environment II around the cellular region.Wherein, be formed in the cellular region I groove with
And the base region positioned at groove two sides, the cellular region I further includes grid and emitter；The termination environment II include field ring region,
Metal field plate and the separation layer area between the field ring region and Metal field plate, the separation layer area include oxide skin(coating), floor
Between dielectric layer etc..
Illustratively, the passivation layer 205 is silicon nitride layer.It is described after forming passivation layer 205 on the termination environment II
The range of the difference in height h of cellular region I and termination environment II is 2 μm -3 μm.
Illustratively, the material of the protective layer 206 is polyimides.Protective layer 206 is formed on the passivation layer 205
Afterwards, the range of the height difference H of the cellular region I and termination environment II is 12 μm -13 μm.
The present invention also provides a kind of electronic devices, including semiconductor devices and the electronics being connected with the semiconductor devices
Component.Wherein, which includes: semiconductor substrate 200, and the front of the semiconductor substrate is formed with I He of cellular region
Around the termination environment II of the cellular region；Passivation layer 205 is formed on the termination environment；Matcoveredn is formed on the passivation layer
206。
Wherein, the semiconductor substrate 200 can be following at least one of the material being previously mentioned: monocrystalline silicon, insulation
Silicon (SOI) on body is laminated silicon (SSOI), SiGe (S-SiGeOI), germanium on insulator SiClx is laminated on insulator on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..It could be formed with device, such as NMOS and/or PMOS in semiconductor substrate
Deng.Equally, conductive member can also be formed in semiconductor substrate, conductive member can be the grid, source electrode or leakage of transistor
Pole is also possible to the metal interconnection structure, etc. being electrically connected with transistor.In addition, can also be formed in the semiconductor substrate
Isolation structure, the isolation structure are shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.As
Example, in the present embodiment, the constituent material of semiconductor substrate select silicon-on-insulator.
Wherein, the electronic building brick can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.
Wherein, Fig. 3 shows the example of mobile phone.The outside of mobile phone 300 is provided with including the display portion in shell 301
302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
The production method of the semiconductor devices provided according to the present invention, by the way that half is first thinned after termination environment forms passivation layer
Then conductor substrate back forms protective layer on the passivation layer again, to make termination environment and cellular during reduction process
The difference in height in area is smaller, reduces the generation and appearance of fragment and micro-crack, and optimizes reduction process window.
Invention is illustrated through the foregoing embodiment, but it is to be understood that, above-described embodiment is only intended to lift
The purpose of example and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also make more kinds of changes
Type and modification, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention is by attached
Claims and its equivalent scope of category are defined.
Claims (10)
1. a kind of production method of semiconductor devices, which comprises the following steps:
Semiconductor substrate is provided, the front of the semiconductor substrate is formed with cellular region and the termination environment around the cellular region；
Passivation layer is formed on the termination environment；
The back side of the semiconductor substrate is thinned；
Protective layer is formed on the passivation layer.
2. production method as described in claim 1, which is characterized in that the semiconductor devices includes insulated gate bipolar crystal
Pipe.
3. production method as described in claim 1, which is characterized in that the protective layer includes polyimide layer.
4. production method as claimed in claim 3, which is characterized in that after forming the protective layer further include to the guarantor
Sheath carries out the step of photoetching, solidification.
5. production method as described in claim 1, which is characterized in that using passivation layer described in chemical vapor deposition growth.
6. production method as described in claim 1, which is characterized in that use mechanical emery wheel grinding so that the semiconductor lining is thinned
The back side at bottom.
7. production method as described in claim 1, which is characterized in that after forming passivation layer on the termination environment, the member
The range of the difference in height in born of the same parents area and the termination environment is 2 μm -3 μm.
8. production method as described in claim 1, which is characterized in that after forming protective layer on the passivation layer, the member
The range of the difference in height in born of the same parents area and the termination environment is 12 μm -13 μm.
9. a kind of semiconductor devices of method production according to claim 1-8 characterized by comprising
Semiconductor substrate, the front of the semiconductor substrate are formed with cellular region and the termination environment around the cellular region；
Passivation layer is formed on the termination environment；
Matcoveredn is formed on the passivation layer.
10. a kind of electronic device, which is characterized in that partly led including semiconductor devices as claimed in claim 9 and with described
The electronic building brick that body device is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711471524.9A CN109994381A (en) | 2017-12-29 | 2017-12-29 | A kind of semiconductor devices and preparation method thereof, electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711471524.9A CN109994381A (en) | 2017-12-29 | 2017-12-29 | A kind of semiconductor devices and preparation method thereof, electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109994381A true CN109994381A (en) | 2019-07-09 |
Family
ID=67108728
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711471524.9A Pending CN109994381A (en) | 2017-12-29 | 2017-12-29 | A kind of semiconductor devices and preparation method thereof, electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109994381A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002324807A (en) * | 2001-04-26 | 2002-11-08 | Fuji Electric Co Ltd | Method for manufacturing semiconductor device |
| CN102790082A (en) * | 2011-05-16 | 2012-11-21 | 瑞萨电子株式会社 | Ie-type trench gate igbt |
| CN103035694A (en) * | 2012-12-04 | 2013-04-10 | 国网智能电网研究院 | Insulated gate bipolar translator (IGCB) chip with terminal protection structure and manufacturing method of IGCB chip with terminal protection structure |
| CN104091764A (en) * | 2014-07-25 | 2014-10-08 | 中航（重庆）微电子有限公司 | IGBT device preparing method and IGBT device |
| CN104332494A (en) * | 2013-07-22 | 2015-02-04 | 无锡华润上华半导体有限公司 | Insulated-gate bipolar transistor and manufacturing method thereof |
| CN104934470A (en) * | 2014-03-18 | 2015-09-23 | 国家电网公司 | IGBT chip and manufacturing method thereof |
| CN105185829A (en) * | 2015-08-28 | 2015-12-23 | 深圳深爱半导体股份有限公司 | Power transistor and manufacturing method thereof |
| CN105679667A (en) * | 2016-03-09 | 2016-06-15 | 上海道之科技有限公司 | Manufacturing method for terminal structure of trench IGBT device |
-
2017
- 2017-12-29 CN CN201711471524.9A patent/CN109994381A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002324807A (en) * | 2001-04-26 | 2002-11-08 | Fuji Electric Co Ltd | Method for manufacturing semiconductor device |
| CN102790082A (en) * | 2011-05-16 | 2012-11-21 | 瑞萨电子株式会社 | Ie-type trench gate igbt |
| CN103035694A (en) * | 2012-12-04 | 2013-04-10 | 国网智能电网研究院 | Insulated gate bipolar translator (IGCB) chip with terminal protection structure and manufacturing method of IGCB chip with terminal protection structure |
| CN104332494A (en) * | 2013-07-22 | 2015-02-04 | 无锡华润上华半导体有限公司 | Insulated-gate bipolar transistor and manufacturing method thereof |
| CN104934470A (en) * | 2014-03-18 | 2015-09-23 | 国家电网公司 | IGBT chip and manufacturing method thereof |
| CN104091764A (en) * | 2014-07-25 | 2014-10-08 | 中航（重庆）微电子有限公司 | IGBT device preparing method and IGBT device |
| CN105185829A (en) * | 2015-08-28 | 2015-12-23 | 深圳深爱半导体股份有限公司 | Power transistor and manufacturing method thereof |
| CN105679667A (en) * | 2016-03-09 | 2016-06-15 | 上海道之科技有限公司 | Manufacturing method for terminal structure of trench IGBT device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9478463B2 (en) | Device and method for improving RF performance | |
| US20150132922A1 (en) | Ion reduced, ion cut-formed three-dimensional (3d) integrated circuits (ic) (3dics), and related methods and systems | |
| CN103426832B (en) | Chip packing-body and forming method thereof | |
| TW200629410A (en) | Semiconductor substrate, semiconductor device and method of manufacturing the same | |
| CN105428416A (en) | Silicon gate graphene/black phosphorus transistor and preparation method | |
| CN103915322B (en) | The preparation method of semiconductor device | |
| CN105097954B (en) | A kind of manufacturing method and electronic device of semiconductor devices | |
| CN109994381A (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| US20170084628A1 (en) | Substrate-transferred, deep trench isolation silicon-on-insulator (soi) semiconductor devices formed from bulk semiconductor wafers | |
| US20170194504A1 (en) | Integrated circuits with gaps | |
| CN105552019A (en) | Silicon substrate material on insulator island and manufacturing method thereof | |
| CN109994388A (en) | A kind of manufacturing method of semiconductor devices, semiconductor devices and electronic device | |
| CN105448971B (en) | A kind of semiconductor devices and preparation method thereof and electronic device | |
| CN105845615B (en) | Method for manufacturing semiconductor device and electronic device | |
| CN108155144A (en) | A kind of production method of semiconductor devices | |
| CN106033717A (en) | Manufacturing method of semiconductor device, semiconductor device, and electronic device | |
| KR100701405B1 (en) | MOS Transistor and the manufacturing method thereof | |
| CN105097677B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| WO2013097551A1 (en) | Method for preparing semiconductor device | |
| CN105448650A (en) | Semiconductor device and preparation method thereof, and electronic device | |
| US8716104B1 (en) | Method of fabricating isolation structure | |
| CN107619019A (en) | A kind of MEMS and its manufacture method and electronic installation | |
| TWI786782B (en) | Method of manufacturing a silicon on insulator wafer | |
| US9349748B2 (en) | Method for forming deep trench isolation for RF devices on SOI | |
| CN103426856B (en) | Wafer encapsulation body and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190709 |