CN109994081B

CN109994081B - Display device and operation method thereof

Info

Publication number: CN109994081B
Application number: CN201810004043.5A
Authority: CN
Inventors: 吴东颖; 蔡政哲
Original assignee: Himax Technologies Ltd
Current assignee: Himax Technologies Ltd
Priority date: 2018-01-03
Filing date: 2018-01-03
Publication date: 2021-04-20
Anticipated expiration: 2038-01-03
Also published as: CN109994081A

Abstract

A display device includes a timing controller and a source driver. The time schedule controller generates an adjusting pulse every other preset time and receives the 1 st to the Nth picture data in sequence within the preset time. The time schedule controller adjusts the 1 st to Kth image data according to a plurality of compensation gains and adjusts the (K +1) th to Nth image data according to a fixed gain. The fixed gain is greater than the plurality of compensation gains. K and N are integers, and K is more than 1 and less than N. The source driver generates 1 st to Nth driving voltage groups according to the adjusted 1 st to Nth picture data. The source driver responds to the adjustment pulse inverted polarity control signal and adjusts the polarities of the 1 st to Nth driving voltage groups according to the inverted polarity control signal.

Description

Display device and operation method thereof

Technical Field

The present invention relates to a display technology, and more particularly, to a display device and an operating method thereof.

Background

In general, to avoid image sticking, a Liquid Crystal Display (LCD) adjusts the switching sequence of the voltage polarity of the image frame every 28 seconds. However, in the initial stage of the switching sequence of the adjustment voltage polarity, the liquid crystal display often has to first charge the same pixel in the display panel with the driving voltage of the same polarity. In this case, pixels in the display panel tend to be overcharged (over charge), which in turn causes a phenomenon of flicker (flicker) of the display panel.

For example, fig. 1 is a waveform diagram for explaining charging of pixels with different polarity and same polarity voltages. As shown in FIG. 1, the same pixel in the display panel can be turned on sequentially in response to the scan pulses P11 and P12. In addition, as shown in the upper half of fig. 1, when the liquid crystal display sequentially charges the same pixel with the positive polarity and the negative polarity driving voltage in response to the polarity control signal POL11, the voltage V11 of the pixel will not be overcharged. On the other hand, as shown in the lower half of fig. 1, when the liquid crystal display sequentially charges the same pixel with the positive driving voltage in response to the polarity control signal POL12, the voltage V12 of the pixel is too saturated to generate the voltage difference Δ V, thereby causing the display panel to flicker.

Disclosure of Invention

The invention provides a display device and an operation method thereof, which can avoid the occurrence of afterimages on image pictures and avoid the occurrence of flicker phenomenon.

The display device comprises a time schedule controller and a source electrode driver. The time schedule controller generates an adjusting pulse every other preset time and receives the 1 st to the Nth picture data in sequence within the preset time. The time schedule controller adjusts the 1 st to Kth image data according to a plurality of compensation gains and adjusts the (K +1) th to Nth image data according to a fixed gain. The fixed gain is greater than the plurality of compensation gains. K and N are integers, and K is more than 1 and less than N. The source driver generates 1 st to Nth driving voltage groups according to the adjusted 1 st to Nth picture data. The source driver responds to the adjustment pulse inverted polarity control signal and adjusts the polarities of the 1 st to Nth driving voltage groups according to the inverted polarity control signal.

The operation method of the display device of the invention comprises the following steps. Through a time schedule controller in the display device, an adjusting pulse is generated every other preset time, and the 1 st to the Nth picture data are received in sequence within the preset time. The 1 st to Kth frame data are adjusted according to the plurality of compensation gains, and the (K +1) th to Nth frame data are adjusted according to the fixed gain. The fixed gain is greater than the plurality of compensation gains. K and N are integers, and K is more than 1 and less than N. And generating 1 st to Nth driving voltage groups according to the adjusted 1 st to Nth picture data by a source driver in the display device. And responding to the adjustment pulse inversion polarity control signal, and adjusting the polarities of the 1 st to Nth driving voltage groups according to the inverted polarity control signal.

Based on the above, the display device and the operation method thereof of the present invention can adjust the 1 st to nth frame data by using the plurality of compensation gains and the fixed gain, and can adjust the polarities of the 1 st to nth driving voltage sets according to the inverted polarity control signal. Therefore, the occurrence of afterimages on the image picture can be avoided, and the occurrence of the flicker phenomenon can be avoided.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a waveform diagram for explaining charging of pixels with voltages of different polarities and the same polarity.

Fig. 2 is a block diagram of a display device according to an embodiment of the invention.

FIG. 3 is a flowchart illustrating an operation method of a display device according to an embodiment of the invention.

FIG. 4 is a signal timing diagram of a display device according to an embodiment of the invention.

Description of the reference symbols

P11, P12: scanning pulse

POL, POL11, POL 12: polarity control signal

V11, V12: voltage of

Δ V: voltage difference

200: display device

210: time sequence controller

220: source driver

230: gate driver

240: display panel

211: counting circuit

212: gain adjusting circuit

250: counter with a memory

260: distinguishing device

D1-DN: picture data

B1-BN: adjusted picture data

S21: adjusting pulses

S22: reset pulse

VR: count value

S310 to S360, S311, S312, S331, S332, S361, S362: the steps in FIG. 3

T41: the first period

T42: the second period

T43: the third period

D0: previous picture data

B0: adjusted previous picture data

G1-GK: compensating gain

GT: fixed gain

F0-FN: image picture

Detailed Description

Fig. 2 is a block diagram of a display device according to an embodiment of the invention. As shown in fig. 2, the display device 200 includes a timing controller 210, a source driver 220, a gate driver 230, and a display panel 240. In addition, the timing controller 210 includes a counting circuit 211 and a gain adjusting circuit 212, and the counting circuit 211 includes a counter 250 and a discriminator 260. The display device 200 may be, for example, a Liquid Crystal Display (LCD). The timing controller 210 is electrically connected to the source driver 220 and the gate driver 230, and the source driver 220 and the gate driver 230 are electrically connected to the display panel 240. The display device 200 can drive the display panel 240 through the source driver 220 and the gate driver 230.

In operation, the counting circuit 211 generates an adjustment pulse S21 every predetermined time (e.g., 28 seconds), and outputs the 1 st to nth frame data D₁～D_NTo the gain adjustment circuit 212. In addition, the gain adjustment circuit 212 can adjust the 1 st to Nth frame data D by using a plurality of compensation gains and fixed gains₁～D_NAnd generating the adjusted 1 st to Nth frame data B₁～B_N。

The source driver 220 can adjust the 1 st to Nth frame data B according to the adjusted frame data₁～B_NGenerating the 1 st to Nth driving voltage groups. In addition, the source driver 220 may invert the polarity control signal POL from the timing controller 210 according to the adjustment pulse S21, and may adjust the polarities of the 1 st to nth driving voltage groups according to the inverted polarity control signal POL. In other words, the display device 200 can adjust the switching sequence of the voltage polarity of the image frame according to the adjustment pulse S21.

For example, before the polarity control signal POL is inverted, the switching sequence of the voltage polarity originally corresponding to the pixel for the same pixel in the display panel 240 may be (+), (-) - … …, (+), (-), where (+) is used for representing the positive driving voltage and (-) is used for representing the negative driving voltage. In addition, after the polarity control signal POL is inverted, the switching sequence of the voltage polarity corresponding to the pixel is changed to (-), +, (+), … …, (-) -, (+). Therefore, the display panel 240 can be prevented from having residual images. In addition, the display device 200 utilizes a plurality of compensation gains and fixed gains to adjust the 1 st to Nth frame data D₁～D_NTherefore, the pixel in the display panel 240 can be prevented from being overcharged (over charge), and the phenomenon of flicker of the display panel 240 can be prevented.

Fig. 3 is a flowchart illustrating an operation method of a display device according to an embodiment of the invention, fig. 4 is a signal timing diagram of the display device according to the embodiment of the invention, and the device 200 will be further described with reference to fig. 2 to 4. In step S310, the timing controller 210 generates an adjustment pulse S21 every predetermined time (e.g., 28 seconds), i.e., every N image frames.

For example, during the first period T41, the counter 250 in the timing controller 210 can receive N previous frame data one by one, wherein D in fig. 4₀For representing the Nth previous picture data, B, of the first period T41₀Is the Nth previous frame data adjusted by the gain adjustment circuit 212, and B₀＝D₀xGT, GT is a fixed gain. In addition, the display device 200 may respond to the adjusted nth previous picture data B₀Generating an image frame F₀。

In the detailed step of step S310, as shown in step S311, the counter 250 may count the number of the N previous picture data to generate a count value VR. For example, the counter 250 increments the count value VR by 1 every time it receives one previous picture data. The discriminator 260 may receive the count value VR from the counter 250, and may discriminate whether the count value VR is equal to N. As shown in step S312, when the counting value VR is equal to N, the discriminator 260 may output the reset pulse S22 and the adjustment pulse S21 generated in the third period T43. Further, the counter 250 may reset the count value VR in response to the reset pulse S22. In other words, the counting circuit 211 can count the number of the N previous picture data to generate the counting value VR. When the count value VR is equal to N, the counting circuit 211 may generate the adjustment pulse S21 and reset the count value VR.

In step S320, the counting circuit 211 can sequentially receive N frame data, i.e. the 1 st to nth frame data D, during a second period T42₁～D_N. It is worth mentioning that the counting circuit 211 can respond to the 1 st to Nth frame data D₁～D_NThe count value VR is accumulated again. In addition, when the counting circuit 211 responds to the Nth picture data D_NWhen the counting value VR is added to NThe counter circuit 211 resets the count value VR again by resetting the adjustment pulse S21 generated in the third period T43. The two adjustment pulses S21 are separated by a predetermined time (e.g., 28 seconds). In other words, the counting circuit 211 can receive the 1 st to Nth frame data D sequentially within a predetermined time₁～D_N。

In step S330, the timing controller 210 can adjust the 1 st to the kth frame data D according to the plurality of compensation gains₁～D_KAnd adjusting the (K +1) th to Nth frame data D according to the fixed gain GT_K+1～D_N. Wherein the fixed gain GT is greater than the plurality of compensation gains, K and N are integers, and K is greater than 1 and less than N.

For example, the gain adjustment circuit 212 may generate the fixed gain GT and the 1 st to Kth compensation gains G of the plurality of compensation gains in response to the adjustment pulse S21₁～G_K. In detail in step S330, as shown in step S331, the gain adjustment circuit 212 can adjust the gain G according to the 1 st compensation gain₁Adjust the 1 st picture data D₁. For example, the gain adjustment circuit 212 can adjust the 1 st picture data D₁Multiplying by the 1 st compensation gain G₁To generate the adjusted 1 st frame data B₁. That is, B₁＝D₁xG₁. Similarly, the gain adjustment circuit 212 can adjust the 2 nd frame data D₂Multiplying by the 2 nd compensation gain G₂To generate the adjusted 2 nd picture data B₂. That is, B₂＝D₂xG₂. By analogy, the gain adjustment circuit 212 can adjust the Kth frame data D_KMultiplying by the Kth compensation gain G_KTo generate adjusted Kth picture data B_K. That is, B_K＝D_KxG_K。

In other words, the timing controller 210 can multiply the ith picture data by the ith compensation gain to generate the adjusted ith picture data, wherein i is an integer and 1 ≦ i ≦ K. In addition, the (j +1) th compensation gain is larger than the jth compensation gain, j is an integer and 1 ≦ j ≦ (K-1). That is, G₁<G₂<……<G_KAnd compensate for the gain G₁～G_KMay for example be respectively smaller than 1. In other words, the timing controller 210 can utilize K compensation gains G₁～G_KReducing K picture data D₁～D_KThe gradation value of each of the plurality of pixel data. In addition, the timing controller 210 may compensate the gain G by K gradually increasing₁～G_KGradually decrease the K picture data D₁～D_KThe falling amplitude of the gradation value of (1).

In step S332, the gain adjustment circuit 212 can adjust the (K +1) th to Nth frame data D according to the fixed gain GT_K+1～D_N. For example, the gain adjustment circuit 212 may adjust the (K +1) th picture data D_K+1Multiplying by a fixed gain GT to generate adjusted (K +1) th picture data B_K+1. That is, B_K+1＝D_K+1xGT are provided. By analogy, the gain adjustment circuit 212 can adjust the Nth frame data D_NMultiplying by a fixed gain GT to generate adjusted Nth picture data B_N. That is, B_N＝D_NxGT are provided. In other words, the timing controller 210 can convert the (K +1) th to Nth frame data D_K+1～D_NMultiplying by a fixed gain GT to generate adjusted (K +1) th to Nth picture data B_K+1～B_N. Wherein the fixed gain GT may for example be equal to 1. In other words, from the (K +1) th picture data D_K+1First to Nth picture data D_NThe timing controller 210 will not decrease the gray level of each frame data.

In step S340, the source driver 220 can adjust the first to nth frame data B according to the adjusted first to nth frame data B₁～B_NGenerating 1 st to nth driving voltage groups, wherein the 1 st to nth driving voltage groups each include a plurality of driving voltages. In addition, as shown in steps S350 and S360, the source driver 220 may invert the polarity control signal POL from the timing controller 210 in response to the adjustment pulse S21 of the second period T42, and the source driver 220 may adjust the polarities of the 1 st to nth driving voltage groups according to the inverted polarity control signal POL. In addition, as for the details of steps S361 and S362 of step S360, the source driver 220 can depend on the reversed polarityThe control signal POL stops inverting the polarity of the 1 st driving voltage group, and the source driver 220 can invert the polarities of the 2 nd to nth driving voltage groups one by one according to the inverted polarity control signal POL.

For example, the source driver 220 can adjust the 1 st frame data B according to the adjusted frame data B₁The 1 st driving voltage group is generated. The display device 200 can drive the display panel 240 by using a plurality of driving voltages in the 1 st driving voltage group, so that the display panel 240 can generate the 1 st image frame F₁. Since the source driver 220 stops inverting the polarity of the 1 st driving voltage group, the 1 st image frame F₁And the previous image frame F₀The polarity distributions of the corresponding driving voltages are the same. For example, the embodiment of FIG. 4 is a dot inversion (dot inversion) image F₀～F_NThe polarity distribution of the corresponding driving voltage.

Similarly, the source driver 220 can adjust the second frame data B according to the adjusted second frame data B₂Generate the 2 nd driving voltage set so that the display panel 240 can generate the 2 nd image frame F₂. By analogy, the display panel 240 may respond to the adjusted 3 rd to nth picture data B₃～B_NGenerating the 3 rd to Nth image frames F₃～F_N. Since the source driver 220 can invert the polarities of the 2 nd to nth driving voltage sets one by one according to the inverted polarity control signal POL, N image frames F are displayed during the second period T42₁～F_NThe polarity distributions of the driving voltages corresponding to any two adjacent image frames are different.

Specifically, the display device 200 can adjust the switching sequence of the voltage polarity of the image frame according to the adjustment pulse S21 every predetermined time (e.g., 28 seconds). In addition, every time the display device 200 adjusts the switching order of the voltage polarities of the video pictures in response to the adjustment pulse S21, the 1 st video picture F following the adjustment pulse S21₁Will stop inverting, thereby causing the display device 200 to utilize the previous image frame F₀The display panel 240 is driven by the same polarity of the driving voltage.

To avoid the flicker phenomenon of the display panel 240, the display device 200 may first use K compensation gains G₁～G_KTo reduce the previous K picture data D₁～D_KAnd the K picture data D₁～D_KThe adjustment range of the gray value can follow K compensation gains G₁～G_KIs gradually decreased. Thereafter, the display device 200 may maintain or not change the subsequent (N-K) pieces of screen data D by using the fixed gain GT_K+1～D_NThe gray value of (a). Thereby, following the 1 st frame data D₁The adjustment and reduction of the gray-level value can prevent the pixels in the display panel 240 from being overcharged under the charging of the driving voltage with the same polarity, and further prevent the display panel 240 from flickering. Further, with the K pieces of picture data D₁～D_KThe gradual decrease of the adjustment range can cause the display panel 240 to generate stable brightness, and can also avoid the display panel 240 from flickering.

In summary, the timing controller in the display device of the present invention can adjust the frame data by using the plurality of compensation gains and the fixed gain, and can generate an adjustment pulse every other predetermined time. The source driver can respond to the adjusting pulse inversion polarity control signal and can adjust the polarity of the driving voltage group according to the inverted polarity control signal. Therefore, the display device can adjust the switching sequence of the voltage polarity of the image picture once every preset time, and further can prevent the image picture from generating residual images. In addition, the flicker phenomenon of the display panel can be avoided by adjusting the picture data through the time schedule controller.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A display device, comprising:

a time schedule controller, which generates an adjusting pulse every a preset time and receives a 1 st to an Nth image data in sequence in the preset time, the time schedule controller adjusts the 1 st to the Kth image data according to a plurality of compensation gains and adjusts the (K +1) th to the Nth image data according to a fixed gain, the fixed gain is larger than the plurality of compensation gains, wherein K and N are integers, and K is more than 1 and less than N; and

and the source driver generates a 1 st to Nth driving voltage group according to the adjusted 1 st to Nth picture data, responds to the adjusting pulse and inverts a polarity control signal, and adjusts the polarity of the 1 st to Nth driving voltage groups according to the inverted polarity control signal.

2. The display device as set forth in claim 1,

the time schedule controller multiplies the ith picture data by the ith compensation gain to generate the adjusted ith picture data, and the time schedule controller multiplies the (K +1) th to Nth picture data by the fixed gain respectively to generate the adjusted (K +1) th to Nth picture data, wherein the (j +1) th compensation gain is greater than the jth compensation gain, i is an integer and is not less than 1 and not more than K, and j is an integer and is not less than 1 and not more than j and not more than K-1.

3. The display device as set forth in claim 1,

the source driver stops inverting the polarity of the 1 st driving voltage group according to the inverted polarity control signal, and inverts the polarities of the 2 nd to Nth driving voltage groups one by one according to the inverted polarity control signal.

4. The display device of claim 3, wherein the timing controller comprises:

a counting circuit, counting the number of N previous frame data to generate a counting value, and when the counting value is equal to N, the counting circuit generates the adjusting pulse and resets the counting value; and

a gain adjustment circuit, responding to the adjustment pulse to generate the fixed gain and the 1 st to Kth compensation gains in the plurality of compensation gains, and the gain adjustment circuit adjusts the ith picture data according to the ith compensation gain and adjusts the (K +1) th to Nth picture data according to the fixed gain, wherein the (j +1) th compensation gain is larger than the jth compensation gain, i is an integer and is not less than 1 and not more than K, j is an integer and is not less than 1 and not more than j and not more than (K-1).

5. The display device of claim 4, wherein the counting circuit comprises:

a counter for counting the number of the N previous image data and generating the count value accordingly; and

and a discriminator for discriminating whether the count value is equal to N, and outputting the adjustment pulse and generating a reset pulse to cause the counter to reset the count value when the count value is equal to N.

6. The display device of claim 1, further comprising:

a display panel electrically connected to the source driver; and

and the grid driver is electrically connected with the display panel, and the display device drives the display panel through the source driver and the grid driver.

7. A method of operating a display device, comprising:

generating an adjusting pulse every other a preset time through a time sequence controller in the display device, and sequentially receiving 1 st to Nth picture data within the preset time;

adjusting the 1 st to Kth frame data according to a plurality of compensation gains, and adjusting the (K +1) th to Nth frame data according to a fixed gain, wherein the fixed gain is larger than the plurality of compensation gains, K and N are integers, and K is more than 1 and less than N:

generating a 1 st to an Nth driving voltage group according to the adjusted 1 st to Nth picture data through a source driver in the display device; and

and inverting a polarity control signal in response to the adjustment pulse, and adjusting the polarities of the 1 st to Nth driving voltage groups according to the inverted polarity control signal.

8. The method as claimed in claim 7, wherein the plurality of compensation gains include 1 st to Kth compensation gains, and the steps of adjusting the 1 st to Kth frame data according to the plurality of compensation gains and adjusting the (K +1) th to Nth frame data according to the constant gain comprise:

multiplying the ith picture data by the ith compensation gain to generate the adjusted ith picture data, wherein the (j +1) th compensation gain is greater than the jth compensation gain, i is an integer and is not less than 1 and not more than K, j is an integer and is not less than 1 and not more than j and not more than K-1; and

multiplying the (K +1) th to Nth frame data by the fixed gain to generate the adjusted (K +1) th to Nth frame data.

9. The method as claimed in claim 8, wherein the 1 st to Kth compensation gains are respectively less than 1.

10. The method of claim 9, wherein the fixed gain is equal to 1.

11. The method according to claim 8, wherein the step of adjusting the polarities of the 1 st to nth driving voltage sets according to the inverted polarity control signal comprises:

stopping inverting the polarity of the 1 st driving voltage group according to the inverted polarity control signal; and

and reversing the polarities of the 2 nd to Nth driving voltage groups one by one according to the inverted polarity control signal.

12. The method as claimed in claim 11, wherein the step of generating the adjustment pulse every the predetermined time comprises:

counting the number of N previous frame data to generate a count value; and

when the count value is equal to N, the adjustment pulse is generated and the count value is reset.