KR102612038B1 - Liquid crystal display and method of driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of improving afterimages and a driving method thereof. The liquid crystal display device and its driving method according to the present invention are N (where N is a natural number greater than 2) to which data voltages of the same polarity are supplied. ) Additional frames are periodically inserted between the multiple frame and the (N multiple + 1) frame. The additional data voltage supplied to the data line during the additional frame period has an opposite polarity to the data voltage supplied to the data line during the N-th frame period. Accordingly, the present invention can improve display quality by preventing afterimages and flicker by periodically reversing the polarity of the voltage charged to the liquid crystal cell.

Description

Liquid crystal display device and driving method thereof {LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME}

The present invention relates to a liquid crystal display device and a driving method thereof, and particularly to a liquid crystal display device capable of improving afterimages and a driving method thereof.

Video display devices, which display various information on a screen, are a core technology of the information and communication era and are developing into thinner, lighter, more portable, and higher performance. Accordingly, flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes (CRTs), are receiving attention.

Among flat display devices, a liquid crystal display displays an image by adjusting the light transmittance of liquid crystal cells according to a video signal. For this purpose, the liquid crystal display device includes a plurality of liquid crystal cells and a thin film transistor connected to each of the plurality of liquid crystal cells.

To prevent deterioration of the liquid crystal display, such liquid crystal display devices are driven by an inversion method that inverts the polarity of the data voltage with respect to the common voltage on a frame-by-frame, line-by-line, or sub-pixel (dot) basis. However, if one of the two polarities of the data voltage is supplied biased for a long time, flicker and direct current afterimages appear due to a shift in the common voltage.

In particular, when the same image is moved or scrolled at a constant speed, voltage of the same polarity is repeatedly accumulated depending on the correlation between the size of the scrolled image and the scroll speed (movement speed), resulting in a direct current afterimage. Not only does the display quality of moving images deteriorate due to these direct current afterimages, but there is also a problem in that the display quality deteriorates due to the flicker phenomenon in which differences in luminance are periodically felt by the naked eye.

The present invention is intended to solve the above problems, and the present invention provides a liquid crystal display device that can improve afterimages and a method of driving the same.

In order to achieve the above object, the liquid crystal display device and its driving method according to the present invention include the N-th frame (where N is a natural number greater than 2) multiple of which a data voltage of the same polarity is supplied, and the (N multiple + 1)-th frame. Additional frames are periodically inserted between frames. The additional data voltage supplied to the data line during the additional frame period has an opposite polarity to the data voltage supplied to the data line during the N-th frame period.

The present invention inserts an additional frame in which an additional data voltage of the opposite polarity to the N-th multiple frame is supplied between the N-th multiple frame and the N-th multiple + 1-th frame in which the data voltage of the same polarity is supplied. Accordingly, the present invention can improve display quality by preventing afterimages and flicker by periodically reversing the polarity of the voltage charged to the liquid crystal cell.

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a block diagram specifically illustrating the timing controller shown in FIG. 1.
FIG. 3 is a waveform diagram for explaining the scan pulse generated by the gate driver shown in FIG. 1.
Figure 4 is a waveform diagram showing a data voltage and an additional data voltage according to a polarity modulation signal applied to a liquid crystal display device according to an embodiment of the present invention.
Figure 5 is a diagram showing the frame polarity of each frame in the method of driving a liquid crystal display device according to an embodiment of the present invention.
Figure 6 is a flowchart for step-by-step explaining a method of driving a liquid crystal display device according to an embodiment of the present invention.
FIGS. 7A and 7B are diagrams for comparing and explaining the image quality of a conventional liquid crystal display device and a liquid crystal display device according to the present invention.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings.

1 is a cross-sectional view showing a liquid crystal display device according to the present invention.

The liquid crystal display device shown in FIG. 1 includes a liquid crystal display panel 100, a panel driver including a data driver 108 and a gate driver 106 that drives the liquid crystal display panel 100, and a timing device that controls the panel driver. A controller 110 is provided.

The liquid crystal display panel 110 displays images through a pixel matrix in which multiple pixels are arranged. Each pixel implements the desired color through a combination of red (R), green (G), and blue (B) sub-pixels that adjust light transmittance by varying the liquid crystal array according to the data signal. Each subpixel includes a thin film transistor (TFT) connected to the gate line (GL) and data line (DL), a liquid crystal cell (Clc) connected in parallel with the thin film transistor (TFT), and a storage capacitor (Cst). The liquid crystal cell (Clc) charges the difference voltage between the data signal supplied to the pixel electrode through a thin film transistor (TFT) and the common voltage (Vcom) supplied to the common electrode, and drives the liquid crystal according to the charged voltage to increase light transmittance. Adjust. The storage capacitor (Cst) keeps the voltage charged in the liquid crystal cell (Clc) stable.

The timing controller 110 inserts an additional frame between the N-th frame and the (N-multiple + 1)-th frame, in which data of the same polarity is supplied, and generates additional data whose polarity is opposite to the data of the N-th multiple frame. , the additional data is supplied to the data driver 108 during the additional frame period. For this purpose, the timing controller 110 includes a periodic signal generator 120, a control signal generator 130, and a data alignment portion 140, as shown in FIG. 2.

The periodic signal generator 120 counts the frame period by counting the data enable signal DE. Since the data enable signal (DE) is generated in a cycle of one horizontal period, when the count value of the data enable signal (DE) accumulates as much as the number of lines of the liquid crystal display panel 100, the count value of the frame period is increased to extend the frame period. Count. Accordingly, the periodic signal generator 120 generates the first periodic signal C1 at the N-th frame period, and generates the first periodic signal C1 at a time delayed by 2/3 frame period from the time the first periodic signal C1 is generated. The second periodic signal C2 is generated, and the first periodic signal C1 is generated at a time delayed by 2/3 frame period from the time the second periodic signal C2 is generated.

The control signal generator 130 includes first and second control signal generators 132 and 134, a control signal selector 136, and a polarity modulator 138.

The first control signal generator 132 generates a main gate control signal (GCS) and a data control signal (DCS) using reference timing signals (Hsync, Vsync, DE, CLK) based on the first frame frequency input from the system. Create. For example, the main gate control signal (GCS) and data control signal (DCS) are generated based on the first frame frequency of 60Hz.

The second control signal generator 134 multiplies the reference timing signal input from the system by times i (where i is an integer greater than 1 and less than 2), and multiplies the reference timing signal with the second frame frequency higher than the first frame frequency. A synchronized gate control signal (GCS') and a data control signal (DCS') are generated using the timing signal. For example, the double-speed gate control signal (GCS') and data control signal (DCS') are generated based on the second frame frequency of 75 to 120 Hz.

The control signal selection unit 136 operates the second control signal generator 134 during the N-th multiple frame, additional frame, and N-th multiple + 1 frame period in response to the first and second periodic signals C1 and C2. The double-speed gate control signal (GCS') and data control signal (DCS') generated in are supplied to the gate driver 106 and the data driver 108. In addition, the control signal selection unit 136 generates the main gate control signal ( GCS) and data control signal (DCS) are supplied to the gate driver 106 and data driver 108.

As shown in FIG. 3, the polarity modulator 138 inverts the polarity control signal POL in response to the second period signal C2, so that the polarity of the additional data voltage is opposite to the data voltage of the N-th frame period. It generates a polarity modulation signal (POL') that causes polarity. The polarity modulation signal (POL') has its polarity reversed on a frame-by-frame basis during the frame period driven at a first frame frequency of 60 Hz, and the N-th multiple frame and additional frame (A Frame) driven at a second frame frequency of 75 to 120 Hz. ) and the polarity is reversed on a frame-by-frame basis during the N-th multiple + 1-th frame period.

The data sorting unit 140 includes an additional data generating unit 142 and a data selecting unit 144.

The additional data generator 142 consists of a frame memory that stores data of the N-th frame. The data of the N-th frame stored in this frame memory is used as additional digital data (ADATA) supplied to an additional frame (A Frame) periodically inserted between the N-th frame and the (N multiple + 1)-th frame.

The data selection unit 144 outputs the additional digital data (ADATA) of the additional data generator 142 during the additional frame (A Frame) in response to the second periodic signal (C2) and supplies it to the data driver 108. , input digital video data (DATA) is output and supplied to the data driver 108 during other frame periods excluding the additional frame period (A Frame).

The gate driver 106 sequentially drives the gate lines GL of the display panel 100 in response to gate control signals GCS and GCS' from the timing controller 110. The gate driver 106 supplies a scan pulse of the gate-on voltage during each scan period of each gate line GL, and supplies a gate-off voltage during the remaining period during which the gate line GL is driven. In particular, as shown in FIG. 4, the gate driver 106 operates at the remaining frame periods excluding the N-th multiple frame, additional frame (A Frame), and N-th multiple + 1 frame period, that is, at the first frame frequency of 60 Hz. During the driving period, a scan pulse of a high gate-on voltage is supplied for each scan period of each gate line (GL) using the main gate control signal (GCS). In addition, the gate driver 106 operates the gate control signal (GCS') during the N-th frame, additional frame (A Frame), and N-th multiple + 1 frame periods, that is, a period driven at a second frame frequency of 90 Hz. ) is used to supply a scan pulse of the gate-on voltage for each scan period of each gate line (GL). At this time, since the period of driving at the second frame frequency is shorter than the period of driving at the first frame frequency, the high period during which the gate-on voltage of the scan pulse is supplied during the period of driving at the second frame frequency is the period of driving at the first frame frequency. It is shorter than the high period of the scan pulse during the period driven by the frequency.

The data driver 108 converts digital data from the timing controller 110 into an analog data voltage in response to the data control signals (DCS, DCS') from the timing controller 110 to drive each gate line (GL). It is supplied through the data line (DL) every time. In particular, as shown in FIG. 3, the data driver 108 is driven at the first frame frequency, that is, the remaining frame periods excluding the N-th frame, the additional frame (A Frame), and the N-th multiple + 1-th frame period. During this period, data voltages (D+, D-) whose polarity is inverted on a frame-by-frame basis according to the polarity modulation signal (POL') are supplied to the data line (DL). Additionally, the data driver 108 inverts its polarity on a frame-by-frame basis according to the polarity modulation signal (POL') during the period of driving at the second frame frequency, which is the N-th frame, additional frame, and N-th multiple + 1 frame period. The data voltage (D+, D-) of the N-th multiple frame, the additional data voltage (A-, A+) of the additional frame (A Frame), and the data voltage (D-, D+) of the N-th multiple + 1 frame. It is supplied sequentially to the data line (DL). That is, the additional data voltages (A-, A+) have the opposite polarity to the polarity of the data voltages (D+, D-) of the N-th frame.

As such, the present invention supplies additional data voltages (+A, -A) of opposite polarity to the N-th multiple frame between the N-th multiple frame and the N-th multiple + 1 frame, to which data voltages of the same polarity are supplied. Insert an additional frame (A Frame). Accordingly, in the present invention, as shown in FIG. 5, the polarity of the voltage charged to the liquid crystal cell is reversed on a frame-by-frame basis, thereby preventing any one polarity of the data voltage from being supplied biased for a long time. In particular, the present invention can prevent direct current afterimages that appear due to accumulation of voltages of the same polarity by periodically (frame by frame) inverting the polarity of the voltage charged in the liquid crystal cell in scroll data in which symbols or characters move at a constant speed. there is.

Figure 6 is a flowchart for explaining a method of driving a liquid crystal display device according to the present invention. In Figure 6, the first frame frequency is 60Hz and the second frame frequency is 90Hz. This is only an example and is not limiting.

As shown in FIG. 6, the frame period is counted by counting the reference timing signal (eg, DE) input together with the digital video data (step S11).

If the current frame period is not the N times frame period and the N times + 1 frame period (step S12), the frame frequency of the remaining frame periods excluding the N times frame period, additional frame period, and N times + 1 frame period is changed. Keep it at 60Hz. Then, the polarity of the data voltage charged in the liquid crystal cell is inverted on a frame-by-frame basis during the remaining frame periods excluding the N-th frame period, the additional frame period, and the N-th + 1 frame period (step S13).

If the current frame period is the N times frame period (step S12), the frame frequency in the N times frame period and the N times + 1 frame period is increased to 90 Hz to create the N times frame period and the N times + 1 frame period. An additional frame (A Frame) period is inserted in between (step S14). Additionally, the polarity of the additional data voltage supplied to the liquid crystal cells during the additional frame period is controlled to be opposite to the N-th frame period. Accordingly, the polarity of the data voltage charged in the liquid crystal cell during the N-th frame period, the additional frame period, and the N-th + 1 frame period is reversed on a frame-by-frame basis.

FIGS. 7A and 7B are diagrams for comparing and explaining the image quality of a conventional liquid crystal display device and a liquid crystal display device according to the present invention.

In a conventional liquid crystal display device, as shown in FIG. 7A, data voltages of the same polarity are supplied during the N-th frame and the N-th + 1 frame period. Accordingly, in a conventional liquid crystal display device, one of the two polarities of the data voltage is supplied dominantly for a long time, and the common voltage is shifted along the dominant polarity. Due to this shift in the common voltage, the charging amount of the positive data voltage and the negative data voltage changes, resulting in a flicker defect. On the other hand, as shown in FIG. 7B, the liquid crystal display device of the present invention has a display device with a polarity opposite to the data voltage supplied to the frame between the N-th frame and the N-th + 1 frame to which a data voltage of the same polarity is supplied. Insert an additional frame (A Frame) to which additional data voltage is supplied. Accordingly, the present invention can prevent a shift in the common voltage by periodically reversing the polarity of the voltage charged in the liquid crystal cell, thereby preventing flicker defects.

Meanwhile, in the present invention, the periodic signal generator 120, the additional data generator 142, the polarity modulator 138, etc. are described as an example built into the timing controller 110, but in addition, the timing controller 110 and It can also be implemented as a separate driving chip.

The above description is merely an exemplary description of the present invention, and various modifications may be made by those skilled in the art without departing from the technical spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention do not limit the present invention. The scope of the present invention should be interpreted in accordance with the scope of the patent claims below, and all technologies within the equivalent scope thereof should be interpreted as being included in the scope of the present invention.

100: liquid crystal display panel 106: gate driver
108: data driver 110: timing controller
120: periodic signal generator 130: control signal generator
138: polarity modulation unit 140: data alignment unit

Claims (10)

Additional data that generates additional data supplied to additional frames that are periodically inserted between the N multiple (where N is a natural number greater than 2) frame, to which a data voltage of the same polarity is supplied, and the (N multiple + 1) frame. A creation department;
A data driver converts the additional data into an analog additional data voltage and supplies it to a data line,
The additional data voltage supplied to the data line has an opposite polarity to the data voltage supplied to the data line during the N-th frame period,
A liquid crystal display device in which the frame frequency changes when inserting the additional frame compared to the previous one. According to claim 1,
The additional data generator is a frame memory that stores data of the N-th frame used as the additional data. According to claim 1,
The frame frequencies of the N multiple frame, the additional frame, and the (N multiple + 1) frame period are the same,
The frame frequencies of the remaining frame periods excluding the N-th frame, the additional frame, and the (N-multiple + 1)-th frame period are the N-th frame, the additional frame, and the (N multiple + 1)-th frame period. A liquid crystal display device with a lower frame frequency during the second frame period. According to claim 1,
The frame period is counted and a first period signal is generated when the N-th frame period becomes multiple, and a second period signal is generated at a time delayed by 2/3 frame period from the time the first period signal is generated, and the The liquid crystal display device further includes a periodic signal generator that generates the first periodic signal at a time delayed by 2/3 frame period from the time the second periodic signal is generated. According to claim 4,
The liquid crystal display device further includes a polarity modulator that inverts a polarity control signal that controls the polarities of the data voltage and the additional data voltage in response to the second periodic signal. According to claim 5,
a first control signal generator that generates a main control signal supplied to the N-th frame, the additional frame, and the remaining frame periods excluding the (N-multiple+1)-th frame period;
Further comprising a second control signal generator that generates a speed control signal supplied during the N-th frame, the additional frame, and the (N-multiple + 1)-th frame period,
The main control signal is generated using a reference timing signal input from the system,
The liquid crystal display device wherein the double speed control signal is generated by multiplying the reference timing signal by i (where i is an integer greater than 1 and less than 2) and using the doubled timing signal. According to claim 6,
a gate driver generating scan pulses in response to the main control signal and the double speed control signal;
a timing controller that controls the gate driver and the data driver;
Further comprising a liquid crystal display panel having a gate line to which the scan pulse is supplied and a data line to which the additional data voltage is supplied,
At least one of the additional data generator, the polarity modulator, and the periodic signal generator is built into the timing controller. According to claim 7,
The high logic period of the scan pulse supplied in the N-th frame, the additional frame, and the (N multiple + 1)-th frame period is the N-th frame, the additional frame, and the (N multiple + 1)-th frame period. A liquid crystal display device that is shorter than the high logic period of the scan pulse supplied in the remaining frame periods except the )th frame period. Generating additional data to be supplied to additional frames periodically inserted between the N-th frame (where N is a natural number greater than 2) to which a data voltage of the same polarity is supplied and the (N multiple + 1)-th frame; ;
Converting the additional data into an analog additional data voltage and supplying it to a data line,
The additional data voltage supplied to the data line has an opposite polarity to the data voltage supplied to the data line during the N-th frame period,
A method of driving a liquid crystal display device in which the frame frequency changes when inserting the additional frame. According to clause 9,
A method of driving a liquid crystal display device in which a data voltage whose polarity is reversed on a frame-by-frame basis is supplied to the data line for the remaining frame periods excluding the N-th frame, the additional frame, and the (N-multiple+1)-th frame period. .

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