CN109962109B - 半导体器件及该半导体器件的制造方法 - Google Patents

半导体器件及该半导体器件的制造方法 Download PDF

Info

Publication number
CN109962109B
CN109962109B CN201810590251.8A CN201810590251A CN109962109B CN 109962109 B CN109962109 B CN 109962109B CN 201810590251 A CN201810590251 A CN 201810590251A CN 109962109 B CN109962109 B CN 109962109B
Authority
CN
China
Prior art keywords
type region
trench
type
insulating layer
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810590251.8A
Other languages
English (en)
Other versions
CN109962109A (zh
Inventor
千大焕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hyundai Motor Co
Kia Corp
Original Assignee
Hyundai Motor Co
Kia Motors Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Motor Co, Kia Motors Corp filed Critical Hyundai Motor Co
Publication of CN109962109A publication Critical patent/CN109962109A/zh
Application granted granted Critical
Publication of CN109962109B publication Critical patent/CN109962109B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0882—Disposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thyristors (AREA)

Abstract

本发明提供一种半导体器件，该半导体器件包括：n‑型层，设置在衬底的第一表面上；沟槽、n型区和p+型区，设置在n‑型层上；p型区，设置在n型区上；n+型区，设置在p型区上；栅绝缘层，设置在沟槽中；栅电极，设置在栅绝缘层上；源电极，设置在绝缘层、n+型区和p+型区上，该绝缘层设置在栅电极上；以及漏电极，设置在衬底的第二表面上。n型区包括第一部分和第二部分，第一部分与沟槽的侧表面接触并且平行于衬底的上表面延伸，第二部分与第一部分接触、与沟槽的侧表面隔开并且垂直于衬底的上表面延伸。

Description

半导体器件及该半导体器件的制造方法
相关申请的交叉引用
本申请要求2017年12月14日提交的申请号为10-2017-0172298的韩国专利申请的优先权和权益，该韩国专利申请的全部内容通过引用并入本文。
技术领域
本发明涉及一种半导体器件及该半导体器件的制造方法，并且更特别地，涉及一种改善半导体器件的性能指数的半导体器件及该半导体器件的制造方法。
背景技术
功率半导体器件需要低导通电阻或低饱和电压以在大量电流流动的同时降低导通状态下的功率损耗。此外，需要可以承受在断开状态或开关断开时施加到功率半导体器件的两端的反向高电压的特性，即高击穿电压特性。
形成功率半导体器件的原材料的外延层区或漂移区的浓度和厚度基于电力系统所需的额定电压来确定。根据泊松方程(Poisson equation)，由于需要功率半导体器件的击穿电压高，因此需要外延层区或漂移区浓度低且厚度大，从而导通电阻增加且前向电流密度减小。
本部分中公开的以上信息仅用于增强对本发明的背景的理解，因此可能包含不构成本领域技术人员已知的现有技术的信息。
发明内容
本发明改善半导体器件的特性。根据本发明的示例性实施例的半导体器件可以包括：n-型层，设置在衬底的第一表面上；沟槽、n型区和p+型区，设置在n-型层上；p型区，设置在n型区上；n+型区，设置在p型区上；栅绝缘层，设置在沟槽中；栅电极，设置在栅绝缘层上；绝缘层，设置在栅电极上；源电极，设置在绝缘层、n+型区和p+型区上；以及漏电极，设置在衬底的第二表面上，其中n型区包括第一部分和第二部分，第一部分与沟槽的侧表面接触并且平行于衬底的上表面延伸，第二部分与第一部分接触、与沟槽的侧表面隔开并且在垂直于衬底的上表面的方向上延伸。
第一部分的深度可以小于沟槽的深度，并且第二部分的深度可以大于沟槽的深度。p+型区的深度可以大于沟槽的深度。p+型区的深度可以大于第二部分的深度。n型区、p型区和n+型区可以设置在p+型区与沟槽的侧表面之间。
第二部分可以与第一部分的侧表面接触，并且第二部分的离子掺杂浓度可以大于第一部分的离子掺杂浓度。第二部分可以与第一部分的下表面接触，并且第二部分的离子掺杂浓度可以小于第一部分的离子掺杂浓度。第一部分可以与p+型区接触。
根据本发明的示例性实施例的半导体器件的制造方法可以包括：在衬底的第一表面上顺序地形成n-型层、初步n型区、p型区和n+型区；蚀刻n+型区、p型区、初步n型区和n-型层以形成沟槽；在沟槽中形成初步栅绝缘层；在初步栅绝缘层上形成栅电极；在栅电极上形成初步绝缘层；在n-型层上形成p+型区；蚀刻初步栅绝缘层和初步绝缘层以形成栅绝缘层和绝缘层；在n-型层上形成n型区的第二部分；在绝缘层、n+型区和p+型区上形成源电极；以及在衬底的第二表面上形成漏电极。进一步地，在形成p+型区时，初步n型区变成n型区的第一部分，n型区的第一部分与沟槽的侧表面接触并平行于衬底的上表面延伸，并且n型区的第二部分与第一部分接触、与沟槽的侧表面隔开并且在垂直于衬底的上表面的方向上延伸。
形成p+型区可以包括使用初步绝缘层作为掩模将p型离子注入到n-型层的上表面。此外，形成n型区的第二部分可以包括使用绝缘层作为掩模将n型离子注入到n+型区和p+型区的上表面。
如上所述，根据本发明的示例性实施例，可以改善包括所有击穿电压和导通电阻特性的半导体器件的性能指数。
附图说明
根据以下结合附图的具体实施方式，本发明的以上和其它目的、特征及其它优点将被更清楚地理解，其中：
图1是根据本发明的示例性实施例的半导体器件的截面图；
图2至图8是根据本发明的示例性实施例的方法制造的半导体器件的截面图；以及
图9是根据本发明的另一示例性实施例的半导体器件的截面图。
附图标记
100：衬底                200：n-型层
250：沟槽                300：p型区
400：n+型区              500：p+型区
600：栅绝缘层            600a：初步栅绝缘层
650：绝缘层              650a：初步绝缘层
700：栅电极              800：n型区
810：第一部分            820：第二部分
910：源电极              920：漏电极
具体实施方式
本文使用的术语仅用于描述特定实施例，并不旨在限制本发明。如本文使用的，单数形式“一”、“一个”和“该”也旨在包括复数形式，除非上下文另有清楚地指示。将进一步理解的是，术语“包括”和/或“包括有”在本说明书中使用时说明所述特征、整体、步骤、操作、元件和/或部件的存在，但是不排除一个或多个其它特征、整体、步骤、操作、元件、部件和/或其组的存在或添加。如本文使用的，术语“和/或”包括一个或多个相关所列项目的任何和所有组合。
除非从上下文中明确地说明或显而易见，否则如本文使用的，术语“约”被理解为在本领域的正常公差范围内，例如，在平均值的2个标准差内。“约”可被理解为在所述值的10％、9％、8％、7％、6％、5％、4％、3％、2％、1％、0.5％、0.1％、0.05％或0.01％内。除非从上下文中另外清楚，否则本文提供的所有数值均被术语“约”修饰。
在下文中，将参照附图详细地描述本发明的示例性实施例。如本领域技术人员将认识到，在不脱离本发明的实质或范围的情况下，所描述的示例性实施例可以以各种不同的方式来修改。相反地，提供本文引入的示例性实施例以使公开的内容完全且完整并将本发明的实质充分地传达给本领域技术人员。
在附图中，为了清楚起见，层、膜、面板、区等的厚度被夸大。将理解的是，当层被称为在另一层或衬底“上”时，该层可直接在另一层或衬底上，或者也可存在中间物。
图1是根据本发明的示例性实施例的半导体器件的截面图。参照图1，根据本示例性实施例的半导体器件可包括衬底100、n-型层200、p型区300、n+型区400、p+型区500、栅电极700、n型区800、源电极910以及漏电极920。
衬底100可以是n+型碳化硅衬底。n-型层200可以设置在衬底100的第一表面上。沟槽250、p+型区500和n型区800可以设置在n-型层200上。p型区300可以设置在n型区800上。n+型区400可以设置在p型区300上。p+型区500可以与沟槽250的侧表面隔开，并且n型区800、p型区300和n+型区400可以邻近沟槽250的侧表面设置。换言之，n型区800、p型区300和n+型区400可以设置在p+型区500与沟槽250的侧表面之间。
p+型区500的离子掺杂浓度可以大于p型区300的离子掺杂浓度。n型区800的离子掺杂浓度可以大于n-型层200的离子掺杂浓度并小于n+型区400的离子掺杂浓度。p+型区500的深度L2可以大于沟槽250的深度L1。因此，在半导体器件的断开状态下，可以防止电场集中在沟槽250的下部。特别地，沟槽250的深度L1指的是沟槽250的上表面与沟槽250的下表面之间的垂直距离。p+型区500的深度L2指的是沟槽250的上表面的延长线与p+型区500的下表面之间的垂直距离。
n型区800可以包括第一部分810和第二部分820。第一部分810的第一侧可以设置成与沟槽250的侧表面接触并且可以平行于衬底100的上表面延伸。第二部分820可以与第一部分810的第二侧接触并且可以在垂直于衬底100的上表面的方向上延伸。第二部分820可以与沟槽250的侧表面隔开并且可以邻近p+型区500设置。
进一步地，第一部分810的深度L3可以小于沟槽250的深度L1并且第二部分820的深度L4可以大于沟槽250的深度L1。此外，第二部分820的深度L4可以小于p+型区500的深度L2。因此，电流的路径可以在半导体器件的导通状态下分散并且p+型区500与沟槽250之间的耗尽层的形成可以被抑制，因此在半导体器件的导通状态下保持击穿电压的同时可以增大电流。特别地，第一部分810的深度L3指的是沟槽250的上表面的延长线与第一部分810的下表面之间的垂直距离。第二部分820的深度L4指的是沟槽250的上表面的延长线与第二部分820的下表面之间的垂直距离。第一部分810的离子掺杂浓度可以小于第二部分820的离子掺杂浓度。
栅绝缘层600可以设置在沟槽250中，并且栅电极700可以设置在栅绝缘层600上。绝缘层650可以设置在栅电极700上。进一步地，绝缘层650覆盖栅电极700。栅绝缘层600和绝缘层650可以包括二氧化硅(SiO2)，并且栅电极700可以包括多晶硅或金属。
源电极910可以设置在绝缘层650、n+型区400和p+型区500上，并且漏电极920可以设置在衬底100的第二表面上。特别地，衬底100的第二表面指与衬底100的第一表面相反的表面。源电极910和漏电极920可以包括欧姆金属。
此外，将参照表1描述根据本示例性实施例的半导体器件的特性与根据比较例1和比较例2的半导体器件的特性。根据比较例1的半导体器件是普通沟槽栅极金属氧化物半导体场效应晶体管(MOSFET)器件。根据比较例2的半导体器件是在普通沟槽栅极MOSFET器件的结构中应用深度大于沟槽的深度的p+型区的结构。
表1示出根据本示例性实施例的半导体器件与根据比较例1和比较例2的半导体器件的仿真结果。在表1中，在根据本示例性实施例的半导体器件与根据比较例的半导体器件的击穿电压相同的情况下，比较电流密度。
表1
Figure BDA0001690448210000061
参照表1可知，与根据比较例1的半导体器件相比较，根据本示例性实施例的半导体器件中的击穿电压增加318％。
此外，从表1可知，与根据比较例2的半导体器件相比较，根据本示例性实施例的半导体器件中的电流密度增加21％并且导通电阻减小19％。因此，与根据比较例2的半导体器件相比较，根据本示例性实施例的半导体器件可以减小形成相同电流的导体区域，因此可以提高器件的成品率并降低成本。
进一步地，比较包括击穿电压和导通电阻的所有特性的半导体器件的性能指数，与根据比较例1的半导体器件相比较，根据本示例性实施例的半导体器件的性能指数增加385％，而与根据比较例2的半导体器件相比较，性能指数增加16％。
将参照图2至图8以及图1描述根据本发明的示例性实施例的半导体器件的制造方法。图2至图8是根据本发明的示例性实施例的半导体器件的制造方法的截面图。
参照图2，可以制备衬底100，然后可以在衬底100的第一表面上形成n-型层200。n-型层200可以通过外延生长形成在衬底100的第一表面上。特别地，衬底100可以是n+型碳化硅衬底。
参照图3，可以在n-型层200上形成初步n型区200a。初步n型区200a可以通过将诸如氮(N)、磷(P)、砷(As)和锑(Sb)的n型离子注入在n-型层200的上表面上而形成。然而，本发明不限于此，初步n型区200a可以通过在n-型层200上外延生长而形成。初步n型区200a的离子掺杂浓度可以大于n-型层200的离子掺杂浓度。
参照图4，在初步n型区200a上顺序地形成p型区300和n+型区400。p型区300可以通过将诸如硼(B)、铝(Al)、镓(Ga)和铟(In)的p型离子注入在初步n型区200a的上表面上而形成。n+型区400可通过将诸如氮(N)、磷(P)、砷(As)和锑(Sb)的n型离子注入在p型区300的部分上表面上而形成。随着p型区300形成，初步n型区200a的厚度减小。特别地，n+型区400的离子掺杂浓度可以大于初步n型区200a的离子掺杂浓度。
参照图5，可以蚀刻n+型区400、p型区300、初步n型区200a和n-型层200以形成沟槽250。沟槽250可以穿透n+型区400、p型区300和初步n型区200a。
参照图6，可在沟槽250中和n+型区400上形成初步栅绝缘层600a，可在初步栅绝缘层600a上形成栅电极700，并且可在栅电极700上形成初步绝缘层650a。初步绝缘层650a可形成为覆盖栅电极700。
参照图7，可在n-型层200上形成p+型区500。p+型区500可以通过使用初步绝缘层650a作为掩模将诸如硼(B)、铝(Al)、镓(Ga)和铟(In)的p型离子注入在n-型层200的上表面上而形成。因此，p+型区500可以与沟槽250的侧表面隔开，并且设置在p+型区500与沟槽250的侧表面之间的初步n型区200a变成n型区800的第一部分810。特别地，p+型区500的离子掺杂浓度可以大于p型区300的离子掺杂浓度。p+型区500的深度可以形成为大于沟槽250的深度和n型区800的第一部分810的深度。
如上所述，由于可以使用初步绝缘层650a作为掩模来形成p+型区500，因此p+型区500可以在没有附加掩模的情况下形成。
参照图8，可以部分地蚀刻初步栅绝缘层600a和初步绝缘层650a以形成栅绝缘层600和绝缘层650，并且可以形成n型区800的第二部分820。n型区800的第二部分820可以通过使用绝缘层650作为掩模来将诸如氮(N)、磷(P)、砷(As)和锑(Sb)的n型离子注入在n+型区400和p+型区500的上表面上而形成。掺杂的n型离子可以扩散成与n型区800的第一部分810接触并且可形成n型区800的第二部分820，n型区800的第二部分820在垂直于衬底100的上表面的方向上延伸。因此，n型区800的第二部分820可以与沟槽250的侧表面隔开并且可以邻近p+型区500设置。特别地，n型区800的第二部分820的离子掺杂浓度可以大于n型区800的第一部分810的离子掺杂浓度。n型区800的第二部分820的深度可以形成为大于沟槽250的深度并小于p+型区500的深度。
如上所述，n型区800的第二部分820可以使用绝缘层650作为掩模来形成并且可以省略附加掩模。由于n型区800的第二部分820和p+型区500可以在没有附加掩模的情况下形成，因此可以降低n型区800的第二部分820与p+型区500之间的对准误差。参照图1，源电极910可以形成在绝缘层650、n+型区400和p+型区500上，并且漏电极920可以形成在衬底100的第二表面上。特别地，衬底100的第二表面指与衬底100的第一表面相反的表面。
进一步地，将参照图9描述根据本发明的另一示例性实施例的半导体器件。图9是根据本发明的另一示例性实施例的半导体器件的截面图。参照图9，除了n型区800的结构外，根据本示例性实施例的半导体器件具有与图1的半导体器件相同的结构。省略相同结构的描述。
n型区800可以设置在n-型层200上并且可包括第一部分810和第二部分820。第一部分810的第一侧可以邻近沟槽250的侧表面设置并且平行于衬底100的上表面延伸。第一部分810的第二侧可以邻近p+型区500设置。第二部分820可以与第一部分810的下表面接触并且在垂直于衬底100的上表面的方向上延伸。第二部分820可以设置成与沟槽250的侧表面隔开并且邻近p+型区500设置。第一部分810的离子掺杂浓度可以大于第二部分820的离子掺杂浓度。第一部分810的深度和第二部分820的深度与根据图1的半导体器件相同。
尽管已经结合目前认为是示例性的实施例描述了本发明，但将理解的是，本发明不限于所公开的示例性实施例，而是相反地，本发明旨在涵盖包括在权利要求的实质和范围内的各种修改和等同布置。

Claims (18)

1.一种半导体器件，包括：
n-型层，设置在衬底的第一表面上；
沟槽、n型区和p+型区，设置在所述n-型层上；
p型区，设置在所述n型区上；
n+型区，设置在所述p型区上；
栅绝缘层，设置在所述沟槽中；
栅电极，设置在所述栅绝缘层上；
绝缘层，设置在所述栅电极上；
源电极，设置在所述绝缘层、所述n+型区和所述p+型区上；以及
漏电极，设置在所述衬底的第二表面上，
其中所述n型区包括第一部分和第二部分，所述第一部分与所述沟槽的侧表面接触并且平行于所述衬底的上表面延伸，所述第二部分与所述第一部分接触、与所述沟槽的侧表面隔开并且在垂直于所述衬底的上表面的方向上延伸。
2.根据权利要求1所述的半导体器件，其中所述第一部分的深度小于所述沟槽的深度，并且所述第二部分的深度大于所述沟槽的深度。
3.根据权利要求2所述的半导体器件，其中所述p+型区的深度大于所述沟槽的深度。
4.根据权利要求3所述的半导体器件，其中所述p+型区的深度大于所述第二部分的深度。
5.根据权利要求4所述的半导体器件，其中所述n型区、所述p型区和所述n+型区设置在所述p+型区与所述沟槽的侧表面之间。
6.根据权利要求5所述的半导体器件，其中所述第二部分与所述第一部分的侧表面接触，并且所述第二部分的离子掺杂浓度大于所述第一部分的离子掺杂浓度。
7.根据权利要求5所述的半导体器件，其中所述第二部分与所述第一部分的下表面接触，并且所述第二部分的离子掺杂浓度小于所述第一部分的离子掺杂浓度。
8.根据权利要求7所述的半导体器件，其中所述第一部分与所述p+型区接触。
9.一种半导体器件的制造方法，包括：
在衬底的第一表面上顺序地形成n-型层、初步n型区、p型区和n+型区；
蚀刻所述n+型区、所述p型区、所述初步n型区和所述n-型层以形成沟槽；
在所述沟槽中形成初步栅绝缘层；
在所述初步栅绝缘层上形成栅电极；
在所述栅电极上形成初步绝缘层；
在所述n-型层上形成p+型区；
蚀刻所述初步栅绝缘层和所述初步绝缘层以形成栅绝缘层和绝缘层；
在所述n-型层上形成n型区的第二部分；
在所述绝缘层、所述n+型区和所述p+型区上形成源电极；以及
在所述衬底的第二表面上形成漏电极，
其中在形成所述p+型区时，所述初步n型区变成所述n型区的第一部分，
所述n型区的第一部分与所述沟槽的侧表面接触并平行于所述衬底的上表面延伸，并且
所述n型区的第二部分与所述第一部分接触、与所述沟槽的侧表面隔开并且在垂直于所述衬底的上表面的方向上延伸。
10.根据权利要求9所述的方法，其中形成所述p+型区包括使用所述初步绝缘层作为掩模将p型离子注入到所述n-型层的上表面。
11.根据权利要求10所述的方法，其中形成所述n型区的第二部分包括使用所述绝缘层作为掩模将n型离子注入到所述n+型区和所述p+型区的上表面。
12.根据权利要求11所述的方法，其中所述n型区的第一部分的深度小于所述沟槽的深度，并且所述n型区的第二部分的深度大于所述沟槽的深度。
13.根据权利要求12所述的方法，其中所述p+型区的深度大于所述沟槽的深度。
14.根据权利要求13所述的方法，其中所述p+型区的深度大于所述n型区的第二部分的深度。
15.根据权利要求14所述的方法，其中所述n型区、所述p型区和所述n+型区设置在所述p+型区与所述沟槽的侧表面之间。
16.根据权利要求15所述的方法，其中所述n型区的第二部分与所述n型区的第一部分的侧表面接触，并且所述n型区的第二部分的离子掺杂浓度大于所述n型区的第一部分的离子掺杂浓度。
17.根据权利要求15所述的方法，其中所述n型区的第二部分与所述n型区的第一部分的下表面接触，并且所述n型区的第二部分的离子掺杂浓度小于所述n型区的第一部分的离子掺杂浓度。
18.根据权利要求17所述的方法，其中所述n型区的第一部分与所述p+型区接触。
CN201810590251.8A 2017-12-14 2018-06-08 半导体器件及该半导体器件的制造方法 Active CN109962109B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020170172298A KR102335490B1 (ko) 2017-12-14 2017-12-14 반도체 소자 및 그 제조 방법
KR10-2017-0172298 2017-12-14

Publications (2)

Publication Number Publication Date
CN109962109A CN109962109A (zh) 2019-07-02
CN109962109B true CN109962109B (zh) 2023-04-28

Family

ID=66813918

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810590251.8A Active CN109962109B (zh) 2017-12-14 2018-06-08 半导体器件及该半导体器件的制造方法

Country Status (3)

Country Link
US (1) US10396195B2 (zh)
KR (1) KR102335490B1 (zh)
CN (1) CN109962109B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107633829B (zh) * 2017-09-27 2020-03-10 京东方科技集团股份有限公司 一种复位电路、移位寄存器及其驱动方法、显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009117593A (ja) * 2007-11-06 2009-05-28 Denso Corp 炭化珪素半導体装置およびその製造方法
WO2012108165A1 (en) * 2011-02-11 2012-08-16 Denso Corporation Silicon carbide semiconductor device
CN103348478A (zh) * 2011-02-11 2013-10-09 株式会社电装 碳化硅半导体器件及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6849898B2 (en) 2001-08-10 2005-02-01 Siliconix Incorporated Trench MIS device with active trench corners and thick bottom oxide
JP4646743B2 (ja) 2004-09-08 2011-03-09 三洋電機株式会社 半導体装置の製造方法
US7671441B2 (en) 2005-04-05 2010-03-02 International Rectifier Corporation Trench MOSFET with sidewall spacer gates
EP2091083A3 (en) * 2008-02-13 2009-10-14 Denso Corporation Silicon carbide semiconductor device including a deep layer
US7998808B2 (en) 2008-03-21 2011-08-16 International Rectifier Corporation Semiconductor device fabrication using spacers
DE102011079747A1 (de) * 2010-07-27 2012-02-02 Denso Corporation Halbleitervorrichtung mit Schaltelement und Freilaufdiode, sowie Steuerverfahren hierfür

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009117593A (ja) * 2007-11-06 2009-05-28 Denso Corp 炭化珪素半導体装置およびその製造方法
WO2012108165A1 (en) * 2011-02-11 2012-08-16 Denso Corporation Silicon carbide semiconductor device
CN103348478A (zh) * 2011-02-11 2013-10-09 株式会社电装 碳化硅半导体器件及其制造方法

Also Published As

Publication number Publication date
US10396195B2 (en) 2019-08-27
US20190189799A1 (en) 2019-06-20
KR20190071333A (ko) 2019-06-24
KR102335490B1 (ko) 2021-12-03
CN109962109A (zh) 2019-07-02

Similar Documents

Publication Publication Date Title
US7602037B2 (en) High voltage semiconductor devices and methods for fabricating the same
US9450056B2 (en) Lateral DMOS device with dummy gate
EP2680312B1 (en) High breakdown voltage LDMOS device
US8492771B2 (en) Heterojunction semiconductor device and method
US7982224B2 (en) Semiconductor device with silicon carbide epitaxial layer including dopant profiles for reducing current overconcentration
US8704292B2 (en) Vertical capacitive depletion field effect transistor
US9117850B2 (en) Method and system for a gallium nitride vertical JFET with self-aligned source and gate
US7511319B2 (en) Methods and apparatus for a stepped-drift MOSFET
JP4975618B2 (ja) ショットキー接合を有するデバイス
US7550804B2 (en) Semiconductor device and method for forming the same
US9466715B2 (en) MOS transistor having a gate dielectric with multiple thicknesses
JP2007027266A (ja) 半導体素子及びその製造方法
CN110828456A (zh) 用于在功率器件中减小衬底掺杂剂向外扩散的氧插入的Si层
CN116072700A (zh) 具有多外延层衬底配置的氧化物场沟槽功率mosfet
US20090065863A1 (en) Lateral double diffused metal oxide semiconductor device
CN109962109B (zh) 半导体器件及该半导体器件的制造方法
JP5037103B2 (ja) 炭化珪素半導体装置
US20230253460A1 (en) Mosfet device with undulating channel
CN107958936B (zh) 半导体器件以及用于制造半导体器件的方法
KR20190124894A (ko) 반도체 소자 및 그 제조 방법
US20220367713A1 (en) Vertical field effect transistor and method for the formation thereof
KR100204932B1 (ko) 절연 게이트 바이폴라 트랜지스터
CN111009575A (zh) 半导体器件及其制造方法
CN219800849U (zh) 集成电路晶体管器件
CN111316447B (zh) 用于减轻碳化硅mosfet器件中的短沟道效应的方法和组件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant