CN109962073A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109962073A CN109962073A CN201711424067.8A CN201711424067A CN109962073A CN 109962073 A CN109962073 A CN 109962073A CN 201711424067 A CN201711424067 A CN 201711424067A CN 109962073 A CN109962073 A CN 109962073A
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- 239000010936 titanium Substances 0.000 claims description 12
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- 238000010276 construction Methods 0.000 claims description 7
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
Abstract
A kind of semiconductor structure and forming method thereof, forming method includes: offer substrate, includes forerunner's control grid layer including substrate and the discrete multiple gate stack structures being set on substrate, gate stack structure；Dielectric layer is formed on the substrate that gate stack structure exposes, dielectric layer exposes at the top of forerunner's control grid layer；The forerunner's control grid layer for removing segment thickness, forms groove in dielectric layer；Conductive layer is formed in groove by depositing operation, conductive layer and remaining forerunner's control grid layer constitute control grid layer.The present invention replaces metal silicide layer using conductive layer, conductive layer is formed by depositing operation, so as to reduce the thickness of gate stack structure, the corresponding tilt problem for improving gate stack structure improves the boundary controllability and pattern quality of conductive layer, and prevents the material of conductive layer from diffusing in the floating in NAND flash memory device；To sum up, by depositing operation to form conductive layer, it is improved the performance of NAND flash memory device.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
Currently, flash memory (Flash), also known as flash memory, have become non-volatility memorizer (Non-volatile
Memory, NVM) mainstream.According to structure difference, flash memory can be divided into or non-flash (Nor Flash) and with non-flash (NAND
Flash) two kinds.The information for being mainly characterized by keep storage for a long time in the case where not powered of flash memory, and there is integrated level
It is high, access speed is fast, the advantages that being easy to wipe and rewrite, thus obtained extensively in the multinomial field such as microcomputer, automation control
Application.
Due to NAND flash memory device cell density with higher, higher storage density, faster write-in and erasing speed
The advantages such as degree, have been increasingly becoming a kind of structure more generally used in flash memory, have been currently used primarily in digital camera etc.
Flash card and MP3 player in.
With continuous diminution, the reduction of device size of integrated circuit technology node, in order to reduce NAND flash memory device
Sheet resistance (Sheet Resistance) and contact resistance (Contact Resistance), generally use metal silicide layer
The conductor material of (Salicide Layer) as the flash memory.
But after introducing metal silicide technology, the performance of NAND flash memory device is easy to cause to decline.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, improves the property of NAND flash memory device
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided, it is described
Substrate includes substrate and multiple gate stack structures on the substrate, and the multiple gate stack structure is described
Discrete setting on substrate, the gate stack structure include forerunner's control grid layer；In the substrate that the gate stack structure exposes
Upper formation dielectric layer, the dielectric layer expose the top of forerunner's control grid layer；Remove the forerunner control of segment thickness
Grid layer forms groove in the dielectric layer；By depositing operation, form conductive layer in the groove, the conductive layer with
Remaining forerunner's control grid layer constitutes control grid layer.
Optionally, the material of the conductive layer is tungsten or copper.
Optionally, the depositing operation is chemical vapor deposition process or electroplating technology.
Optionally, the step of forming conductive layer in the groove includes: that conductive material is filled into the groove, described
Conductive material also covers at the top of the dielectric layer；Planarization process is carried out to the conductive material, removal is higher than the dielectric layer
The conductive material at top retains the conductive material in the groove as the conductive layer.
Optionally, after forming groove in the dielectric layer, in Xiang Suoshu groove before filling conductive material, the formation
Method further include: form barrier layer in the bottom and side wall of the groove, the barrier layer also covers at the top of the dielectric layer；It is right
The conductive material carried out in the step of planarization process, and also removal is located at the blocking at the top of the dielectric layer.
Optionally, the barrier layer includes titanium layer and the titanium nitride layer on the titanium layer；Alternatively, the barrier layer
Including tantalum layer and with the tantalum nitride layer on the tantalum layer.
Optionally, in the step of substrate is provided, the gate stack structure with a thickness ofExtremely
Optionally, in the step of substrate is provided, forerunner's control grid layer with a thickness ofExtremelyRemove part
In the step of forerunner's control grid layer of thickness, the thickness value for removing forerunner's control grid layer isExtremely
Optionally, forerunner's control grid layer includes: the first polysilicon layer；Etching stop layer is located at first polycrystalline
On silicon layer；Second polysilicon layer is located on the etching stop layer.
Optionally, the material of the etching stop layer be one of silica, silicon nitride, silicon oxynitride and amorphous carbon or
It is a variety of.
Optionally, the step of removing forerunner's control grid layer of segment thickness includes: with the etching stopping layer surface
For stop position, second polysilicon layer is removed；After removing second polysilicon layer, the etching stop layer is removed,
The groove for exposing first polysilicon layer is formed in the dielectric layer.
Optionally, first polysilicon layer with a thickness ofExtremelyThe etching stop layer with a thickness ofExtremelySecond polysilicon layer with a thickness of 270 to
Optionally, in the step of substrate is provided, the gate stack structure further include: gate insulation layer is located at the substrate
Between forerunner's control grid layer；Floating, between the gate insulation layer and forerunner's control grid layer；Gate medium
Layer, between the floating and forerunner's control grid layer.
Correspondingly, the present invention also provides a kind of semiconductor structures, comprising: substrate；Discrete multiple gate stack structures, position
In on the substrate, the gate stack structure includes control grid layer, wherein the control grid layer include forerunner's control grid layer,
And the conductive layer on forerunner's control grid layer, and the conductive layer is formed by depositing operation；Dielectric layer is located at
On the substrate that the gate stack structure exposes, the dielectric layer exposes the top of the conductive layer.
Optionally, the material of the conductive layer is tungsten or copper.
Optionally, the semiconductor structure further include: barrier layer, be located at the conductive layer and forerunner's control grid layer it
Between and the conductive layer and the dielectric layer between.
Optionally, the barrier layer includes titanium layer and the titanium nitride layer on the titanium layer；Alternatively, the barrier layer
Including tantalum layer and with the tantalum nitride layer on the tantalum layer.
Optionally, the gate stack structure with a thickness ofExtremely
Optionally, forerunner's control grid layer with a thickness ofExtremelyThe conductive layer with a thickness of
Extremely
Optionally, the gate stack structure further include: gate insulation layer is located at the substrate and forerunner's control grid layer
Between；Floating, between the gate insulation layer and forerunner's control grid layer；Gate dielectric layer is located at the floating grid
Between layer and forerunner's control grid layer.
Compared with prior art, technical solution of the present invention has the advantage that
The present invention removes forerunner's control grid layer of segment thickness, groove is formed in dielectric layer, and pass through depositing operation,
Conductive layer is formed in the groove to replace metal silicide layer, the conductive layer and remaining forerunner's control grid layer constitute control gate
Layer (Control Gate)；Compared with the scheme for forming metal silicide layer (Salicide Layer), the shape of the conductive layer
It at without consuming forerunner's control grid layer, therefore can suitably reduce the thickness of forerunner's control grid layer, accordingly reduce
The thickness of the gate stack structure, to advantageously reduce etching in the technical process for forming the gate stack structure
The difficulty of technique avoids the occurrence of the excessive problem of depth-to-width ratio (Aspect Ration), and then improves the gate stack structure
Tilt problem；Moreover, the technique for forming metal silicide layer generally includes annealing process, compared with annealing process, using deposition
The mode of technique can lead to the problem of different pressures to avoid to each region of the gate stack structure, to be conducive to further
Improve the tilt problem of the gate stack structure；In addition, passing through depositing operation compared with the scheme for forming metal silicide layer
Mode, the boundary controllability of the conductive layer is more preferable, so as to reduce the conductive layer and formed NAND flash memory device
In the probability that is in contact of gate dielectric layer, accordingly can prevent the material of the conductive layer from diffusing to formed NAND flash memory device
In floating in；To sum up, obtain the performance of formed NAND flash memory device by depositing operation to form the conductive layer
To improve.
In optinal plan, forerunner's control grid layer includes the first polysilicon layer, on first polysilicon layer
Etching stop layer and the second polysilicon layer on the etching stop layer；Removal segment thickness it is described before control
In the step of grid layer processed, using the etching stopping layer surface as stop position, second polysilicon layer is removed, described in removal
The etching stop layer is removed after second polysilicon layer, so as to improve forerunner's control grid layer etch amount it is uniform
Property, it avoids causing forerunner's control grid layer the problem that etching is insufficient or etch amount is excessive, and then be conducive to further improve
The performance of the NAND flash memory device.
Detailed description of the invention
Fig. 1 to Fig. 3 is the corresponding structural schematic diagram of each step in a kind of forming method of semiconductor structure；
Fig. 4 is the electron microscope that semiconductor structure is formed by using forming method described in Fig. 1 to Fig. 3；
Fig. 5 to Figure 10 is the corresponding structural representation of each step in one embodiment of forming method of semiconductor structure of the present invention
Figure；
Figure 11 is the structural schematic diagram of one embodiment of semiconductor structure of the present invention.
Specific embodiment
It can be seen from background technology that metal silicide technology is easy to cause the performance of NAND flash memory device to decline.Now in conjunction with one
The forming method of kind of semiconductor structure, the reason of analyzing the performance decline of NAND flash memory device.
Fig. 1 to Fig. 3 is the corresponding structural schematic diagram of each step in a kind of forming method of semiconductor structure.The formation side
Method includes:
It with reference to Fig. 1, provides substrate (not indicating), the substrate includes substrate 10 and more on the substrate 10
A gate stack structure (not indicating), the discrete setting on the substrate 10 of the multiple gate stack structure.
Specifically, the gate stack structure includes: gate insulation layer 11 on the substrate 10, to be located at the grid exhausted
Floating (Floating Gate) 12 in edge layer 11, the gate dielectric layer 13 on the floating 12 and it is located at
Forerunner's control grid layer (Control Gate) 14 on the gate dielectric layer 13.
In the present embodiment, the material of forerunner's control grid layer 14 is polysilicon, and forerunner's control grid layer 14 can be used for
As the wordline (WL) of formed NAND flash memory device, leakage selection line (DSL) or source selection line (SSL).
In the present embodiment, multiple discrete gate stack structures are formed on the substrate 10, correspondingly, the adjacent grid
There is the groove 15 for exposing the substrate 10 between the laminated construction of pole.
With reference to Fig. 2, dielectric layer 16, the medium are formed on the substrate 10 that the gate stack structure (not indicating) exposes
Layer 16 exposes the partial sidewall of forerunner's control grid layer 14.
With reference to Fig. 3, metal layer (not shown) is formed on the dielectric layer 16, described in the metal layer also cover and is exposed to
14 surface of forerunner's control grid layer of dielectric layer 16；After forming the metal layer, by the first annealing process make the metal layer and
Forerunner's control grid layer 14 reacts to each other, and 14 material of forerunner's control grid layer of segment thickness is changed into metal silication
Object is formed self-aligned original metal silicide layer on remaining forerunner's control grid layer 14；Remove unreacted remaining gold
Belong to layer；After removing unreacted residual metallic layer, by the second annealing process, gold is converted by the original metal silicide layer
Belong to silicide layer 17, the resistance value of the metal silicide layer 17 is less than the resistance value of the original metal silicide layer.
Wherein, the laminated construction of the metal silicide layer 17 and remaining forerunner's control grid layer 14 constitutes the NAND
The control grid layer of flush memory device, using wordline, leakage selection line or the source selection line as the nand flash memory.
It should be noted that since the formation of the metal silicide layer 17 need to consume forerunner's control grid layer 14, because
, when the thickness of forerunner's control grid layer 14 is smaller, be easy to appear that forerunner's control grid layer 14 is consumed completely asks for this
Topic, so that the metal silicide layer 17 is easy to cause to be in contact with the gate dielectric layer 13, the metal silicide layer 17
Material diffuses to a possibility that in the floating 12 and also increase accordingly, and then the programming to the NAND flash memory device
(Program) ability and efficiency generate adverse effect.
So to solve the above-mentioned problems, the thickness of current forerunner's control grid layer 14 is larger, usuallyExtremelyAnd the actual (real) thickness demand based on the gate insulation layer 11, floating 12 and gate dielectric layer 13, the gate stack
The thickness of structure is usuallyExtremelyThe depth of the i.e. described groove 15 isExtremely
In conjunction with reference Fig. 4, the electron microscope that semiconductor structure is formed by using above-mentioned forming method is shown.The grid
The thickness of laminated construction is larger, and the depth-to-width ratio of the groove 15 is accordingly larger, therefore forms the etching of the gate stack structure
The problem of difficulty of technique also increases with it, and the gate stack structure is easy to appear inclination；Wherein, the gate stack structure
Inclination, also result in neighboring gates laminated construction spacing reduce, to occur cross-interference issue in programming process.Especially
The width of NAND flash memory device lesser for device size, the width of the gate stack structure and the groove 15 is smaller,
The probability of the gate stack structure run-off the straight is higher, and inclined degree is also bigger.
Moreover, the step of forming metal silicide layer 17 includes annealing process, in the high temperature item of the annealing process
Under part, be directed toward at the top of forerunner's control grid layer 14 on the direction of bottom, the synthesis speed of the metal silicide layer 17 by
It is decrescence small, therefore the annealing process can generate different pressures, and the gate stack to each region of the gate stack structure
The pressure that structural top is subject to is particularly evident, deforms so as to cause the gate stack structure, and then is degrading the grid
The tilt problem of pole laminated construction.
In addition, during forming metal silicide layer 17, the metal layer and it is exposed to the dielectric layer 16
Forerunner's control grid layer 14 reaction rate it is very fast, the metal layer be located at the dielectric layer 16 in forerunner's control grid layer 14
Reaction rate it is slower, therefore under the barrier effect of the dielectric layer 16, (as schemed at the top side location of the dielectric layer 16
At position shown in 4 chain lines 24) the shoulder easy to form of metal silicide layer 17 (as shown in virtual coil 31 in Fig. 4), thus
It is easy to produce tip electric current, and then reduces the performance of the NAND flash memory device.
Further more, as shown in virtual coil 32 in Fig. 4, even if at present using forerunner's control grid layer 14 of larger thickness, before described
The problem of control grid layer 14 is consumed completely is driven it is possible to occurring, is situated between so as to cause the metal silicide layer 17 with the grid
Matter layer 13 is in contact, and based on above-mentioned analysis, it is difficult to improve by way of increasing by 14 thickness of forerunner's control grid layer
State the problem of forerunner's control grid layer 14 is totally consumed.
So metal silicide technology is easy to cause the performance of NAND flash memory device to decline.
In order to solve the technical problem, the present invention forms conductive layer by depositing operation, to replace metal silicide layer；
The formation of the conductive layer can suitably reduce the thickness of forerunner's control grid layer without consuming forerunner's control grid layer
Degree, so as to improve the tilt problem of the gate stack structure；It, can by the way of depositing operation and compared with annealing process
Different pressures are led to the problem of to avoid to each region of the gate stack structure, to be conducive to further improve the grid
The tilt problem of laminated construction；In addition, the boundary controllability of the conductive layer is more preferable by way of depositing operation, so as to
To reduce the probability that the conductive layer is in contact with the gate dielectric layer in NAND flash memory device, the conductive layer can be accordingly prevented
Material diffuse in the floating in NAND flash memory device；To sum up, institute is made to form the conductive layer by depositing operation
The performance for forming NAND flash memory device is improved.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 5 to Figure 10 is the corresponding structural representation of each step in the forming method first embodiment of semiconductor structure of the present invention
Figure.
It with reference to Fig. 5, provides substrate (not indicating), the substrate includes substrate 100 and on the substrate 100
Multiple gate stack structures, the discrete setting on the substrate 100 of the multiple gate stack structure, the gate stack structure
Including forerunner's control grid layer 200.
The substrate 100 provides technique platform to be subsequently formed flash memory.Specifically, the substrate 100 is used for shape
At with non-flash (NAND Flash) device.
Correspondingly, the gate stack structure further include: gate insulation layer 110, positioned at the substrate 100 and it is described before control
Between grid layer 200 processed；Floating 120, between the gate insulation layer 110 and forerunner's control grid layer 200；Gate medium
Layer 130, between the floating 120 and forerunner's control grid layer 200.
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate can also be
The other materials such as germanium, SiGe, silicon carbide, GaAs or gallium indium, the substrate can also on insulator silicon substrate or
The other kinds of substrate such as the germanium substrate on person's insulator.The material of the substrate, which can be, to be suitable for process requirement or is easy to collect
At material.
The gate insulation layer 110 is the tunnel oxide (Tunnel Oxide) of the NAND flash memory device, is used for conduct
Isolation layer between the floating 120 and the substrate 100, to prevent from being stored in data storage procedure described floating
It sets the carrier in grid layer 120 and enters the substrate 100, and then reduce the loss of carrier, i.e., the described gate insulation layer 110 is suitable for
Prevent the data being stored in the flash from losing.In the present embodiment, the material of the gate insulation layer 110 is oxidation
Silicon.
The floating 120 stores carrier for playing the role of in formed NAND flash memory device, to make
The NAND flash memory device plays the function of data storage.In the present embodiment, the material of the floating 120 is polysilicon.
The gate dielectric layer 130 is used for as the insulation between the floating 120 and subsequent formed control grid layer
Layer.In the present embodiment, the gate dielectric layer 130 is ONO (Oxide-Nitride-Oxide) structure, i.e., the described gate dielectric layer 130
Including the first silicon oxide layer, the first silicon nitride layer on first silicon oxide layer and it is located at first silicon nitride
The second silicon oxide layer on layer.
In the present embodiment, the material of forerunner's control grid layer 200 includes polysilicon, and forerunner's control grid layer 200 is used
In providing Process ba- sis for the control grid layer that is subsequently formed the NAND flash memory device.
It should be noted that subsequent step includes the forerunner's control grid layer 200 for removing segment thickness, by depositing work
Skill, forms conductive layer on remaining forerunner's control grid layer 200, and the conductive layer and remaining forerunner's control grid layer 200 are constituted
The control grid layer of the NAND flash memory device, correspondingly, the removal thickness of subsequent forerunner's control grid layer 200 is described lead
The thickness of electric layer.
Compared with the scheme for forming metal silicide layer, the formation of the subsequent conductive layer is without consuming forerunner's control
Grid layer 200, therefore can suitably reduce the thickness D2 of forerunner's control grid layer 200, accordingly reduce the gate stack knot
The thickness D1 of structure, to advantageously reduce the difficulty of etching technics in the technical process for forming the gate stack structure, keep away
Exempt from the excessive problem of depth-to-width ratio occur, and then the tilt problem of the gate stack structure can be improved.
But the thickness D2 of forerunner's control grid layer 200 is also unsuitable too small.If forerunner's control grid layer 200
Thickness D2 is too small, then is easy to cause the subsequent conductive layer thickness that is formed by too small, to be easy to cause the NAND flash memory device
Sheet resistance and contact resistance it is excessive, and then cause the performance decline of the NAND flash memory device.For this purpose, being mentioned in the present embodiment
In the step of for the substrate, the thickness D2 of forerunner's control grid layer 200 isExtremely
For this purpose, in the present embodiment, thickness D2 and the gate insulation layer 110 based on forerunner's control grid layer 200,
The thickness D1 of the actual (real) thickness demand of floating 120 and gate dielectric layer 130, the gate stack structure isExtremely
In the present embodiment, in order to preferably control the subsequent removal amount to forerunner's control grid layer 200, controled before described
Grid layer 200 processed includes: the first polysilicon layer 140；Etching stop layer 150 is located on first polysilicon layer 140；More than second
Crystal silicon layer 160 is located on the etching stop layer 150.
Wherein, for first polysilicon layer 140 for playing a protective role to the gate dielectric layer 130, increase forms institute
The process window of conductive layer is stated, so that the material of the conductive layer be avoided to diffuse to the floating grid through the gate dielectric layer 130
In layer 120；It is subsequent removal segment thickness forerunner's control grid layer 200 the step of in, 150 surface of etching stop layer
For defining the stop position of etching technics, so as to improve forerunner's control grid layer 200 etch amount homogeneity, keep away
Exempt to cause forerunner's control grid layer 200 problem that etching is insufficient or etch amount is excessive, and then is conducive to further improve institute
State the performance of NAND flash memory device.
Correspondingly, the etching technics of forerunner's control grid layer 200 described in subsequent etching has forerunner's control grid layer 200
Higher etching selection ratio, i.e., the described etching technics are greater than to the etching etch rate of forerunner's control grid layer 200
The etch rate of stop-layer 150, so that the etching stop layer 150 be made preferably to play the role of etching stopping；Moreover, subsequent
It also needs to remove the etching stop layer 150, so that Process ba- sis is provided to be subsequently formed conductive layer, so the etching stop layer
150 material is also the material for being easy to be removed.
So in the present embodiment, choose that processing compatibility is higher, technique is commonly used, is easy to be removed and lower-cost material
Expect the material as the etching stop layer 150.Specifically, the material of the etching stop layer 150 can be silica, nitridation
One of silicon, silicon oxynitride and amorphous carbon are a variety of.
In the present embodiment, the material of the etching stop layer 150 is silica.The work of silica material and polycrystalline silicon material
Skill compatibility preferably, can be avoided and stress problem occur, to be conducive to improve the quality and property of forerunner's control grid layer 200
Energy.
In other embodiments, the etching stop layer can also be ONO (Oxide-Nitride-Oxide) structure, i.e.,
The etching stop layer includes third silicon oxide layer, the second silicon nitride layer on the third silicon oxide layer and is located at
The 4th silicon oxide layer on second silicon nitride layer.
It should be noted that the thickness D4 of the etching stop layer 150 is unsuitable too small, also should not be too large.In subsequent removal
In the step of forerunner's control grid layer 200 of segment thickness, it is difficult to guarantee that forerunner's control grid layer 200 is gone in each region
Removal rates are identical, so if the thickness D4 of the etching stop layer 150 is too small, the etching stop layer 150 is difficult to play quarter
The effect stopped being lost, to be easy to cause etching injury or loss to first polysilicon layer 140, and then to controling before described
The problem that grid layer 200 processed causes etching excessive；It also needs to remove the etching stop layer 150 due to subsequent, if the etch-stop
Only the thickness D4 of layer 150 is excessive, accordingly will increase the technology difficulty for removing the etching stop layer 150, is removing the etching
It during stop-layer 150, is also easy to cause etching injury or loss to first polysilicon layer 140, thus to before described
Drive the problem that control grid layer 200 causes etching excessive.For this purpose, in the present embodiment, the thickness D4 of the etching stop layer 150 isExtremely
It should also be noted that, the thickness D3 of second polysilicon layer 160 is unsuitable too small, also should not be too large.It is subsequent to go
Except the etching stop layer 150 and the second polysilicon layer 160, thus in the etching stop layer 150 and the second polysilicon layer 160
Position at form the conductive layer, i.e., the thickness of the described conductive layer is also influenced by 160 thickness of the second polysilicon layer,
So if the thickness D3 of second polysilicon layer 160 is too small, then it is easy to cause the conductive layer thickness too small, to be easy
Cause sheet resistance and the contact resistance of the NAND flash memory device excessive, and then causes under the performance of the NAND flash memory device
Drop；If the thickness D3 of second polysilicon layer 160 is excessive, the thickness D5 of first polysilicon layer 140 accordingly will lead to
Too small, i.e., the spacing of subsequent formed conductive layer and the gate dielectric layer 130 is too small, then is easy to increase process risk, described to lead
The material of electric layer is easy to diffuse in the floating 120.For this purpose, in the present embodiment, the thickness of second polysilicon layer 160
Spend D3 be 270 to
Correspondingly, in the present embodiment, the thickness D5 of first polysilicon layer 140 isExtremely
In conjunction with reference Fig. 6 and Fig. 7, dielectric layer is formed on the substrate 100 that the gate stack structure (not indicating) exposes
170 (as shown in Figure 7), the dielectric layer 170 expose the top of forerunner's control grid layer 200.
The dielectric layer 170 is formed between the adjacent gate stack structure, for the adjacent gate stack knot
Structure plays insulating effect.
Therefore, the material of the dielectric layer 170 is insulating materials.The material of the dielectric layer 170 can be silica, nitrogen
SiClx, silicon oxynitride or carbon silicon oxynitride.In the present embodiment, the material of the dielectric layer 170 is silica.
In the present embodiment, 170 top of the dielectric layer with flushed at the top of forerunner's control grid layer 200, to be subsequent
Forerunner's control grid layer 200 of removal segment thickness provides good Process ba- sis.
Specifically, the step of forming dielectric layer 170 includes: on the substrate 100 that the gate stack structure exposes
It is formed deielectric-coating 175 (as shown in Figure 6), the deielectric-coating 175 also covers 200 top of forerunner's control grid layer；Using flat
Chemical industry skill, removal are higher than the deielectric-coating 175 at 200 top of forerunner's control grid layer, the remaining media after the flatening process
Film 175 is used as the dielectric layer 170.
In the present embodiment, the dielectric layer 170 be plasma enhanced oxidation layer (Plasma Enhance Oxide,
PEOX), that is, the technique for forming the deielectric-coating 175 is plasma enhanced chemical vapor deposition (Plasma Enhanced
Chemical Vapor Deposition, PECVD) technique.The deposition rate of plasma enhanced chemical vapor deposition technique compared with
Fast and quality of forming film is preferable, to be conducive to improve filling of the dielectric layer 170 between the adjacent gate stack structure
Effect reduces the probability that hole (Void) is formed in the dielectric layer 170.
In other embodiments, the technique for forming the deielectric-coating can also be low-pressure chemical vapor deposition (Low
Pressure Chemical Vapor Deposition, LPCVD) technique or high density plasma CVD
(High Density Plasma Chemical Vapor Deposition, HDPCVD) technique.
With reference to Fig. 8, forerunner's control grid layer 200 (as described in Figure 7) of segment thickness is removed, in the dielectric layer 170
Interior formation groove 180.
The groove 180 is used to provide spatial position to be subsequently formed conductive layer.
It should be noted that being controled before removal is described in the step of forerunner's control grid layer 200 of removal segment thickness
The thickness value of grid layer 200 processed is unsuitable too small, also should not be too large.Thickness by removing forerunner's control grid layer 200 is institute
The thickness of conductive layer is stated, if the thickness value for removing forerunner's control grid layer 200 is too small, the thickness of the conductive layer is corresponding
It is too small, to be easy to cause the sheet resistance of the NAND flash memory device and contact resistance excessive, and then the NAND is caused to dodge
The performance of memory device declines；If the thickness value for removing forerunner's control grid layer 200 is excessive, remaining forerunner's control grid layer
200 thickness is accordingly too small, and the residue forerunner control grid layer 200 is difficult to play the gate dielectric layer 130 and floating 120
To protective effect, the material of the conductive layer is easy to diffuse in the floating 120 through the gate dielectric layer 130.For this purpose,
In the present embodiment, the thickness value for removing forerunner's control grid layer 200 isExtremelyThe depth of the i.e. described groove 180
ForExtremely
Specifically, forerunner's control grid layer 200 includes the first polysilicon layer 140, is located at first polysilicon layer 140
On etching stop layer 150 (as described in Figure 7) and the second polysilicon layer 160 on the etching stop layer 150 (such as
Described in Fig. 7), therefore the step of removing forerunner's control grid layer 200 of segment thickness includes: with the etching stop layer 150
Surface is stop position, removes second polysilicon layer 160；After removing second polysilicon layer 160, the etching is removed
Stop-layer 150 forms the groove 180 for exposing first polysilicon layer 140 in the dielectric layer 170.
In the present embodiment, in order to improve process efficiency, and in order to reduce by first polysilicon layer 140 by plasma
The probability of damage removes second polysilicon layer 160 using dry etch process；After removing second polysilicon layer 160,
The etching stop layer 150 is removed using wet-etching technology.Specifically, in the step of removing second polysilicon layer, institute
Stating etching gas used by dry etch process includes HBr；In the step of removing the etching stop layer, the wet etching
Etching solution used by technique is hydrofluoric acid solution
In other embodiments, second polysilicon layer and etching stopping can also be removed using wet-etching technology
Layer.Specifically, in the step of removing second polysilicon layer, etching solution used by the wet-etching technology is tetramethyl
Base aqua ammonia (TMAH) solution.
Conductive layer is formed in the groove 180 (as shown in Figure 8) by depositing operation in conjunction with reference Fig. 9 and Figure 10
230 (as shown in Figure 10), the conductive layer 230 and remaining forerunner's control grid layer 200 composition control grid layer 300 (as shown in Figure 7)
(as shown in Figure 10).
The conductive layer 230 constitutes control grid layer 300 with remaining forerunner's control grid layer 200, and the control grid layer 300 is used for
As the wordline (WL) of formed NAND flash memory device, leakage selection line (DSL) or source selection line (SSL).Wherein, by residue
The conductive layer 230 is formed on forerunner's control grid layer 200, to reduce the sheet resistance and contact electricity of the NAND flash memory device
Resistance.
In the present embodiment, the material of the conductive layer 230 is tungsten.In other embodiments, the material of the conductive layer is also
It can be copper.
In the present embodiment, the conductive layer 230 is formed in the groove 180 by depositing operation.Due to forming metal
The technique of silicide layer generally includes annealing process, can be to avoid to institute by the way of depositing operation compared with annealing process
It states each region of gate stack structure and leads to the problem of different pressures, to prevent the gate stack structure from deforming, in turn
Be conducive to the tilt problem for further improving the gate stack structure.
Moreover, compared with the scheme for forming metal silicide layer, by way of depositing operation, the conductive layer 230
Pattern is depending on the pattern of the groove 180, therefore the boundary controllability of the conductive layer 230 is more preferable, so as to reduce
The probability that the conductive layer 230 is in contact with the gate dielectric layer 130 can accordingly prevent the material of the conductive layer 230 from expanding
It is dissipated in the floating 120.
So enabling the performance of formed NAND flash memory device to mention to form the conductive layer 230 by depositing operation
It is high.
Specifically, the step of conductive layer 230 are formed in the groove 180 includes: that conduction is filled into the groove 180
Material 220 (as shown in Figure 9), the conductive material 220 also cover 170 top of dielectric layer；To the conductive material 220 into
Row planarization process, removal are higher than the conductive material 220 at 170 top of dielectric layer, retain the conduction material in the groove 180
Material 220 is used as the conductive layer 230.
In the present embodiment, the material of the conductive layer 230 is tungsten, correspondingly, using chemical vapor deposition (Chemical
Vapor Deposition, CVD) technique forms the conductive material 220.Wherein, the porefilling capability of chemical vapor deposition process
Preferably, it so as to effectively improve the conductive layer 230 in the filling quality of the groove 180, and then advantageously reduces described
The sheet resistance and contact resistance of NAND flash memory device.
In other embodiments, such as when the conductive material is copper, the depositing operation mutually should be electroplating technology.
It should be noted that the forming method is also wrapped before filling the conductive material 220 into the groove 180
It includes: barrier layer 210 (as shown in Figure 9) is formed in the bottom and side wall of the groove 180, described in the barrier layer 210 also covers
170 top of dielectric layer, then the conductive material 220 covers the barrier layer 210.Correspondingly, being carried out to the conductive material 220
In the step of planarization process, also removal is located at the barrier layer 210 at the top of the dielectric layer 170.
The barrier layer 210 is for preventing from being formed used reactant and more than described first when the conductive material 220
Crystal silicon layer 140 reacts, and the material for being also possible to prevent the conductive layer 230 is spread into the dielectric layer 170, in order to avoid influence
The insulation performance of the dielectric layer 170, to improve the performance of the NAND flash memory device.
In the present embodiment, the material of the conductive layer 230 is tungsten, correspondingly, the barrier layer 210 includes titanium layer and position
Titanium nitride layer on the titanium layer.In other embodiments, when the material of the conductive layer is copper, the barrier layer is corresponding
Including tantalum layer and with the tantalum nitride layer on the tantalum layer.
Correspondingly, the present invention also provides a kind of semiconductor structures.
With reference to Figure 11, the structural schematic diagram of one embodiment of semiconductor structure of the present invention is shown.
The semiconductor structure includes: substrate 400；Discrete multiple gate stack structures (not indicating) are located at the lining
On bottom 400, the gate stack structure includes control grid layer 600, wherein the control grid layer 600 includes forerunner's control grid layer
440 and the conductive layer 530 on forerunner's control grid layer 440, and the conductive layer 530 passes through depositing operation institute shape
At；Dielectric layer 470, on the substrate 400 that the gate stack structure exposes, the dielectric layer 470 exposes the conductive layer
530 top.
The substrate 400 provides technique platform for the formation of flash memory.In the present embodiment, the flash memory is
With non-flash (NAND Flash) device.
Correspondingly, the gate stack structure further include: gate insulation layer 410, positioned at the substrate 400 and it is described before control
Between grid layer 440 processed；Floating 420, between the gate insulation layer 410 and forerunner's control grid layer 440；Gate medium
Layer 430, between the floating 420 and forerunner's control grid layer 440.
In the present embodiment, the substrate 400 is silicon substrate.In other embodiments, the material of the substrate can also be
The other materials such as germanium, SiGe, silicon carbide, GaAs or gallium indium, the substrate can also on insulator silicon substrate or
The other kinds of substrate such as the germanium substrate on person's insulator.The material of the substrate, which can be, to be suitable for process requirement or is easy to collect
At material.
The gate insulation layer 410 is the tunnel oxide of the NAND flash memory device, for being used as the floating 420
With the isolation layer between the substrate 400, to prevent the load being stored in the floating 420 in data storage procedure
Stream enters the substrate 400, and then reduces the loss of carrier, i.e., the described gate insulation layer 410 is suitable for preventing from being stored in described
Data in flash are lost.In the present embodiment, the material of the gate insulation layer 410 is silica.
The floating 420 stores carrier for playing the role of in the NAND flash memory device, to make institute
State the function that NAND flash memory device plays data storage.In the present embodiment, the material of the floating 420 is polysilicon.
The gate dielectric layer 430 is used for as the insulating layer between the floating 420 and control grid layer 600.This reality
It applies in example, the material of the gate dielectric layer 430 is ONO (Oxide-Nitride-Oxide) structure, i.e., the described gate dielectric layer 430
Including the first silicon oxide layer, the first silicon nitride layer on first silicon oxide layer and it is located at first silicon nitride
The second silicon oxide layer on layer.
The control grid layer 600 is used for the wordline as the NAND flash memory device, leakage selection line or source selection line.
Wherein, for forerunner's control grid layer 440 for playing a protective role to the gate dielectric layer 430, increase forms institute
The process window of conductive layer 530 is stated, so that it is described to avoid the material of the conductive layer 530 from diffusing to through the gate dielectric layer 430
In floating 420；By the way that the conductive layer 230 is arranged on forerunner's control grid layer 440, dodged to reduce the NAND
The sheet resistance and contact resistance of memory device.
In the present embodiment, the material of forerunner's control grid layer 440 is polysilicon, and the material of the conductive layer 530 is tungsten.
In other embodiments, according to actual process demand, the material of the conductive layer can also be copper.
In the present embodiment, metal silicide layer (Salicide Layer) is replaced using the conductive layer 350, and described lead
Electric layer 530 is formed by depositing operation.Compared with the scheme for introducing metal silicide layer, the formation nothing of the conductive layer 530
Forerunner's control grid layer 440 need to be consumed, therefore can suitably reduce the thickness D7 of forerunner's control grid layer 440, is accordingly subtracted
The small thickness D9 of the gate stack structure, to be conducive to drop in the technical process for forming the gate stack structure
The difficulty of low etching technics avoids the occurrence of the excessive problem of depth-to-width ratio, and then improves the tilt problem of the gate stack structure.
Moreover, the technique for forming metal silicide layer generally includes annealing process, compared with annealing process, using deposition work
The mode of skill can lead to the problem of different pressures to avoid to each region of the gate stack structure, to prevent the grid folded
Layer structure deforms, and then is conducive to the tilt problem for further improving the gate stack structure.
In addition, compared with the scheme for introducing metal silicide layer, by way of depositing operation, the conductive layer 530
Boundary controllability is more preferable, so as to reduce the probability that the conductive layer 530 is in contact with the gate dielectric layer 430, accordingly may be used
To prevent the material of the conductive layer 530 from diffusing in the floating 420.
So having correspondinglyd increase the performance of the NAND flash memory device by the conductive layer 530.
It should be noted that the thickness D6 of the conductive layer 530 is unsuitable too small, also should not be too large.If the conductive layer
530 thickness D6 is too small, then is easy to cause the sheet resistance of the NAND flash memory device and contact resistance excessive, and then leads to institute
State the performance decline of NAND flash memory device；If the thickness D6 of the conductive layer 530 is excessive, it is easy to cause the gate stack
The thickness D9 of structure is excessive, in the etching process for forming the gate stack structure, accordingly will increase the etching work
The technology difficulty of skill, and it is easy to cause the gate stack structure run-off the straight, to reduce the property of the NAND flash memory device
Can, alternatively, accordingly will lead to forerunner's control grid layer 440 in the case where the thickness D8 of the control grid layer 600 is certain
Thickness D7 is too small, to reduce protective effect of the forerunner's control grid layer 440 to the gate dielectric layer 430.For this purpose, this implementation
In example, the thickness D6 of the conductive layer isExtremely
Correspondingly, while in order to guarantee protective effect of the forerunner's control grid layer 440 to the gate dielectric layer 430,
Avoid the occurrence of the excessive problem of the gate stack structure thickness D9, in the present embodiment, the thickness of forerunner's control grid layer 440
D7 isExtremely
For this purpose, in the present embodiment, the thickness D7 of thickness D6, forerunner's control grid layer 440 based on the conductive layer, with
And the actual (real) thickness demand of the gate insulation layer 410, floating 420 and gate dielectric layer 430, the thickness of the gate stack structure
Spending D9 isExtremely
It should be noted that the semiconductor structure further include: barrier layer 510, be located at the conductive layer 530 and it is described before
It drives between control grid layer 440 and between the conductive layer 530 and the dielectric layer 470.
The barrier layer 510 for used reactant when preventing from being formed the conductive material 530 with it is described before control
Grid layer 440 processed reacts, and the material for being also possible to prevent the conductive layer 530 is spread into the dielectric layer 470, in order to avoid influence
The insulation performance of the dielectric layer 470, to improve the performance of the NAND flash memory device.
In the present embodiment, the material of the conductive layer 530 is tungsten, correspondingly, the barrier layer 510 includes titanium layer and position
Titanium nitride layer on the titanium layer.In other embodiments, when the material of the conductive layer is copper, the barrier layer is corresponding
Including tantalum layer and with the tantalum nitride layer on the tantalum layer.
The semiconductor structure can be formed using forming method described in previous embodiment, can also be using other formation
Method is formed.In the present embodiment, to the specific descriptions of the semiconductor structure, accordingly retouching in previous embodiment can refer to
It states, details are not described herein for the present embodiment.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, the substrate includes substrate and multiple gate stack structures on the substrate, the multiple grid
The discrete setting over the substrate of pole laminated construction, the gate stack structure include forerunner's control grid layer；
Dielectric layer is formed on the substrate that the gate stack structure exposes, the dielectric layer exposes forerunner's control grid layer
Top；
The forerunner's control grid layer for removing segment thickness, forms groove in the dielectric layer；
By depositing operation, conductive layer is formed in the groove, and the conductive layer and remaining forerunner's control grid layer are constituted and controlled
Grid layer.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the conductive layer be tungsten or
Copper.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the depositing operation is chemical gaseous phase
Depositing operation or electroplating technology.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that form conductive layer in the groove
The step of include:
Conductive material is filled into the groove, the conductive material also covers at the top of the dielectric layer；
Planarization process is carried out to the conductive material, removal is higher than the conductive material at the top of the dielectric layer, retains described recessed
Conductive material in slot is as the conductive layer.
5. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that form groove in the dielectric layer
Afterwards, in Xiang Suoshu groove before filling conductive material, the forming method further include:
Barrier layer is formed in the bottom and side wall of the groove, the barrier layer also covers at the top of the dielectric layer；
In the step of carrying out planarization process to the conductive material, also removal is located at the blocking at the top of the dielectric layer
Layer.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the barrier layer include titanium layer and
Titanium nitride layer on the titanium layer；
Alternatively, the barrier layer include tantalum layer and with the tantalum nitride layer on the tantalum layer.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that described in the step of providing substrate
Gate stack structure with a thickness ofExtremely
8. the forming method of semiconductor structure as claimed in claim 1 or 7, which is characterized in that in the step of substrate is provided, institute
State forerunner's control grid layer with a thickness ofExtremely
In the step of removing forerunner's control grid layer of segment thickness, the thickness value for removing forerunner's control grid layer isExtremely
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that forerunner's control grid layer includes:
First polysilicon layer；
Etching stop layer is located on first polysilicon layer；
Second polysilicon layer is located on the etching stop layer.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the material of the etching stop layer
For one of silica, silicon nitride, silicon oxynitride and amorphous carbon or a variety of.
11. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that remove segment thickness it is described before
The step of driving control grid layer includes: to remove second polysilicon layer using the etching stopping layer surface as stop position；
After removing second polysilicon layer, the etching stop layer is removed, is formed in the dielectric layer and exposes described first
The groove of polysilicon layer.
12. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the thickness of first polysilicon layer
Degree isExtremelyThe etching stop layer with a thickness ofExtremelySecond polysilicon layer with a thickness of
270 to
13. the forming method of semiconductor structure as described in claim 1, which is characterized in that described in the step of providing substrate
Gate stack structure further include:
Gate insulation layer, between the substrate and forerunner's control grid layer；
Floating, between the gate insulation layer and forerunner's control grid layer；
Gate dielectric layer, between the floating and forerunner's control grid layer.
14. a kind of semiconductor structure characterized by comprising
Substrate；
Discrete multiple gate stack structures are located on the substrate, and the gate stack structure includes control grid layer, wherein
The control grid layer includes forerunner's control grid layer and the conductive layer on forerunner's control grid layer, and the conductive layer
It is formed by depositing operation；
Dielectric layer, on the substrate that the gate stack structure exposes, the dielectric layer exposes the top of the conductive layer.
15. semiconductor structure as claimed in claim 14, which is characterized in that the material of the conductive layer is tungsten or copper.
16. semiconductor structure as claimed in claim 14, which is characterized in that the gate stack structure with a thickness of
Extremely
17. the semiconductor structure as described in claim 14 or 16, which is characterized in that forerunner's control grid layer with a thickness ofExtremelyThe conductive layer with a thickness ofExtremely
18. semiconductor structure as claimed in claim 14, which is characterized in that the semiconductor structure further include:
Barrier layer, between the conductive layer and forerunner's control grid layer and the conductive layer and the dielectric layer it
Between.
19. semiconductor structure as claimed in claim 18, which is characterized in that the barrier layer includes titanium layer and is located at described
Titanium nitride layer on titanium layer；
Alternatively, the barrier layer include tantalum layer and with the tantalum nitride layer on the tantalum layer.
20. semiconductor structure as claimed in claim 14, which is characterized in that the gate stack structure further include:
Gate insulation layer, between the substrate and forerunner's control grid layer；
Floating, between the gate insulation layer and forerunner's control grid layer；
Gate dielectric layer, between the floating and forerunner's control grid layer.
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