CN109962067B - SOI-based microcomatography column and micro heat conduction Integrated chip of detector and preparation method - Google Patents
SOI-based microcomatography column and micro heat conduction Integrated chip of detector and preparation method Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 161
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 161
- 239000010703 silicon Substances 0.000 claims abstract description 161
- 239000000758 substrate Substances 0.000 claims abstract description 95
- 238000000034 method Methods 0.000 claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 238000000059 patterning Methods 0.000 claims abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 28
- 239000011521 glass Substances 0.000 claims description 23
- 238000000708 deep reactive-ion etching Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005452 bending Methods 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims 4
- 238000013461 design Methods 0.000 abstract description 7
- 230000035945 sensitivity Effects 0.000 abstract description 4
- 239000007789 gas Substances 0.000 description 6
- 238000001514 detection method Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000004817 gas chromatography Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004587 chromatography analysis Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000006059 cover glass Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- -1 thermistor 51 Chemical compound 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N30/00—Investigating or analysing materials by separation into components using adsorption, absorption or similar phenomena or using ion-exchange, e.g. chromatography or field flow fractionation
- G01N30/02—Column chromatography
- G01N30/60—Construction of the column
- G01N30/6095—Micromachined or nanomachined, e.g. micro- or nanosize
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N30/00—Investigating or analysing materials by separation into components using adsorption, absorption or similar phenomena or using ion-exchange, e.g. chromatography or field flow fractionation
- G01N30/02—Column chromatography
- G01N30/62—Detectors specially adapted therefor
- G01N30/64—Electrical detectors
- G01N30/66—Thermal conductivity detectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Investigating Or Analyzing Materials Using Thermal Means (AREA)
Abstract
The invention provides an SOI-based integrated chip of a micro chromatographic column and a micro heat conduction detector and a preparation method thereof, comprising the following steps: an SOI silicon wafer having a substrate silicon, a buried oxide layer and a top silicon; the patterning stacking structure comprises a cross net-shaped structure, a release groove is arranged below the patterning stacking structure, and the patterning stacking structure is suspended in the release groove; a cap substrate bonded to the top silicon, the cap substrate having micro-grooves, the patterned stacking structure is positioned in the micro-groove; the micro-channel of the micro-chromatographic column is formed in the substrate silicon, a micro-column array is arranged in the micro-channel, and the micro-channel is communicated with the release groove; a base substrate bonded to the substrate silicon, to form a microchannel comprising a microchannel, a relief groove and a microchannel. The micro heat conduction detector and the micro chromatographic column are respectively positioned on the top silicon and the substrate silicon of the SOI silicon wafer, so that the flexibility of design and the controllability of process manufacturing are improved. The invention has the advantages of low dead volume, high sensitivity and the like without additional connecting parts.
Description
Technical Field
The invention belongs to the field of micro-electromechanical systems, and particularly relates to an integrated chip of a micro chromatographic column and a micro heat conduction detector based on SOI and a preparation method thereof.
Background
Gas chromatography is an important analytical instrument and is widely used. The traditional gas chromatograph is generally used in a laboratory due to large volume, high power consumption and heavy weight. However, in the aspects of current environmental safety, production safety, food safety, public safety monitoring and the like, real-time, on-site and rapid detection of complex gas components is required, and development of a miniature gas chromatograph is urgently required. The chromatographic column and the thermal conductivity detector are two key components of the gas chromatograph, and related research groups at home and abroad generally adopt MEMS technology to chip the chromatographic column and the thermal conductivity detector, so as to finally realize the miniaturization of the gas chromatograph.
The connection of the column chip and the thermal conductivity detector chip can lead to new dead volumes, which is detrimental to improving the separation detection performance of micro gas chromatography. To further improve the separation and detection performance, researchers have tried to integrate the microcolumn and the microheat conduction detector on the same chip and design and manufacture the microcolumn and the microheat conduction detector on the same surface of silicon (Bradley C Kaanta, hua Chen and Xin Zhang, A monolithically fabricated gas chromatography separation column with an integrated high sensitivity thermal conductivity detector, j. Micromech. Microbg. 20 (2010) 055016 (6 pp)). However, when the integrated chip of the micro chromatographic column and the micro heat conduction detector is prepared on the same surface of the silicon substrate, the release of the thermistor of the micro heat conduction detector is considered, that is, the silicon below the thermistor is removed by adopting an isotropic etching method after deep etching is finished, at the moment, the micro channel of the thermistor, the micro channel of the chromatographic column and the micro column array in the micro channel are simultaneously etched, that is, the geometric dimension of the device cannot be precisely controlled, the process controllability is poor, the dead volume of the manufactured integrated chip is large, and the performance of the device is reduced.
Based on the above, it is necessary to provide an integrated chip and a preparation method capable of effectively integrating a gas chromatographic column and a micro heat conduction detector.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to an integrated chip of a micro-chromatographic column and a micro-heat conduction detector based on SOI and a method for manufacturing the same, which are used for solving the problems of difficult integration of the micro-chromatographic column and the micro-heat conduction detector or insufficient device performance in the prior art.
To achieve the above and other objects, the present invention provides an integrated chip of a micro-chromatographic column and a micro-heat conduction detector based on SOI, comprising: an SOI silicon wafer having a substrate silicon, a buried oxide layer and a top silicon; the patterned stacked structure comprises a cross net structure, a release groove formed by patterning the substrate silicon and the oxygen-buried layer is arranged below the patterned stacked structure, and the patterned stacked structure is suspended in the release groove; a cap substrate bonded to the top silicon, the cap substrate having a micro-trench, the patterned stack structure being located within the micro-trench; a microchannel of a microcolumn formed in the substrate silicon, the microchannel having a microcolumn array therein, the microchannel being in communication with the release groove; and a base substrate bonded to the substrate silicon of the SOI silicon wafer to form a microchannel including the microchannel, the release groove and the microchannel.
Preferably, a pad groove is further formed in the top layer silicon of the SOI silicon wafer, a pad structure is formed in the pad groove, and the pad structure is electrically connected with the thermistor.
Preferably, the cross-web structure has a plurality of extensions, each extension being coupled to the SOI wafer to support the cross-web structure.
Preferably, the thermistor extends along the cross-web structure in a zigzag shape and is connected with the pad structure.
Preferably, the metal used for the thermistor includes one of a Pt/Ti stack, a Ni/Cr stack, a W/Ti stack and a W/Re stack.
Preferably, the first dielectric film and the second dielectric film comprise a laminated structure formed by one or two of a silicon oxide film and a silicon nitride film.
Preferably, the first dielectric film and the second dielectric film are laminated structures formed by a silicon oxide film and a silicon nitride film, the first dielectric film is laminated structures formed by a silicon oxide film and a silicon nitride film from bottom to top, and the second dielectric film is laminated structures formed by a silicon nitride film and a silicon oxide film from bottom to top.
Preferably, the first dielectric film and the second dielectric film are used for wrapping the thermistor or clamping the thermistor.
Preferably, the patterned stack is suspended from a central region of the relief slot.
Preferably, the cover substrate comprises a glass cover sheet, the base substrate comprises a glass base sheet, the bonding of the glass cover sheet to the top silicon of the SOI wafer comprises electrostatic bonding, and the bonding of the glass base sheet to the substrate silicon of the SOI wafer comprises electrostatic bonding.
Preferably, the micro-channel is formed in the substrate silicon in a shape of back and forth bending extension, and the release groove is connected to two ends of the micro-channel and serves as an inlet end and an outlet end of the micro-channel.
Preferably, the inlet end and the outlet end of the micro-channel are simultaneously formed with the patterned stacking structure of the top silicon-first dielectric film-thermistor-second dielectric film.
The invention also provides a preparation method of the integrated chip of the micro chromatographic column and the micro heat conduction detector based on SOI, which comprises the following steps: step 1), providing an SOI silicon wafer, forming a pad groove on top silicon of the SOI silicon wafer, and depositing a first dielectric film on the surface of the top silicon of the SOI silicon wafer and the bottom of the pad groove; step 2), depositing metal on the first dielectric film and patterning to form a thermistor, and forming a pad structure in the pad groove, wherein the pad structure is electrically connected with the thermistor; step 3), depositing a second dielectric film on the first dielectric film and the thermistor, patterning the first dielectric film and the second dielectric film, and etching the top silicon of the SOI silicon wafer to form a patterned stacked structure comprising the top silicon, the first dielectric film, the thermistor and the second dielectric film, wherein the patterned stacked structure comprises a cross reticular structure, and simultaneously, the bonding pad structure and the bonding area of the top silicon of the SOI silicon wafer are exposed; step 4), providing a cover substrate with micro grooves, bonding the cover substrate and top silicon of the SOI silicon wafer, wherein the patterned stacking structure is positioned in the micro grooves; step 5), etching the substrate silicon of the SOI silicon wafer to form a micro-channel of a micro-chromatographic column and a micro-column array positioned in the micro-channel in the substrate silicon, and simultaneously forming a release groove of the patterned stacked structure by etching the substrate silicon and an oxygen burying layer of the SOI silicon wafer, wherein the release groove is communicated with the micro-channel; and step 6) providing a base substrate and bonding the base substrate to the substrate silicon of the SOI silicon wafer to form a microchannel comprising the microchannel, the release groove and the microchannel.
Preferably, in step 2), the metal comprises one of a Pt/Ti stack, a Ni/Cr stack, a W/Ti stack and a W/Re stack.
Preferably, the cross-web structure has a plurality of extensions therein, each of which is connected to the SOI wafer after the patterned stack of the top silicon-first dielectric film-thermistor-second dielectric film is released to support the cross-web structure.
Preferably, the thermistor extends along the cross-web structure in a zigzag shape and is connected with the pad structure.
Preferably, the first dielectric film and the second dielectric film comprise a laminated structure formed by one or two of a silicon oxide film and a silicon nitride film.
Preferably, the first dielectric film and the second dielectric film wrap the thermistor or clamp the thermistor.
Preferably, in step 4), the area of the cover substrate corresponding to the pad structure has a protection groove, and the protection groove is used for avoiding bonding between the pad structure and the cover substrate.
Preferably, the patterned stack is suspended from a central region of the relief slot.
Preferably, in step 5), the substrate silicon of the SOI silicon wafer is etched from the back side by using a deep reactive ion etching process, and etching the buried oxide layer by adopting a reactive ion etching process to release the patterned stacked structure.
Preferably, the cover substrate comprises a glass cover sheet, the base substrate comprises a glass base sheet, the bonding process of the cover glass and the top silicon of the SOI silicon wafer in step 4) comprises an electrostatic bonding process, the bonding process of the glass negative in the step 6) and the substrate silicon of the SOI silicon wafer comprises an electrostatic bonding process.
Preferably, the micro-channel is formed in the substrate silicon in a shape of back and forth bending extension, and the release groove is connected to two ends of the micro-channel and serves as an inlet end and an outlet end of the micro-channel.
Preferably, the method comprises the steps of, the inlet end and the outlet end of the micro-channel are simultaneously formed with the top layer silicon-first A dielectric film-thermistor-second dielectric film patterned stack structure.
As described above, the integrated chip of the SOI-based micro chromatographic column and the micro heat conduction detector and the preparation method thereof have the following beneficial effects:
the micro heat conduction detector and the micro chromatographic column are respectively positioned on the top silicon and the substrate silicon of the SOI silicon wafer, so that the flexibility of design and the controllability of process manufacturing are improved.
In the integrated chip of the micro chromatographic column and the micro heat conduction detector, the micro channel of the micro heat conduction detector is obtained by deep reactive ion etching, the size is accurate and controllable, and the lower dead volume can be obtained; the micro chromatographic column is also obtained by deep reactive ion etching, and the size is accurate and controllable.
The micro chromatographic column and the micro heat conduction detector are integrated on the same chip, no additional connecting component is needed, and the integrated chip has the advantages of low dead volume, high sensitivity and the like.
Drawings
FIG. 1 is a schematic diagram of a patterned stack structure in a micro-thermal conductivity detector according to the present invention.
Fig. 2 shows a microheat conduction detector of the present invention having four thermistors.
Fig. 3 shows a wheatstone bridge of four thermistors of the present invention.
Fig. 4 to 13 are schematic structural views showing steps of a method for manufacturing an integrated chip of an SOI-based microcolumn and a microheat conduction detector according to the present invention.
Description of element reference numerals
1 SOI silicon chip
11. Substrate silicon
12. Oxygen-buried layer
13. Top silicon
14. Release slot
15. Patterned stacking structure
16a microchannel
16. Microchannel
161. Micro-column array
162. Inlet end
163. Outlet end
2. Mask layer
3. Bonding pad groove
41. First dielectric film
42. Second dielectric film
51. Thermistor with high temperature resistance
52. Bonding pad structure
6. Cover substrate
61. Micro-groove
62. Protection groove
7. Bottom substrate
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-13. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 13, the patterned stack structure 15 of the top silicon 13-first dielectric film 41-thermistor 51-second dielectric film 42 of the present invention is fabricated on the top silicon 13 of the SOI wafer 1 and suspended in the central area of the release groove 14, and the distances from the patterned stack structure 15 to the two sidewalls of the release groove 14 are equal. As shown in fig. 1, in the patterned stacked structure 15, the thermistor 51 is protected by two layers of silicon oxide/silicon nitride films, which are respectively from top to bottom: silicon oxide/silicon nitride, thermistor 51, silicon nitride/silicon oxide, top layer silicon 13, note that the upper silicon oxide/silicon nitride is not shown in fig. 1 for the sake of clarity in the thermistor 51 structure. In addition, it should be noted that: other configurations of patterned stack 15 and thermistor 51 may be used and are not limited to the configuration shown in fig. 1. The novel structural design well solves three problems in the prior art: firstly, the upper and lower layers of silicon oxide/silicon nitride films of the thermistor 51 not only play a role in protecting the upper and lower layers of silicon oxide/silicon nitride films, but also play a role in balancing stress due to the symmetrical distribution of the structure, so that the deformation of the cross-network structure is reduced; secondly, a cross net structure is released by adopting a one-step Deep Reactive Ion Etching (DRIE) process, the side wall of the release groove 14 is steep, and the dead volume of the device is small; thirdly, the top silicon 13 of the SOI silicon wafer 1 is used as a main supporting layer of the thermistor 51, compared with highly doped silicon, the top silicon 13 has complete crystal lattice and few defects, has better mechanical strength as a supporting layer, and the thickness of the supporting layer can be flexibly selected according to performance requirements. In addition, the DRIE process time is shorter compared to long doping times.
In general, a microheat conduction detector includes four thermistors 51R1, R2, R3, R4, as shown in FIG. 2, with R1, R2, R3, R4 connected in the order shown in FIG. 3 to form a Wheatstone bridge. The invention designs and manufactures the patterned stacking structure 15 containing the thermistor 51 of the micro heat conduction detector on the top silicon 13 of the SOI silicon wafer 1, designs and manufactures micro chromatographic columns on the substrate silicon 11 of the SOI silicon wafer 1, and generally contains a micro column array 161 or does not contain the micro column array 161 in a micro channel 16a of micro chromatography. The micro thermal conductivity detector comprises four patterned stacks 15 (with equal or similar resistance values) containing thermistors 51, wherein two cross-web structures containing thermistors 51 are located at the inlet end 162 of the microchannel 16 of the micro chromatographic column and the other two cross-web structures containing thermistors 51 are located at the outlet end 163 of the microchannel 16 of the micro chromatographic column, as shown in fig. 13.
As shown in fig. 4 to 13, the present invention provides a method for manufacturing an integrated chip of a micro chromatographic column and a micro heat conduction detector based on SOI, the method comprising the steps of:
as shown in fig. 4 to 6, step 1) is first performed, an SOI silicon wafer 1 is provided, the SOI silicon wafer 1 includes a substrate silicon 11, a buried oxide layer 12 and a top silicon 13, a mask layer 2 is formed on the top silicon 13 of the SOI silicon wafer 1, the top silicon 13 is etched based on the mask layer 2 to form a pad groove 3, and then a first dielectric film 41 is deposited on the surface of the top silicon 13 of the SOI silicon wafer 1 and the bottom of the pad groove 3.
The thickness of the top silicon layer 13 of the SOI silicon wafer 1 ranges from 0.5 to 200 micrometers, and the first dielectric film 41 has a stacked structure of a silicon oxide film and a silicon nitride film from bottom to top.
As shown in fig. 6, step 2) is then performed to deposit metal on the first dielectric film 41 and pattern the metal to form a thermistor 51, and simultaneously form a pad structure 52 in the pad groove 3, wherein the pad structure 52 is electrically connected to the thermistor 51.
The metal includes one of a Pt/Ti stack, a Ni/Cr stack, a W/Ti stack, and a W/Re stack.
As shown in fig. 7 to 9, step 3) is performed, a second dielectric film 42 is deposited on the first dielectric layer film and the thermistor 51, the first dielectric film 41 and the second dielectric film 42 are patterned, and the top silicon 13 of the SOI wafer 1 is etched, so as to form a patterned stacked structure 15 including the top silicon 13-the first dielectric film 41-the thermistor 51-the second dielectric film 42, and the patterned stacked structure 15 includes a cross-web structure, and the bonding pad structure 52 and the bonding region of the top silicon 13 of the SOI wafer 1 are exposed.
The second dielectric film 42 is a stacked structure of a silicon nitride film and a silicon oxide film from bottom to top.
The cross-web structure has a plurality of extensions therein, each of which is connected to the SOI wafer 1 after the patterned stack 15 of the top silicon 13-first dielectric film 41-thermistor 51-second dielectric film 42 is released, to support the cross-web structure.
The thermistor 51 extends along the cross-web structure in a zigzag shape and is connected to the pad structure 52, as shown in fig. 1 and 13.
The first dielectric film 41 and the second dielectric film 42 are used for wrapping the thermistor 51 or for clamping the thermistor 51. The first dielectric film 41 and the second dielectric film 42 may include a stacked structure of one or both of a silicon oxide film and a silicon nitride film. In this embodiment, the first dielectric film 41 is a stacked structure of a silicon oxide film and a silicon nitride film from bottom to top, the second dielectric film 42 is a stacked structure of a silicon oxide film and a silicon nitride film from top to bottom, that is, the silicon nitride film contacts the thermistor 51, and the silicon oxide film is located outside the silicon nitride film, so that the thermistor 51 can be more effectively protected, and the oxidation resistance of the thermistor 51 is increased.
The upper and lower layers of silicon oxide/silicon nitride films of the thermistor 51 not only play a role in protecting the thermistor, but also play a role in balancing stress due to the symmetrical distribution of the structure, so that the deformation of the cross-network structure is reduced, and the strength and stability of the supporting structure of the thermistor 51 are greatly improved.
As shown in fig. 10, step 4) is performed, a cover substrate 6 having micro-grooves 61 is provided, the cover substrate 6 and the top silicon 13 of the SOI wafer 1 are bonded, and the patterned stack structure 15 is located in the micro-grooves 61.
Preferably, the cover substrate 6 has a protective groove 62 in a region corresponding to the pad structure 52, and the protective groove 62 is used to avoid bonding between the pad structure 52 and the cover substrate 6.
The cover substrate 6 comprises a glass cover sheet, and the bonding process of the glass cover sheet and the top silicon 13 of the SOI silicon wafer 1 is an electrostatic bonding process.
As shown in fig. 11, step 5) is then performed to etch the substrate silicon 11 of the SOI wafer 1 to form micro-channels 16a of micro-chromatography columns and an array of micro-columns 161 located within the micro-channels 16a in the substrate silicon 11, while the release trenches 14 are in communication with the micro-channels 16a by etching the substrate silicon 11 and the buried oxide layer 12 of the SOI wafer 1 to form release trenches 14 of the patterned stack structure 15.
Preferably, the patterned stack 15 is suspended from a central region of the relief slot 14.
Preferably, the substrate silicon 11 of the SOI silicon wafer 1 is etched from the back by using a deep reactive ion etching process to form a micro channel 16a of a micro chromatographic column, a micro column array 161 located in the micro channel 16a and the release groove 14 in the substrate silicon 11, and the buried oxide layer 12 is etched by using a reactive ion etching process to release the patterned stacked structure 15.
The invention adopts deep reactive ion etching DRIE process to form the micro channel 16a and the micro column array 161, and simultaneously releases the patterned stacking structure 15, so that the side walls of the micro channel 16a, the release groove 14 and the micro column array 161 are steep, and the dead volume of the device is reduced.
As shown in fig. 12 and 13, step 6) is finally performed to provide a base substrate 7, and the base substrate 7 is bonded to the substrate silicon 11 of the SOI silicon wafer 1 to form the micro-channel 16 including the micro-groove 61, the release groove 14 and the micro-channel 16 a.
As an example, the base substrate 7 includes a glass negative, and the bonding process of the glass negative and the substrate silicon 11 of the SOI silicon wafer 1 is an electrostatic bonding process.
As an example, as shown in fig. 13, the micro channel 16a is formed in the substrate silicon 11 in a back and forth bent extension shape, and the release grooves 14 are connected to both ends of the micro channel 16a as an inlet end 162 and an outlet end 163 of the micro channel 16. The inlet end 162 and the outlet end 163 of the micro-channel 16 are simultaneously formed with the patterned stack structure 15 of the top silicon 13-the first dielectric film 41-the thermistor 51-the second dielectric film 42. It should be noted that, the number of round-trip bends shown in fig. 13 is 2, and in practical applications, the number of round-trip bends may be more, for example, the number of round-trip bends may be between 1 and 500, and is not limited to the examples listed herein.
As shown in fig. 12 and 13, the present embodiment further provides an SOI-based integrated chip of a micro chromatographic column and a micro heat conduction detector, including: an SOI silicon wafer 1 having a substrate silicon 11, a buried oxide layer 12 and a top silicon 13; a patterned stack structure 15 comprising a top silicon 13, a first dielectric film 41, a thermistor 51 and a second dielectric film 42, wherein the patterned stack structure 15 comprises a cross-network structure, a release groove 14 formed by patterning the substrate silicon 11 and the oxygen-buried layer 12 is arranged below the patterned stack structure 15, and the patterned stack structure 15 is suspended in the release groove 14; a cap substrate 6 bonded to the top silicon 13, the cap substrate 6 having micro-grooves 61, the patterned stack 15 being located within the micro-grooves 61; a microchannel 16a of a microcolumn formed in the substrate silicon 11, the microchannel 16a having a microcolumn array 161 therein, the microchannel 16a being in communication with the relief groove 14; and a base substrate 7 bonded to the substrate silicon 11 of the SOI silicon wafer 1 to form a micro channel 16 including the micro trench 61, the release groove 14 and the micro channel 16 a.
As shown in fig. 6 and 12, a pad groove 3 is further formed in the top silicon 13 of the SOI silicon wafer 1, a pad structure 52 is formed in the pad groove 3, and the pad structure 52 is electrically connected to the thermistor 51.
As shown in fig. 13, the cross-web structure has a plurality of extensions, each of which is connected to the SOI wafer 1 to support the cross-web structure. As shown in fig. 1, the thermistor 51 extends along the cross-web structure in a zigzag shape and is connected to the pad structure 52. The metal used for the thermistor 51 includes one of a Pt/Ti stack, a Ni/Cr stack, a W/Ti stack and a W/Re stack.
As shown in fig. 12, the first dielectric film 41 and the second dielectric film 42 include a stacked structure of one or both of a silicon oxide film and a silicon nitride film. As an example, the first dielectric film 41 and the second dielectric film 42 are stacked structures formed by a silicon oxide film and a silicon nitride film, the first dielectric film 41 is a stacked structure of a silicon oxide film and a silicon nitride film from bottom to top, and the second dielectric film 42 is a stacked structure of a silicon nitride film and a silicon oxide film from bottom to top. As shown in fig. 13, the patterned stack 15 is suspended from a central region of the release slot 14. The first dielectric film 41 and the second dielectric film 42 are used for wrapping the thermistor 51 or for clamping the thermistor 51. The upper and lower layers of silicon oxide/silicon nitride films of the thermistor 51 not only play a role in protecting the thermistor, but also play a role in balancing stress due to the symmetrical distribution of the structure, so that the deformation of the cross-network structure is reduced, and the strength and stability of the supporting structure of the thermistor 51 are greatly improved.
The cover substrate 6 comprises a glass cover sheet, the base substrate 7 comprises a glass cover sheet, the bonding of the glass cover sheet and the top silicon 13 of the SOI silicon wafer 1 is electrostatic bonding, and the bonding of the glass cover sheet and the substrate silicon 11 of the SOI silicon wafer 1 is electrostatic bonding.
As shown in fig. 13, the micro-channel 16a is formed in the substrate silicon 11 in a back-and-forth bent extension shape, and the release grooves 14 are connected to both ends of the micro-channel 16a as an inlet end 162 and an outlet end 163 of the micro-channel 16. The inlet end 162 and the outlet end 163 of the micro-channel 16 are simultaneously formed with the patterned stack structure 15 of the top silicon 13-the first dielectric film 41-the thermistor 51-the second dielectric film 42. It should be noted that, the number of round-trip bends shown in fig. 13 is 2, and in practical applications, the number of round-trip bends may be more, for example, the number of round-trip bends may be between 1 and 500, and is not limited to the examples listed herein.
As described above, the integrated chip of the SOI-based micro chromatographic column and the micro heat conduction detector and the preparation method thereof have the following beneficial effects:
the micro heat conduction detector and the micro chromatographic column are respectively positioned on the top silicon 13 and the substrate silicon 11 of the SOI silicon wafer 1, so that the flexibility of design and the controllability of process manufacturing are improved.
In the integrated chip of the micro chromatographic column and the micro heat conduction detector, the micro channel 16a of the micro heat conduction detector is obtained by deep reactive ion etching, the size is accurate and controllable, and the lower dead volume can be obtained; the micro chromatographic column is also obtained by deep reactive ion etching, and the size is accurate and controllable.
The micro chromatographic column and the micro heat conduction detector are integrated on the same chip, no additional connecting component is needed, and the integrated chip has the advantages of low dead volume, high sensitivity and the like.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and functions of the present invention, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (24)
1. An integrated chip of micro chromatographic column and micro heat conduction detector based on SOI, which is characterized in that: comprising the following steps:
an SOI silicon wafer having a substrate silicon, a buried oxide layer and a top silicon;
the patterned stacked structure comprises a cross net structure, a release groove formed by patterning the substrate silicon and the oxygen-buried layer is arranged below the patterned stacked structure, and the patterned stacked structure is suspended in the release groove;
a cap substrate bonded to the top silicon, the cap substrate having a micro-trench, the patterned stack structure being located within the micro-trench;
a microchannel of a microcolumn formed in the substrate silicon, the microchannel having a microcolumn array therein, the microchannel being in communication with the release groove; and
and a bottom substrate bonded to the substrate silicon of the SOI silicon wafer to form a microchannel including the microchannel, the release groove and the microchannel.
2. The integrated SOI-based microchromatography column and microheat conduction detector chip of claim 1 wherein: a pad groove is formed in the top layer silicon of the SOI silicon wafer, a pad structure is formed in the pad groove, and the pad structure is electrically connected with the thermistor.
3. The integrated SOI-based microchromatography column and microheat conduction detector chip of claim 2 wherein: the cross-web structure has a plurality of extensions, each extension being coupled to the SOI wafer to support the cross-web structure.
4. The integrated SOI-based microchromatography column and microheat conduction detector chip of claim 3 wherein: the thermistor extends along the cross network structure in a zigzag shape and is connected with the bonding pad structure.
5. The integrated SOI-based microchromatography column and microheat conduction detector chip of claim 1 wherein: the metal adopted by the thermistor comprises one of Pt/Ti lamination, ni/Cr lamination, W/Ti lamination and W/Re lamination.
6. The integrated SOI-based microchromatography column and microheat conduction detector chip of claim 1 wherein: the first dielectric film and the second dielectric film comprise a laminated structure formed by one or two of a silicon oxide film and a silicon nitride film.
7. The integrated SOI-based microchromatography column and microheat conduction detector chip of claim 6 wherein: the first dielectric film and the second dielectric film are laminated structures formed by silicon oxide films and silicon nitride films, the first dielectric film is laminated structures of the silicon oxide films and the silicon nitride films from bottom to top, and the second dielectric film is laminated structures of the silicon nitride films and the silicon oxide films from bottom to top.
8. The integrated chip of SOI-based microchromatography column and micro-thermal conductivity detector of claim 1, the method is characterized in that: the first medium film and the second medium film are used for wrapping the thermistor or clamping the thermistor.
9. The integrated SOI-based microchromatography column and microheat conduction detector chip of claim 1 wherein: the patterned stack is suspended from a central region of the relief slot.
10. The integrated SOI-based microchromatography column and microheat conduction detector chip of claim 1 wherein: the cover substrate comprises a glass cover sheet, the base substrate comprises a glass base sheet, the bonding of the glass cover sheet to the top silicon of the SOI silicon wafer comprises electrostatic bonding, and the bonding of the glass base sheet to the substrate silicon of the SOI silicon wafer comprises electrostatic bonding.
11. The integrated SOI-based microchromatography column and microheat conduction detector chip of claim 1 wherein: the micro-channel is formed in the substrate silicon in a back-and-forth bending extension shape, and the release groove is connected to two ends of the micro-channel and serves as an inlet end and an outlet end of the micro-channel.
12. The integrated SOI-based microchromatography column and microheat conduction detector chip of claim 11 wherein: and the inlet end and the outlet end of the micro-channel are simultaneously formed with the patterned stacking structure of the top silicon-first dielectric film-thermistor-second dielectric film.
13. The preparation method of the integrated chip of the micro chromatographic column and the micro heat conduction detector based on the SOI is characterized by comprising the following steps:
step 1), providing an SOI silicon wafer, forming a pad groove on top silicon of the SOI silicon wafer, and depositing a first dielectric film on the surface of the top silicon of the SOI silicon wafer and the bottom of the pad groove;
step 2), depositing metal on the first dielectric film and patterning to form a thermistor, and forming a pad structure in the pad groove, wherein the pad structure is electrically connected with the thermistor;
step 3), depositing a second dielectric film on the first dielectric film and the thermistor, patterning the first dielectric film and the second dielectric film, and etching the top silicon of the SOI silicon wafer to form a patterned stacked structure comprising the top silicon, the first dielectric film, the thermistor and the second dielectric film, wherein the patterned stacked structure comprises a cross network structure, and simultaneously, the bonding pad structure and the bonding area of the top silicon of the SOI silicon wafer are exposed;
step 4), providing a cover substrate with micro grooves, bonding the cover substrate and top silicon of the SOI silicon wafer, wherein the patterned stacking structure is positioned in the micro grooves;
step 5), etching the substrate silicon of the SOI silicon wafer to form a micro-channel of a micro-chromatographic column and a micro-column array positioned in the micro-channel in the substrate silicon, and simultaneously forming a release groove of the patterned stacked structure by etching the substrate silicon and an oxygen burying layer of the SOI silicon wafer, wherein the release groove is communicated with the micro-channel; and
step 6) providing a base substrate and bonding said base substrate to the substrate silicon of said SOI silicon wafer, to form a microchannel comprising the microchannel, the relief groove and the microchannel.
14. The method for manufacturing an integrated chip of an SOI-based microcolumn and a microheat conduction detector as in claim 13, wherein: in step 2), the metal comprises one of a Pt/Ti stack, a Ni/Cr stack, a W/Ti stack and a W/Re stack.
15. The method for manufacturing an integrated chip of an SOI-based microcolumn and a microheat conduction detector as in claim 13, wherein: the cross-web structure is provided with a plurality of extending parts, and each extending part is connected with the SOI silicon chip after the patterned stacking structure of the top silicon-first dielectric film-thermistor-second dielectric film is released so as to support the cross-web structure.
16. The method for manufacturing an integrated chip of an SOI-based microcolumn and a microheat conduction detector as in claim 15 wherein: the thermistor extends along the cross network structure in a zigzag shape and is connected with the bonding pad structure.
17. The method for manufacturing an integrated chip of an SOI-based microcolumn and a microheat conduction detector as in claim 13, wherein: the first dielectric film and the second dielectric film comprise a laminated structure formed by one or two of a silicon oxide film and a silicon nitride film.
18. The method for manufacturing an integrated chip of an SOI-based microcolumn and a microheat conduction detector as in claim 13, wherein: the first medium film and the second medium film wrap the thermistor or clamp the thermistor.
19. The method for manufacturing an integrated chip of an SOI-based microcolumn and a microheat conduction detector as in claim 13, wherein: in step 4), the area of the cover substrate corresponding to the pad structure is provided with a protection groove, and the protection groove is used for avoiding bonding between the pad structure and the cover substrate.
20. The method for manufacturing an integrated chip of an SOI-based microcolumn and a microheat conduction detector as in claim 13, wherein: the patterned stack is suspended from a central region of the relief slot.
21. The method for manufacturing an integrated chip of an SOI-based microcolumn and a microheat conduction detector as in claim 13, wherein: and 5) etching the substrate silicon of the SOI silicon wafer from the back by adopting a deep reactive ion etching process to form a micro channel of a micro chromatographic column, a micro column array positioned in the micro channel and the release groove in the substrate silicon, and etching the buried oxide layer by adopting a reactive ion etching process to release the patterned stacked structure.
22. The method for manufacturing an integrated chip of an SOI-based microcolumn and a microheat conduction detector as in claim 13, wherein: the cover substrate comprises a glass cover sheet, the base substrate comprises a glass base sheet, the bonding process of the glass cover sheet in step 4) and the top silicon of the SOI silicon wafer comprises an electrostatic bonding process, and the bonding process of the glass base sheet in step 6) and the substrate silicon of the SOI silicon wafer comprises an electrostatic bonding process.
23. The method for manufacturing an integrated chip of an SOI-based microcolumn and a microheat conduction detector as in claim 13, wherein: the micro-channel is formed in the substrate silicon in a back-and-forth bending extension shape, and the release groove is connected to two ends of the micro-channel and serves as an inlet end and an outlet end of the micro-channel.
24. The method for fabricating an SOI-based microchromatography column and micro-thermal conductivity detector integrated chip of claim 23 wherein: and the inlet end and the outlet end of the micro-channel are simultaneously formed with the patterned stacking structure of the top silicon-first dielectric film-thermistor-second dielectric film.
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| AU2003285849A1 (en) * | 2002-03-20 | 2004-03-29 | Advanced Sensor Technologies, Inc. | Personal monitor to detect exposure to toxic agents |
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| WO2005018770A2 (en) * | 2003-08-20 | 2005-03-03 | California Institute Of Technology | Design of an ic-processed polymer nano-liquid chromatography system on-a-chip and method of making it |
| GB201421102D0 (en) * | 2014-11-27 | 2015-01-14 | Cambridge Entpr Ltd | Thermal conductivity sensing device, methods for operation and uses of the same |
| WO2016100504A2 (en) * | 2014-12-17 | 2016-06-23 | Robert Bosch Gmbh | A mems gas chromatograph and method of forming a separator column for a mems gas chromatograph |
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