CN109952560B - Timing method and device of virtual timer and electronic device - Google Patents
Timing method and device of virtual timer and electronic device Download PDFInfo
- Publication number
- CN109952560B CN109952560B CN201780001891.4A CN201780001891A CN109952560B CN 109952560 B CN109952560 B CN 109952560B CN 201780001891 A CN201780001891 A CN 201780001891A CN 109952560 B CN109952560 B CN 109952560B
- Authority
- CN
- China
- Prior art keywords
- timer
- virtual
- timing
- hardware
- virtual timer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
Abstract
A timing method of a virtual timer, a device thereof and an electronic device are provided, wherein the timing method comprises the following steps: if the counting time of the hardware timer reaches the timing reference value, entering an interrupt stage and stopping the hardware timer (S701); in the stage of refreshing the virtual timer, judging whether a virtual timer reaching the timing time exists in the virtual timer queue (S702); if yes, executing the corresponding application task (S703); if not, the corresponding application task is not executed; determining the shortest timing time in the virtual timer queue from the moment when the hardware timer stops in the interrupt stage according to the time consumption between the stop of the hardware timer and the latest start before the hardware timer stops in the interrupt stage (S704); entering the hardware timer starting stage, updating the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, exiting the interrupt stage to restart the hardware timer (S705), effectively improving the performance of the processor and reducing the burden of the processor.
Description
Technical Field
The embodiment of the invention relates to the technical field of timers, in particular to a timing method of a virtual timer, a device and an electronic device thereof.
Background
Commonly used timers can be divided into hardware timers and virtual timers (also called software timers). The hardware timer has the advantages of high precision and high real-time performance, but for a processor (a CPU or an MCU), the number of the hardware timers is often limited, so that it is difficult to meet a scenario requiring a large number of timers; the virtual timer can meet the requirement of a scene needing a large number of timers without the limitation of the number of hardware timers.
In the prior art, on one hand, the virtual timer needs to be refreshed according to the minimum timing cycle of the hardware timer as the reference clock, and whether the virtual timer reaches the timing time is judged, so that it can be seen that the smaller the timing cycle of the hardware timer, the more frequently the virtual timer is refreshed, thereby causing the burden of processor resources to be larger. On the other hand, virtual timers are often attached to the operating system, and the use of virtual timer resources often requires porting the entire minimal kernel of the operating system. For the lightweight embedded application, because the resources of the processor are limited, when the application is applied in a complex application scene, if the virtual timer is used, the whole minimum kernel of the operating system needs to be transplanted, the waste of the processor resources is increased.
Disclosure of Invention
In view of the above, an embodiment of the present invention provides a timing method of a virtual timer, an apparatus thereof, and an electronic apparatus, so as to overcome the above technical defects in the prior art.
The embodiment of the invention provides a timing method of a virtual timer, which comprises the following steps:
if the counting time of the hardware timer reaches the timing reference value, entering an interrupt stage and stopping the hardware timer;
in the virtual timer refreshing stage, judging whether a virtual timer reaching the timing time exists in a virtual timer queue; if yes, executing the corresponding application task; if not, the corresponding application task is not executed;
determining the shortest timing time in the virtual timer queue from the moment when the hardware timer stops in the interrupt stage according to the time consumption of the hardware timer between the stop and the latest start before the hardware timer stops in the interrupt stage;
entering a hardware timer starting stage, updating the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, and exiting an interrupt stage to restart the hardware timer.
The embodiment of the invention provides a timing device of a virtual timer, which comprises:
the interrupt module is used for entering an interrupt stage and stopping the hardware timer when the counting time of the hardware timer reaches a timing reference value;
the timing module is used for judging whether a virtual timer which reaches the timing time exists in the virtual timer queue or not in the virtual timer refreshing stage; if yes, executing the corresponding application task; if not, the corresponding application task is not executed;
the refreshing module is used for determining the shortest timing time in the virtual timer queue from the moment when the hardware timer stops in the interrupt stage according to the time consumed by the hardware timer between the stop and the latest start before the hardware timer stops in the interrupt stage;
and the starting module is used for entering a hardware timer starting stage, updating the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, and exiting an interrupt stage to restart the hardware timer.
An embodiment of the present invention provides an electronic device, which includes: the system comprises a hardware timer, a plurality of virtual timers and a processor, wherein when the counting time of the hardware timer reaches a timing reference value, the hardware timer enters an interrupt stage and stops; the processor is configured to:
in the virtual timer refreshing stage, judging whether a virtual timer reaching the timing time exists in a virtual timer queue; if yes, executing the corresponding application task; if not, the corresponding application task is not executed;
determining the shortest timing time in the virtual timer queue from the moment when the hardware timer stops in the interrupt stage according to the time consumption of the hardware timer between the stop and the latest start before the hardware timer stops in the interrupt stage;
and enabling the hardware timer to enter a hardware timer starting stage, updating the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, and exiting an interrupt stage to restart the hardware timer.
In the embodiment of the invention, if the counting time of the hardware timer reaches the timing reference value, the hardware timer enters an interrupt stage and stops; in the virtual timer refreshing stage, judging whether a virtual timer reaching the timing time exists in a virtual timer queue; if yes, executing the corresponding application task; if not, the corresponding application task is not executed; determining the shortest timing time in the virtual timer queue from the moment when the hardware timer stops in the interrupt stage according to the time consumption of the hardware timer between the stop and the latest start before the hardware timer stops in the interrupt stage; entering a hardware timer starting stage, updating the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, exiting an interrupt stage to restart the hardware timer, thereby reducing the refreshing frequency of virtual timer resources, ensuring that the utilization rate of a CPU is lower, effectively improving the performance of a processor and reducing the burden of the processor.
In addition, in an optional embodiment, by defining the global variable and the attribute element of the virtual timer, the timing of the virtual timer is separated from an operating system and is generally used for different operating systems, so that the waste of CPU resources caused by the need of transplanting a minimum kernel of the operating system when the virtual timer is used is avoided.
Drawings
Some specific embodiments of the present invention will be described in detail hereinafter, by way of illustration and not limitation, with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:
FIG. 1 is a schematic diagram of an initialization process according to a first embodiment of the present invention;
FIG. 2 is a flowchart illustrating a virtual timer starting stage according to a second embodiment of the present invention;
FIG. 3 is a flowchart illustrating a third embodiment of stopping a hardware timer according to the present invention;
FIG. 4 is a flowchart illustrating a virtual timer insertion process according to a fourth embodiment of the present invention;
FIG. 5 is a flowchart illustrating a virtual timer refresh phase according to a fifth embodiment of the present invention;
FIG. 6 is a flowchart illustrating a hardware timer starting phase according to a sixth embodiment of the present invention;
FIG. 7 is a flowchart illustrating a timing method of a virtual timer according to a seventh embodiment of the present invention;
FIG. 8 is a flowchart illustrating an eighth embodiment of a virtual timer stopping process;
fig. 9 is a schematic structural diagram of a timing apparatus of a virtual timer according to a ninth embodiment of the present invention.
Detailed Description
It is not necessary for any particular embodiment of the invention to achieve all of the above advantages at the same time.
In order to make those skilled in the art better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments of the present invention shall fall within the scope of the protection of the embodiments of the present invention.
In the following embodiments of the present invention, specific applications are taken as examples to describe the technology of the present invention according to the sequence of the applications, and it should be noted that the following exemplary sequence is only for clearly explaining the technical solution of the present invention, and is not specifically limited to be executed only according to the following sequence.
The following description is made by taking as an example a hardware timer which provides a timing reference for virtual timers each having a unique ID number and a plurality of virtual timers capable of performing a software timing task, the plurality of virtual timers forming virtual timer resources capable of participating in the timing task, and when a part of the virtual timers actually participating in the timing task form a virtual timer queue, the virtual timers which have completed the timing task are deleted from the virtual timer queue and re-entered into the virtual timer resources.
It should be noted that, in a specific application, the corresponding relationship between the hardware timer and the virtual timer in terms of number may be actually configured, and a person skilled in the art may refer to the following description that one hardware timer corresponds to a plurality of virtual timers to implement the corresponding relationship.
Before the following timing method is performed, a structure (for example, referred to as a first structure) is defined for each virtual timer, where the first structure includes a plurality of first attribute elements, for example, including: a flag bit (denoted by used _ flag) which indicates whether any virtual timer has been used, an attribute element (denoted by remaining _ ms) which records the timing time of any virtual timer, a flag bit (denoted by load _ flag) which indicates whether any virtual timer is a periodic virtual timer or a one-time virtual timer, and an attribute element (denoted by load _ ms) which records the timing time of a periodic virtual timer.
In order to manage the virtual timer conveniently, another structural body (for example, referred to as a second structural body) is defined, and the second structural body also includes a plurality of second attribute elements, for example, including: an attribute element (indicated by used _ SW _ TIMER) for recording the number of virtual TIMERs participating in a timed task in the virtual TIMER queue, an attribute element (indicated by test _ SW _ TIMER _ index) for recording the minimum ID number of the virtual TIMERs participating in the timed task in the virtual TIMER queue, and an attribute element (indicated by SW _ TIMER _ CNT) for recording the maximum number of virtual TIMERs in the virtual TIMER resources.
To facilitate management of the above structure, two global variables are exemplarily defined: virtual timer head variable (denoted sw _ timer _ head), time consuming variable (denoted past _ time _ ms), where: the virtual timer head file comprises at least one of the first structure body and the second structure head; the elapsed time variable is used to record the elapsed time between the stop and the most recent start of the hardware timer prior to the stop.
In this embodiment, by defining the global variable, the first structure and the second structure, the timing of the virtual timer is separated from the operating system and is commonly used in different operating systems, thereby avoiding the CPU resource waste caused by the need to migrate the minimum kernel of the operating system to use the virtual timer.
When the timing method of the present invention is used, the virtual timer and the hardware timer may be initialized first, and a specific initialization flow is shown in fig. 1.
FIG. 1 is a schematic diagram of an initialization process according to a first embodiment of the present invention; as shown in fig. 1, it includes the following steps:
s101, initializing global variables, wherein the global variables comprise attribute elements of a first structural body and attribute elements of a second structural body;
specifically, the two global variables are respectively: the virtual timer head variable sw _ timer _ head and the time-consuming variable past _ time _ ms are provided, because the virtual timer head file comprises at least one of the first structure body and the second structure head, the first structure body comprises the plurality of first attribute elements, and the second structure body comprises the plurality of second attribute elements, the initialization of the part or all of the first attribute elements and the part or all of the second attribute elements is realized by initializing the global variable, so that the preparation is prepared for the timing execution of the subsequent timed task.
Specifically, when the global variable is initialized, the virtual timer head variable sw _ timer _ head may be initialized first, and then the time-consuming variable past _ time _ ms may be initialized; or, the time-consuming variable past _ time _ ms may be initialized first, and then the virtual timer head variable sw _ time _ head may be initialized; alternatively, the virtual timer head variable sw _ timer _ head may be initialized simultaneously with the time-consuming variable past _ time _ ms.
And S102, initializing the working mode of the hardware timer.
In this embodiment, in order to implement the timing function of the hardware timer and finally ensure the implementation of the timing task of the virtual timer, the working mode of the hardware timer may be a comparison mode or an overflow mode.
In the following embodiments, the time counted by the hardware timer set as the working mode of the hardware timer is compared with a set timing reference value, and when the timing time of the hardware timer is reached, the comparison interrupt stage is further entered, and finally, the timing task of the virtual timer is realized.
In a specific application scenario, to implement the initialization shown in fig. 1, an interface function (e.g., void sw _ timer _ init (void)) may be predefined, and the initialization process is implemented through the interface function.
After the initialization process shown in fig. 1 is completed, if a new timing task needs to be executed, a virtual timer starting stage is entered, and the detailed process is shown in fig. 2. It should be noted that the new timing task includes the first timing task, or a new timing task added by the existing timing task.
FIG. 2 is a flowchart illustrating a virtual timer starting stage according to a second embodiment of the present invention; as shown in fig. 2, it includes the following steps S201 to S210:
s201, judging whether the timing time required by the new timing task is reasonable, if so, executing the step S202; if not, returning a judgment result that the timing time required by the new timing task is invalid;
in this embodiment, it is specifically determined whether the timing time matched with the new timing task is reasonable according to a set timing time threshold.
Specifically, in this embodiment, the timing time threshold has an upper threshold and a lower threshold, and correspondingly, whether the timing time matched with the new timing task is reasonable is determined according to the upper threshold and the lower threshold. If the timing time matched with the new timing task is located in the range (including end points) defined by the upper threshold and the lower threshold, the timing time matched with the new timing task is reasonable; otherwise, it is not reasonable.
In this embodiment, the upper threshold and the lower threshold may be adjusted according to actual application requirements.
Specifically, in a specific application scenario, the following formula (1) may be used to determine whether the timing time required by the new timing task is reasonable.
min_delay_ms<＝delay_ms<＝max_delay_ms(1)
In formula (1), min _ delay _ ms represents a lower threshold, max _ delay _ ms represents an upper threshold, and delay _ ms represents a timing time matched by the new timing task.
As shown in formula (1), the timing time matched by the new timing task is equal to the lower threshold or the upper threshold, or is greater than the lower threshold and smaller than the upper threshold, and it can be determined that the timing time matched by the new timing task is reasonable.
S202, judging whether unused virtual timers exist in the virtual timer resources or not, and if yes, executing a step S203; otherwise, returning that the virtual timer resources do not have unused virtual timers;
in this embodiment, whether an unused virtual timer exists in the virtual timer resource is determined according to the number of virtual timers executing each timing task in the virtual timer queue and the maximum number of virtual timers in the virtual timer resource.
Specifically, the number of virtual TIMERs executing each timing task in the virtual TIMER queue is obtained by reading a value from a used _ SW _ TIMER, the maximum number of virtual TIMERs in the virtual TIMER resource is obtained from an attribute element SW _ TIMER _ CNT, and if the value read from the used _ SW _ TIMER is smaller than the value read from SW _ TIMER _ CNT, it is determined that unused virtual TIMERs exist in the virtual TIMER resource; if the value read from the used _ SW _ TIMER is equal to the value read from the SW _ TIMER _ CNT, it is determined that there is no unused virtual TIMER in the virtual TIMER resource.
S203, stopping the hardware timer at the starting stage of the virtual timer, and determining the consumed time between the stopping of the hardware timer at the starting stage of the virtual timer and the nearest starting of the hardware timer;
in this embodiment, the reason why the hardware timer is to be stopped in step S203 is to insert a virtual timer into the virtual timer queue and re-determine the timing reference value of the hardware timer.
Specifically, in the present embodiment, a detailed schematic flow of step S203 may be as shown in fig. 3.
Fig. 3 is a flowchart illustrating a hardware timer stopping process in a third embodiment of the invention. As shown in fig. 3, it includes the following steps S213 to S223.
S213, stopping the hardware timer;
in this embodiment, the hardware timer may be specifically stopped by an enable signal or a clock source of the hardware timer may be turned off.
S223, determining the consumed time between the stop of the hardware timer and the nearest start of the hardware timer in the virtual timer starting stage;
in this embodiment, if the count is addition count, when the elapsed time in step S223 is calculated, the start time closest to the elapsed time is subtracted from the stop time in step S213; if based on a subtraction technique, the stop time in step S213 is subtracted from the start time closest thereto.
Further, in obtaining the elapsed time in step S223, a corresponding value is assigned to the elapsed time variable past _ time _ ms.
In the present embodiment, step S213 is executed before step S223, but in other embodiments, step S223 may be executed at step S213.
S204, determining a virtual timer corresponding to the new timing task from the unused virtual timers and inserting the virtual timer into the virtual timer queue.
In this embodiment, an exemplary specific flow of step S204 may be as shown in fig. 4.
Fig. 4 is a flowchart illustrating a virtual timer insertion process according to a fourth embodiment of the present invention. As shown in fig. 4, it includes the following steps S214 to S244.
S214, searching an unused virtual timer in the virtual timer queue;
specifically, if the virtual timers in the virtual timer queue are sorted according to the timing time from short to long, that is, the virtual timer with shorter timing time is sorted in the virtual timer queue before the virtual timer queue, and the virtual timer with longer timing time is sorted in the virtual timer queue after the virtual timer queue, in this embodiment, in step S214, an unused virtual timer is searched, the virtual timer queue is traversed from front to back until a first unused virtual timer is found, and the unused virtual timer is used as the virtual timer used in the subsequent step S213.
S224, updating the number of the virtual timers in the virtual timer;
specifically, as mentioned above, the step S224 is equivalent to modifying the value of the attribute element used _ sw _ timer, and in this embodiment, the value of the attribute element used _ sw _ timer is increased on the basis before updating; e.g., inserting a virtual timer, the value of the attribute element used _ sw _ timer is incremented by one.
S234, registering a new virtual timer in the virtual timer queue according to the virtual timer determined in the step S214 and the incoming attribute element;
in this embodiment, the attribute elements transmitted in step S234 include: the flag bit used _ flag indicating whether the virtual timer has been used, the attribute element of the timing time of the virtual timer, the attribute element used _ sw _ timer indicating the number of virtual timers participating in the timing task, and the like.
In this embodiment, the process of registration is actually equivalent to adding the incoming attribute element to the virtual timer queue to finally complete the insertion process of the virtual timer.
And S244, returning a successful virtual timer insertion result.
S205, judging whether a virtual timer which reaches the timing time exists in the virtual timer queue in the virtual timer refreshing stage, if so, executing the step S206: executing the corresponding application task; if not, the corresponding application task is not executed;
in this embodiment, specifically, the value of the time-consuming variable past _ time _ ms used for recording the time consumption obtained in step S223 is subtracted from the timing time represented by each virtual timer attribute element remaining _ ms in the virtual timer queue when the hardware timer is stopped in step S203; in a specific application scenario, if the difference value is less than or equal to 0, the corresponding virtual timer is a virtual timer of the arrival timing time; in another specific application scenario, if the difference is smaller than the timing resolution of the virtual timer, the virtual timer corresponding to the virtual timer is also represented as the virtual timer of the arrival timing time.
S207, determining the shortest timing time in the virtual timer queue after the virtual timer is inserted according to the consumed time between the stop of the hardware timer at the virtual timer starting stage and the start closest to the stop;
in this embodiment, in a specific application scenario, the step S205 and the step S207 may enter a virtual timer updating stage;
FIG. 5 is a flowchart illustrating a virtual timer refresh phase according to a fifth embodiment of the present invention; as shown in fig. 5, it specifically includes the following steps S216 to S276:
s216, traversing the virtual timer queue, and subtracting the value of the time-consuming variable past _ time _ ms used for recording the time consumption obtained in the step S223 from the timing time represented by each virtual timer attribute element remain _ ms in the virtual timer queue when the hardware timer is stopped in the step S203 to obtain a plurality of difference values;
s226, traversing the corresponding difference value of each virtual timer in the virtual timer queue, and determining the virtual timer reaching the timing time; if the virtual timer reaching the timing time does not exist, jumping to step S276;
in a specific application scenario, if the difference is less than or equal to 0, the virtual timer corresponding to the virtual timer is the virtual timer of the arrival timing time; in another specific application scenario, if the difference is smaller than the timing resolution of the virtual timer, the virtual timer corresponding to the virtual timer is also represented as the virtual timer of the arrival timing time.
S236, executing an application task corresponding to the virtual timer reaching the timing time;
s246, judging whether the virtual timer reaching the timing time is a periodic virtual timer or a one-time virtual timer; if the virtual timer reaching the timing time is the periodic virtual timer, go to step S256; otherwise, go to step S266;
s256, configuring the reached timing time as the timing time of the periodic virtual timer, and jumping to the step S276;
in this embodiment, step S256 is specifically implemented as: and assigning the arrival timing time to an attribute element load _ ms, and then assigning the value of the attribute element load _ ms to a domain _ ms for recording the timing time of the periodic virtual timer.
S266, the attribute of the virtual timer reaching the timing time is modified to be in an unused state after being used, and the number of the used virtual timers represented by the attribute element used _ sw _ timer is reduced by one; and jumps to step S276;
and configuring whether the virtual timer is used or not with the flag bit used _ flag, and modifying the value of the flag bit used _ flag to indicate that the virtual timer reaching the timing time is configured to be used and is in an unused state currently.
S276, determining the shortest timing time in the virtual timer queue after the virtual timer is inserted by the elapsed time between the stop of the hardware timer and the start closest to the stop in the virtual timer starting stage.
In this embodiment, the specific implementation of step S276 may determine the shortest timing time in the virtual timer queue after inserting the virtual timer according to the minimum ID number of the virtual timer recorded by the attribute element latest _ sw _ timer _ index.
S208, judging whether a virtual timer for executing a timing task still exists in the virtual timer queue, if so, executing a step S209; otherwise, executing step S210;
in this embodiment, the determination may be specifically performed by a value of the attribute element used _ sw _ timer, and if the value is not 0, it indicates that there is a virtual timer for executing the timing task; if its value is 0, it means that there is no virtual timer to perform the timing task.
In another embodiment, step S208 may be omitted.
S209, re-entering the hardware timer starting stage, updating the timing reference value according to the shortest timing time in the virtual timer queue after the virtual timer is inserted and the longest timing time of the hardware timer, and re-starting the hardware timer at the virtual timer starting stage.
In this embodiment, a specific implementation process of step S209 is shown in fig. 6.
FIG. 6 is a flowchart illustrating a hardware timer starting phase according to a sixth embodiment of the present invention; as shown in fig. 6, the apparatus includes the following steps S219 to S239:
s219, determining the updated timing reference value according to the shortest timing time in the virtual timer queue after the virtual timer is inserted and the longest timing time of the hardware timer;
in this embodiment, the step S218 is specifically realized by the following formula (2).
cmp_val＝MIN(remain_ms,HARDWARE_MAX_DELAY_MS)(2)
In the above formula (2), the domain _ MS is an attribute element for recording the timing time of the virtual timer, the hardway _ MAX _ DELAY _ MS is an attribute element for recording the longest timing time of the HARDWARE timer, and the updated timing reference value is obtained by calculating the minimum value of the domain _ MS and the hardway _ MAX _ DELAY _ MS.
In this embodiment, for the above formula (2), there may be, but is not limited to, two cases:
in one case, when the shortest timing time in the virtual timer queue after the virtual timer is inserted is longer than the longest timing time of the hardware timer, since the timing time of the virtual timer is not counted up when the maximum timing of the hardware timer is reached while the timing task is executed, the new timing task may be generated, and then the software timer resource needs to be refreshed. Since the virtual timer queue will change, the hardware timer needs to be restarted; in another case, when the shortest timing time in the virtual timer queue after the virtual timer is inserted is longer than the longest timing time of the hardware timer, at this time, since the shortest timing time is reached, the longest timing time of the hardware timer is not yet reached, and since the virtual timer queue is changed, the software timer resource needs to be refreshed, and the hardware timer needs to be restarted.
Therefore, the timing reference value of the hardware timer is related to the longest timing time of the hardware timer, and the timing reference value is related to the timing time of the virtual timer, so that the longer the timing time of the virtual timer is, the lower the refreshing frequency of the virtual timer resource is, and the lower the utilization rate of the CPU is ensured, thereby effectively improving the performance of the processor and reducing the burden of the processor.
S229, filling the updated timing reference value into a comparator included in a hardware periodizer to complete updating of the timing reference value;
and S239, enabling the hardware timer.
In this embodiment, the hardware timer is specifically enabled by an enable signal to restart the hardware timer.
S210, jumping to generate a result that the virtual timer is started successfully.
In this embodiment, when the start of the virtual timer is specifically implemented, a corresponding interface function may be predefined, for example, the agent 16_ t sw _ timer _ start (agent 8_ t reload _ flag, agent 32_ t time _ ms, agent 8_ t _ p _ timer _ ID), where the reload _ flag is a flag indicating whether any virtual timer is a periodic virtual timer or a one-time virtual timer as described above, time _ ms represents a timing time corresponding to a new timing task, and p _ timer _ ID represents an ID number of an inserted virtual timer. The attribute elements are also added to the virtual timer queue in step S234, wherein it is noted that the value of time _ ms is assigned to remaining _ ms.
After the initialization correlation is completed, and after the virtual timer and the hardware timer are started, a complete timing process can be performed.
Fig. 7 is a flowchart illustrating a timing method of a virtual timer according to a seventh embodiment of the present invention; as shown in fig. 7, it includes the following steps S701 to S705:
s701, if the counted time of the hardware timer reaches a timing reference value, entering an interrupt stage and stopping the hardware timer;
in this embodiment, if a difference between the counted time of the hardware timer and the timing reference value is 0, the counted time of the hardware timer reaches the timing reference value.
In this embodiment, after entering the hardware interrupt phase and before stopping the hardware timer, the method further includes: clearing a hardware interrupt zone bit;
s702, judging whether a virtual timer which reaches the timing time exists in a virtual timer queue at a virtual timer refreshing stage; if yes, go to step S703: executing the corresponding application task; if not, the corresponding application task is not executed, and then the step S705 is executed;
in the step, it is determined whether there is a virtual timer in the virtual timer queue reaching the timer time in the refresh phase, which is similar to the step S205, please refer to the related description above.
S704, determining the shortest timing time in the virtual timer queue from the moment when the hardware timer stops in the interrupt stage according to the time consumed by the hardware timer between the stop and the latest start before the hardware timer stops in the interrupt stage;
in this embodiment, step S704 determines that the shortest timing time in the virtual timer queue from the time when the hardware timer stops in the interrupt stage is similar to step S207, please refer to the related description above.
S705, entering a hardware timer starting stage, updating the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, and exiting an interrupt stage to restart the hardware timer.
In this embodiment, the process of step S705 entering the hardware timer starting stage is similar to step S208, please refer to the related description above.
In this embodiment, when exiting the interrupt stage, the interrupt stage exits according to the cleared hardware interrupt flag bit, and since the hardware interrupt flag bit is cleared, the interrupt stage exits after the timing reference value is updated after the execution is completed.
It should be noted that, in another embodiment, after the corresponding application task is executed, before determining that the interrupt phase is entered before the shortest timing time in the virtual timer queue from the time when the hardware timer is stopped, the method further includes: when a virtual timer reaching a timing time is a periodic virtual timer, configuring the reached timing time as the timing time of the periodic virtual timer; when the virtual timer reaching the timing time is the one-time virtual timer, the attribute of the virtual timer reaching the timing time is modified to be in an unused state at present and used end. This attribute modification is implemented in dependence on modifying the value of the flag used flag.
Further, when the virtual timer reaching the timing time is a one-time virtual timer, the method further includes: stopping and deleting the virtual timer of the arrival timing time from the virtual timer queue.
In one specific implementation, to implement the process of FIG. 7 described above, a function may be configured, such as a void timer _ isr _ handler (void).
The stopping process of the virtual timer is specifically implemented by referring to the process flow of the virtual timer shown in fig. 8. Fig. 8 is a flowchart illustrating a process of stopping a virtual timer according to an eighth embodiment of the present invention. As shown in fig. 8, it includes the following steps S811-S817:
s811, entering a virtual timer stopping stage and judging whether the ID number of the virtual timer to be stopped is valid; if yes, go to step S812; if the ID of the virtual timer is invalid, returning the result that the ID of the virtual timer is invalid;
in this embodiment, if the ID number of the virtual TIMER to be stopped is greater than the maximum virtual TIMER number indicated by the attribute element SW _ TIMER _ CNT, it is determined that the virtual TIMER is invalid.
For example, in this embodiment, if the ID number of the stopped virtual timer does not match the timer task, it is determined to be invalid.
S812, judging whether the timing time of the virtual timer to be stopped is the shortest timing time in a virtual timer queue when the hardware timer is stopped in the interrupt stage; if yes, go to step S813; otherwise, the virtual timer to be stopped is not the virtual timer corresponding to the shortest timing time;
in this embodiment, the attribute element latest _ sw _ timer _ index may be used to determine the shortest timing time in the virtual timer queue when S812 is executed, where the shortest timing time is not aligned with the timing time of the virtual timer to be stopped, and if the shortest timing time is equal to the timing time of the virtual timer to be stopped, the timing time of the virtual timer to be stopped is the shortest timing time in the virtual timer queue when the hardware timer is stopped during entering the interrupt phase, that is, the virtual timer to be stopped is the virtual timer corresponding to the shortest timing time; if the two are not equal, the virtual timer to be stopped is not the virtual timer corresponding to the shortest timing time.
If the virtual timer to be stopped is the virtual timer corresponding to the shortest timing time, starting the refreshing processing of the virtual timer because the virtual timer is to be stopped subsequently or restarted for periodic timing, and re-determining the shortest timing time in the queue of the virtual timer; if the stopped virtual timer is not the virtual timer corresponding to the shortest timing time, the shortest timing time in the virtual timer queue can not be changed, so that the stopped virtual timer can be directly deleted from the virtual timer queue, the hardware timer is prevented from being restarted and the timing reference is prevented from being updated, the efficiency is improved, the delay is reduced, and the load of CPU resources is reduced.
S813, stopping the hardware timer at the stop stage of the virtual timer, and consuming time between the stop of the hardware timer at the stop stage of the virtual timer and the latest start before the stop;
in the present embodiment, step S813 is similar to step S203 described above.
S814, modifying the flag bit used _ flag of the virtual timer with the effective ID in the step S811 into false, and reducing the using number of the virtual timer represented by the attribute element used _ sw _ timer by one;
in this embodiment, since the virtual timer that reaches the timing time and stops the timing is deleted from the virtual timer queue, the related attribute element is correspondingly maintained.
S815, executing an application task corresponding to the virtual timer reaching the timing time in the virtual timer refreshing stage;
s816, determining the shortest timing time in the virtual timer queue according to the consumed time of the hardware timer between the stop of the virtual timer at the stop stage and the latest start before the stop;
in this embodiment, step S816 is similar to step S206.
S817, entering a hardware timer starting stage, updating the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, and exiting an interrupt stage to restart the hardware timer.
In this embodiment, step S817 is similar to embodiment 208 described above.
In a specific application scenario, a function, such as the fluid 16_ t sw _ timer _ stop (fluid 8_ t timer _ id), may be configured to implement the stop flow shown in fig. 8.
In the above embodiment, for the embedded system, under different MCU platforms, the longest timing time of the hardware timer is related to the clock of the hardware timer and the bit width of the hardware timer. Without considering the effect of the clock, the effect on the maximum timing time is only the bit width of the hardware timer. Generally, the bit width of our hardware timer is related to the platform of the MCU, for example, a 16-bit hardware timer and a 32-bit hardware timer are commonly used, so that the minimum value of the shortest timing time and the longest timing time is taken when determining the timing reference value of the hardware periodicity, thereby shielding the difference of the longest timing times of different platforms.
It should be noted that, in the above embodiment, when the virtual timer needs to be refreshed or restarted or stopped, hardware interruption may be performed according to needs, and details are not described again.
FIG. 9 is a schematic structural diagram of a timing apparatus of a virtual timer according to a ninth embodiment of the present invention; as shown in fig. 9, it includes:
an interrupt module 901, configured to enter an interrupt phase and stop the hardware timer when the counted time of the hardware timer reaches a timing reference value thereof;
a timing module 902, configured to determine, in a virtual timer refresh stage, whether a virtual timer that reaches a timing time exists in a virtual timer queue; if yes, executing the corresponding application task; if not, the corresponding application task is not executed;
a refresh module 903, configured to determine, according to consumed time between the stop of the hardware timer when entering the interrupt stage and the latest start of the hardware timer before the stop, a shortest timing time in the virtual timer queue from a time when the hardware timer stops when entering the interrupt stage;
a starting module 904, configured to enter a hardware timer starting stage, update the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, and exit an interrupt stage to restart the hardware timer.
The interrupting module 901, the timing module 902, the refreshing module 903, and the initiating module 904 may perform specific steps or further steps corresponding to each of the above-described method embodiments.
The present embodiment further provides an electronic device, which includes: the system comprises a hardware timer, a plurality of virtual timers and a processor, wherein when the counting time of the hardware timer reaches a timing reference value, the hardware timer enters an interrupt stage and stops; the processor is configured to:
in the virtual timer refreshing stage, judging whether a virtual timer reaching the timing time exists in a virtual timer queue; if yes, executing the corresponding application task; if not, the corresponding application task is not executed;
determining the shortest timing time in the virtual timer queue from the moment when the hardware timer stops in the interrupt stage according to the consumed time of the hardware timer between the stop and the latest start before the hardware timer enters the interrupt stage;
and enabling the hardware timer to enter a hardware timer starting stage, updating the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, and exiting an interrupt stage to restart the hardware timer.
In this embodiment, the processor may be a CPU or an MCU.
The electronic device of the embodiment of the invention can be a specific circuit, and can also be a complete machine electronic device, including but not limited to:
(1) Mobile communication devices, which are characterized by mobile communication capabilities and are primarily targeted at providing voice and data communications. Such terminals include smart phones (e.g., iphones), multimedia phones, functional phones, and low-end phones, among others.
(2) The ultra-mobile personal computer equipment belongs to the category of personal computers, has the functions of calculation and processing, and generally has the mobile internet access characteristic. Such terminals include PDA, MID, and UMPC devices, such as ipads.
(3) Portable entertainment devices such devices may display and play multimedia content. Such devices include audio and video players (e.g., ipods), handheld game consoles, electronic books, as well as smart toys and portable car navigation devices.
(4) The server is similar to a general computer architecture, but has higher requirements on processing capability, stability, reliability, safety, expandability, manageability and the like because of the need of providing highly reliable services.
(5) And other electronic devices with data interaction functions.
The above-described embodiments of the apparatus are merely illustrative, wherein the modules described as separate parts may or may not be physically separate, and the parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment may be implemented by software plus a necessary general hardware platform, and may also be implemented by hardware. With this understanding in mind, the above-described technical solutions and/or portions thereof that contribute to the prior art may be embodied in the form of a software product that can be stored on a computer-readable storage medium including any mechanism for storing or transmitting information in a form readable by a computer (e.g., a computer). For example, a machine-readable medium includes Read Only Memory (ROM), random Access Memory (RAM), magnetic disk storage media, optical storage media, flash memory storage media, electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others, and the computer software product includes instructions for causing a computing device (which may be a personal computer, server, or network device, etc.) to perform the methods described in the various embodiments or portions of the embodiments.
As will be appreciated by one of skill in the art, embodiments of the present invention may be provided as a method, apparatus (device), or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (17)
1. A method for timing a virtual timer, comprising:
if the counting time of the hardware timer reaches the timing reference value, entering an interrupt stage and stopping the hardware timer;
in the virtual timer refreshing stage, judging whether a virtual timer reaching the timing time exists in a virtual timer queue; if yes, executing the corresponding application task; if not, the corresponding application task is not executed;
determining the shortest timing time in the virtual timer queue from the moment when the hardware timer stops in the interrupt stage according to the time consumption of the hardware timer between the stop and the latest start before the hardware timer stops in the interrupt stage;
entering a hardware timer starting stage, updating the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, and exiting an interrupt stage to restart the hardware timer.
2. The timing method according to claim 1, wherein after the entering the hardware interrupt phase and before stopping the hardware timer, further comprising: clearing a hardware interrupt zone bit; correspondingly, exiting the interrupt phase includes exiting the interrupt phase according to the cleared hardware interrupt flag.
3. The timing method according to claim 1, further comprising, before the time counted by the hardware timer reaches its timing reference value: and initializing at least one of attribute elements in each virtual timer in the virtual timer resource and the working mode of the hardware timer.
4. The timing method of claim 3, wherein the attribute element comprises: a flag bit for indicating whether any virtual timer is used, a flag bit for recording the timing time of any virtual timer, and a flag bit for indicating whether any virtual timer is a periodic virtual timer or a one-time virtual timer.
5. The timing method according to claim 1, wherein if a new timing task needs to be executed, entering a virtual timer starting stage, and determining whether the timing time required by the new timing task is reasonable, if so, further determining whether there are unused virtual timers in virtual timer resources, and if so, determining a virtual timer corresponding to the new timing task from the unused virtual timers and inserting the virtual timer into the virtual timer queue.
6. The timing method according to claim 5, wherein it is determined whether there are any unused virtual timers in the virtual timer resource based on the number of virtual timers executing each timing task in the virtual timer queue and the maximum number of virtual timers in the virtual timer resource.
7. The timing method according to claim 5, wherein whether the timing time matched with the new timing task is reasonable is judged according to a set timing time threshold.
8. The timing method according to claim 7, wherein the timing time threshold has an upper threshold and a lower threshold, and correspondingly, whether the timing time matched with the new timing task is reasonable is determined according to the upper threshold and the lower threshold.
9. The timing method according to claim 5, further comprising, before inserting the virtual timer corresponding to the new timing task into the virtual timer queue: stopping the hardware timer at the starting stage of the virtual timer, and determining the time consumed by the hardware timer until the hardware timer is stopped at the starting stage of the virtual timer and is started closest to the hardware timer;
after inserting the virtual timer corresponding to the new timing task into the virtual timer queue, the method further includes:
judging whether a virtual timer reaching the timing time exists in the virtual timer queue at the virtual timer refreshing stage, and if so, executing a corresponding application task; if not, the corresponding application task is not executed;
determining the shortest timing time in the virtual timer queue after the virtual timer is inserted according to the consumed time between the stop of the hardware timer at the virtual timer starting stage and the start closest to the stop;
and re-entering a hardware timer starting stage, updating the timing reference value according to the shortest timing time in the virtual timer queue after the virtual timer is inserted and the longest timing time of the hardware timer, and re-starting the hardware timer in the virtual timer starting stage.
10. The timing method according to claim 9, wherein after the virtual timer starting stage determines whether there is a virtual timer in the virtual timer queue that reaches the timing time, the method further comprises: and judging whether a virtual timer for executing a timing task still exists in the virtual timer queue, and if so, re-entering a hardware timer starting stage.
11. The timing method according to claim 1, wherein after the executing the corresponding application task, determining that the interrupt phase is entered before the shortest timing time in the virtual timer queue from the time when the hardware timer is stopped further comprises:
when a virtual timer reaching a timing time is a periodic virtual timer, configuring the reached timing time as the timing time of the periodic virtual timer;
when the virtual timer reaching the timing time is the one-time virtual timer, the attribute of the virtual timer reaching the timing time is modified to be in an unused state at present and used end.
12. The timing method according to claim 11, wherein when the virtual timer for reaching the timing time is a one-time virtual timer, further comprising: stopping and deleting the virtual timer of the arrival timing time from the virtual timer queue.
13. The timing method of claim 12, wherein stopping the virtual timer for reaching the timing time comprises:
entering a virtual timer stopping stage and judging whether the ID number of the virtual timer to be stopped is valid or not;
if the virtual timer is valid, judging whether the timing time of the virtual timer to be stopped is the shortest timing time in a virtual timer queue when the hardware timer is stopped in the interrupt stage; if yes, stopping the hardware timer at the virtual timer stopping stage, and entering a virtual timer refreshing stage;
executing an application task corresponding to the virtual timer reaching the timing time in a virtual timer refreshing stage;
determining the shortest timing time in the virtual timer queue according to the consumed time of the hardware timer between the stop of the virtual timer at the stop stage and the latest start before the stop;
entering a hardware timer starting stage, updating the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, and exiting an interrupt stage to restart the hardware timer.
14. The timing method according to claim 11, wherein a flag bit used or not used is configured for the virtual timer, and when the virtual timer reaching the timing time is a one-time virtual timer, the modifying the attribute of the virtual timer reaching the timing time to be in an end-of-use state and currently in an unused state comprises: the value of the flag bit is modified to indicate that the virtual timer of the timing time of arrival is configured to be in an unused state and to be used.
15. The timing method according to claim 1, wherein after stopping the hardware timer, determining whether there is a virtual timer in the virtual timer queue before the virtual timer that reaches the timing time further comprises:
and traversing all the virtual timers in the virtual timer queue and determining the difference between the timing time of each virtual timer and the consumed time so as to judge whether a virtual timer reaching the timing time exists in the virtual timer queue according to the difference.
16. A timing apparatus of a virtual timer, comprising:
the interrupt module is used for entering an interrupt stage and stopping the hardware timer when the counting time of the hardware timer reaches a timing reference value;
the timing module is used for judging whether a virtual timer reaching the timing time exists in the virtual timer queue at the virtual timer updating stage; if yes, executing the corresponding application task; if not, the corresponding application task is not executed;
the refreshing module is used for determining the shortest timing time in the virtual timer queue from the moment when the hardware timer stops in the interrupt stage according to the time consumed by the hardware timer between the stop and the latest start before the hardware timer stops in the interrupt stage;
and the starting module is used for entering a hardware timer starting stage, updating the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, and exiting an interrupt stage to restart the hardware timer.
17. An electronic device, comprising: the system comprises a hardware timer, a plurality of virtual timers and a processor, wherein if the counting time of the hardware timer reaches a timing reference value, the hardware timer enters an interrupt stage and stops; the processor is configured to:
in the virtual timer refreshing stage, judging whether a virtual timer reaching the timing time exists in a virtual timer queue; if yes, executing the corresponding application task; if not, the corresponding application task is not executed;
determining the shortest timing time in the virtual timer queue from the moment when the hardware timer stops in the interrupt stage according to the time consumption of the hardware timer between the stop and the latest start before the hardware timer stops in the interrupt stage;
and enabling the hardware timer to enter a hardware timer starting stage, updating the timing reference value according to the shortest timing time and the longest timing time of the hardware timer, and exiting an interrupt stage to restart the hardware timer.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2017/107098 WO2019075745A1 (en) | 2017-10-20 | 2017-10-20 | Timing method of virtual timer, apparatus thereof, and electronic apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109952560A CN109952560A (en) | 2019-06-28 |
| CN109952560B true CN109952560B (en) | 2022-12-23 |
Family
ID=66173979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201780001891.4A Active CN109952560B (en) | 2017-10-20 | 2017-10-20 | Timing method and device of virtual timer and electronic device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109952560B (en) |
| WO (1) | WO2019075745A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112559117A (en) * | 2019-09-25 | 2021-03-26 | 阿里巴巴集团控股有限公司 | Timer processing method and device, electronic equipment and computer storage medium |
| CN112463125B (en) * | 2020-12-09 | 2023-09-15 | 百富计算机技术（深圳）有限公司 | Timing method and equipment of virtual timer |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008181392A (en) * | 2007-01-25 | 2008-08-07 | Hitachi Ltd | Virtual timer control method |
| CN101320337A (en) * | 2008-07-16 | 2008-12-10 | 北京中星微电子有限公司 | Timer and its implementing method |
| US7475002B1 (en) * | 2004-02-18 | 2009-01-06 | Vmware, Inc. | Method and apparatus for emulating multiple virtual timers in a virtual computer system when the virtual timers fall behind the real time of a physical computer system |
| CN101566956A (en) * | 2008-04-25 | 2009-10-28 | 北京闻言科技有限公司 | Method for interrupting overtime task by using timer |
| CN101840353A (en) * | 2010-05-14 | 2010-09-22 | 陈冬岩 | Dynamic timing method for real-time embedded operating system |
| CN102541616A (en) * | 2010-12-17 | 2012-07-04 | 北京凯思昊鹏软件工程技术有限公司 | Embedded operating system virtual machine and implementation method thereof |
| CN103034480A (en) * | 2011-09-30 | 2013-04-10 | 重庆重邮信科通信技术有限公司 | Embedded system timer realizing method |
| CN104166585A (en) * | 2014-08-19 | 2014-11-26 | Tcl通讯（宁波）有限公司 | Terminal timer control method and system |
| CN105474127A (en) * | 2013-06-13 | 2016-04-06 | 微软技术许可有限责任公司 | Virtual per processor timers for multiprocessor systems |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5774479A (en) * | 1995-03-30 | 1998-06-30 | Motorola, Inc. | Method and system for remote procedure call via an unreliable communication channel using multiple retransmission timers |
-
2017
- 2017-10-20 WO PCT/CN2017/107098 patent/WO2019075745A1/en active Application Filing
- 2017-10-20 CN CN201780001891.4A patent/CN109952560B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7475002B1 (en) * | 2004-02-18 | 2009-01-06 | Vmware, Inc. | Method and apparatus for emulating multiple virtual timers in a virtual computer system when the virtual timers fall behind the real time of a physical computer system |
| JP2008181392A (en) * | 2007-01-25 | 2008-08-07 | Hitachi Ltd | Virtual timer control method |
| CN101566956A (en) * | 2008-04-25 | 2009-10-28 | 北京闻言科技有限公司 | Method for interrupting overtime task by using timer |
| CN101320337A (en) * | 2008-07-16 | 2008-12-10 | 北京中星微电子有限公司 | Timer and its implementing method |
| CN101840353A (en) * | 2010-05-14 | 2010-09-22 | 陈冬岩 | Dynamic timing method for real-time embedded operating system |
| CN102541616A (en) * | 2010-12-17 | 2012-07-04 | 北京凯思昊鹏软件工程技术有限公司 | Embedded operating system virtual machine and implementation method thereof |
| CN103034480A (en) * | 2011-09-30 | 2013-04-10 | 重庆重邮信科通信技术有限公司 | Embedded system timer realizing method |
| CN105474127A (en) * | 2013-06-13 | 2016-04-06 | 微软技术许可有限责任公司 | Virtual per processor timers for multiprocessor systems |
| CN104166585A (en) * | 2014-08-19 | 2014-11-26 | Tcl通讯（宁波）有限公司 | Terminal timer control method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2019075745A1 (en) | 2019-04-25 |
| CN109952560A (en) | 2019-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11099901B2 (en) | Method for resource allocation and terminal device | |
| WO2017206854A1 (en) | Method, device and system for synchronizing foreground application with scene | |
| WO2017166650A1 (en) | Voice recognition method and device | |
| CN106484848B (en) | Application recommendation method and device | |
| CN109952560B (en) | Timing method and device of virtual timer and electronic device | |
| CN108536480B (en) | Input method configuration method and related product | |
| WO2017016126A1 (en) | Picture composition method and apparatus for speech recognition syntax tree, terminal device and storage medium | |
| EP4137931A1 (en) | Voice skill jumping method for man-machine dialogue, electronic device, and storage medium | |
| CN109766282B (en) | Stuck detection method, stuck detection device and terminal equipment | |
| CN110652728A (en) | Game resource management method and device, electronic equipment and storage medium | |
| WO2019076254A1 (en) | Game application control method, and device | |
| KR101990603B1 (en) | Automatic imports and dependencies in large source code repositories | |
| WO2018026452A1 (en) | System and method for distributing and replaying trigger packets via a variable latency bus interconnect | |
| CN112612519B (en) | Instruction fetching method and device, electronic equipment and storage medium | |
| CN106557525B (en) | Method and device for cleaning application program residual file and electronic equipment | |
| CN109150951B (en) | Method and device for starting Activity of Android system | |
| CN108037839B (en) | Character input method and related product | |
| CN114118397A (en) | Neural network method and apparatus, electronic device, and storage medium | |
| CN111857865A (en) | Event type task processing method and device, electronic equipment and storage medium | |
| CN106775748B (en) | Screen locking switching method and device and electronic equipment | |
| CN113223538B (en) | Voice wake-up method, device, system, equipment and storage medium | |
| CN110868384B (en) | Method and device for determining vulnerable assets in network environment and electronic equipment | |
| US20200192942A1 (en) | Method for Processing Application Resources and Related Products | |
| CN113553161A (en) | Method and device for depicting heterogeneous tasks based on time overhead and related products | |
| CN116492693A (en) | Method and device for promoting online game data, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |