CN109949705A - A kind of array substrate and display device - Google Patents
A kind of array substrate and display device Download PDFInfo
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- CN109949705A CN109949705A CN201910252188.1A CN201910252188A CN109949705A CN 109949705 A CN109949705 A CN 109949705A CN 201910252188 A CN201910252188 A CN 201910252188A CN 109949705 A CN109949705 A CN 109949705A
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Abstract
The present invention provides a kind of array substrate and display devices.Array substrate includes the first substrate being stacked and the second substrate, wherein, first substrate includes first edge binding area and pixel arrangement area, pixel arrangement area is provided with pixel circuit, first edge binding area is formed with several first pins being arranged towards the second substrate, and pixel circuit is electrically connected with several first pins；The second substrate includes second edge binding area and circuit trace area, circuit trace area includes the scan drive circuit for being electrically connected with pixel circuit, second edge binding area is formed with several second pins being arranged towards first substrate, scan drive circuit is electrically connected with several second pins, several first pins and the binding of several second pins connect.The present invention can substantially reduce the pressure drop of cabling by the way that first substrate and the second substrate to be provided separately；Border width is reduced by first substrate and the second substrate solid stack manner, increases screen accounting.
Description
Technical field
The present invention relates to technical field of display panel, in particular to a kind of array substrate and display device.
Background technique
With the prevalence of comprehensive panel type display, requirement of the market to screen accounting is higher and higher.Existing display screen body it is non-
Display area includes driving circuit and binding region etc., occupies very big frame size, becomes and hinders frame size further
The main reason for diminution.
Therefore a kind of array substrate is urgently provided, can solve the setting side of driving circuit and binding region in the prior art
The problem of formula hinders frame size to further reduce.
Summary of the invention
In view of this, the embodiment of the present invention is dedicated to providing a kind of array substrate and display device, to solve the prior art
The technical issues of set-up mode of middle scan drive circuit and binding region, obstruction frame size further reduces.
According to an aspect of the present invention, a kind of array substrate is provided, including the first substrate and the second base being stacked
Plate, wherein
The first substrate includes that first edge binding area and pixel arrangement area, the pixel arrangement area are provided with pixel
Circuit, first edge binding area are formed with several first pins being arranged towards the second substrate, the pixel electricity
Road is electrically connected with several described first pins；
The second substrate includes second edge binding area and circuit trace area, the circuit trace area include for
The scan drive circuit of the pixel circuit electrical connection, second edge binding area, which is formed with towards the first substrate, to be arranged
Several second pins, the scan drive circuit is electrically connected with several described second pins,
Several described first pins and several described second pin bindings connect.
In one embodiment, the second substrate further includes third binding area, and third binding area is described second
Substrate is provided with several third pins far from a side surface of the first substrate, and the third pin is used for and external circuit
Binding connection.
In one embodiment, third binding area is set to the middle position of the second substrate.
In one embodiment, the pixel circuit is connected by the first conductive interconnection line with first pin, described
First conducting interconnection line be scan line, data line, reference voltage line it is one or more.
In one embodiment, the scan drive circuit is connected by the second conductive interconnection line with the second pin,
And the scan drive circuit is connected interconnection line by the third and connect with the third pin.
It in one embodiment, include at least one thin film transistor (TFT) in the second substrate, the third pin connection
To the thin film transistor (TFT).
In one embodiment, each thin film transistor (TFT) includes channel layer, the third pin and the channel layer
Towards the first substrate a side surface contact, and the third pin from the second substrate far from the first substrate
It draws one side surface.
In one embodiment, the second substrate includes the multilayered structure being stacked, and the multilayered structure is towards institute
The side for stating first substrate is provided with organic layer, and the second pin is set in the organic layer.
In one embodiment, at least one set of first pin is provided on the first substrate, and first draw described in every group
Foot includes several described first pins arranged along the extending direction of the respective side edge of the first substrate；And/or
At least one set of second pin is provided in the second substrate, and second pin described in every group includes along described second
Several described second pins of the extending direction arrangement of the respective side edge of substrate.
According to an aspect of the present invention, a kind of display device, including above-mentioned array substrate are provided.
The array substrate and display device that the embodiment of the present invention provides, by the regions such as scan drive circuit and first substrate
It separates, moves in individual the second substrate, first substrate is then subjected to binding with the second substrate again and is connected, battle array is not being influenced
Under the premise of column functional substrate, battle array is reduced by scan drive circuit setting to another substrate using three-dimensional stack manner
The width of column substrate edges is conducive to the screen accounting for further increasing screen, and the second substrate provides bigger sky for cabling
Between, be conducive to the width for suitably increasing cabling, and then reduce the pressure drop of cabling.
Detailed description of the invention
Fig. 1 a show the planar structure schematic diagram of the second substrate of one embodiment of the invention offer.
Fig. 1 b show the planar structure schematic diagram of the first substrate of one embodiment of the invention offer.
Fig. 1 c show the binding structural schematic diagram of the array substrate of one embodiment of the invention offer.
Fig. 2 show the schematic diagram of the section structure of the first substrate of one embodiment of the invention offer.
Fig. 3 show the schematic diagram of the section structure of the second substrate of one embodiment of the invention offer.
Fig. 4 show the flow diagram of the preparation method of the array substrate of one embodiment of the invention offer.
Fig. 5 show the flow diagram of the preparation method for the array substrate that an exemplary embodiment of the invention provides.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that the described embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on this
Embodiment in invention, every other reality obtained by those of ordinary skill in the art without making creative efforts
Example is applied, shall fall within the protection scope of the present invention.
In Fig. 1 a, Fig. 1 b and Fig. 1 c array substrate that one embodiment of the invention provides shown respectively, the second substrate is put down
The binding structural schematic diagram of face structural schematic diagram, the planar structure schematic diagram of first substrate and array substrate.
The aobvious array substrate includes the first substrate 110 being stacked and the second substrate 120, wherein
The first substrate 110 includes first edge binding area 111 and pixel arrangement area 112, the pixel arrangement area
112 are provided with pixel circuit, and first edge binding area 111 is formed with several being arranged towards the second substrate 120
First pin 113, the pixel circuit are electrically connected with several described first pins 113；
The second substrate 120 includes second edge binding area 121 and circuit trace area 123, the circuit trace area
123 include the scan drive circuit for being electrically connected with the pixel circuit, and second edge binding area 121 is formed with direction
Several second pins 124 that the first substrate 110 is arranged, the scan drive circuit and several described second pins
124 electrical connections,
Several described first pins 113 and several described bindings of second pin 124 connect.
The array substrate includes the first substrate 110 of Fig. 1 a, first substrate 110 include first edge binding area 111 and
Pixel arrangement area 112, first edge binding area 111 are formed with several first pins being arranged towards the second substrate 120.
In simple terms, first substrate has stepped construction, and the first edge binding area 111 in Fig. 1 a is actually arranged with pixel
Cloth area 112 is located on two different surfaces of first substrate 110, shared by the reality for also meaning that pixel arrangement area 112
Space can be with first edge binding area 111 it is Chong Die, not can be visually seen, only occupied except first edge is tied up in Fig. 1 a
Determine the central space in area 111.
Specifically, the second substrate 120 is a kind of stepped construction, can substantially area from the plan view of this stepped construction
Three functional areas are separated, are second edge binding area 121 respectively, for carrying out binding connection with other substrates；Third is tied up
Area 123 is determined, for being electrically connected with external circuit；And circuit trace area 122, for being routed, and play to second
Pin, scan drive circuit and the third pin in edge binding area 121 provide the effect of access.It is to be understood that because the
Two substrates 120 are a kind of stepped constructions, are bound so space shared by the circuit trace area 122 in figure can be with second edge
What area 121 and third binding area 123 were overlapped, it not can be visually seen, only occupied except second edge binds area 121 and the in Fig. 1 a
The space in three binding areas 122.
First substrate 110 is that the region for being used to show in existing array substrate is individually split into a substrate, by
It is moved to the one end of first substrate 110 far from viewing area in the place of original cabling, so as to effectively reduce screen frame.
The four Mondays circle of first substrate 110 is provided with the table positioned at first substrate 110 far from 122 side of pixel arrangement area
First pin 113 in face, the material of the first pin 113 can be metal or other conductive materials, be used for and the second substrate 120
Second pin 124 carry out binding connection, realize electric pathway.
The second substrate 120 is exactly individually to split wiring (scan drive circuit) part in existing array substrate
At a substrate, the existing wiring region for occupying non-display area (frame region) and circuit region can be moved to first substrate in this way
Lower section, to effectively reduce screen frame；Simultaneously because originally in the non-display area of screen edge, wiring region and circuit region
Space it is very limited, mode of the invention has arrived the spatial spread of wiring region and circuit region and array substrate similar size
Space, considerably increases the area of wiring and circuit layout, thus be conducive to the width for suitably increasing cabling, to reduce resistance,
Achieve the purpose that reduce cabling pressure drop.
A side surface of first substrate 110 is provided with several third pins in the second substrate 120, second edge is tied up
Determine area 121 and is formed with several second pins 124 being arranged towards first substrate 110.As illustrated in figure 1 c, second pin 124 is
An exposed circle pin around the second substrate 120, the material of pin can be metal or other conductive materials, be used for and first
The first pin 113 on substrate 110 carries out binding connection, realizes electric pathway.
In first substrate 110 and the binding procedure of the second substrate 120, as illustrated in figure 1 c, if being with the direction in scheming
Example, first substrate 110 are located at the top of the second substrate 120, and 113 be the first pin of first substrate 110, and 124 be the second substrate
120 second pin is can be seen that in conjunction with Fig. 1 c, Fig. 2, Fig. 3 after binding first substrate 110 and the second substrate 120, corresponding
From the point of view of vertical structure, pixel arrangement area 112 is located at the upper surface of first substrate 110, and the second substrate 120 is then located at first substrate
110 lower section.Two respective pins of substrate are aligned, then bind together two substrates, with realize two not
The substrate of congenerous is bound, and then forms electric pathway between first substrate 110 and the second substrate 120, realizes existing array base
Function possessed by plate.
Array substrate in the present embodiment moves to list due to separating the regions such as scan drive circuit and first substrate
In only the second substrate, first substrate is then subjected to binding with the second substrate again and is connected, does not influence array substrate function
Under the premise of, using three-dimensional stack manner, effectively reduces scan drive circuit and binding region occupies the space of frame, be conducive to
The screen accounting for further increasing screen can also substantially reduce the pressure drop of cabling, while isolated design can be to display function
Substrate and wiring function substrate realize individually management control, also can effectively reduce maintenance cost.
In one embodiment, the second substrate further includes third binding area, and third binding area is in second base
Plate is provided with several third pins far from a side surface of the first substrate, and the third pin with external circuit for tying up
Fixed connection.
In Figure 1b, second pin is set on the surface in the second substrate 120 towards 110 side of first substrate, for
First pin 113 of first substrate 110 carries out binding connection, and in side table of the second substrate 120 far from first substrate 110
Face is arranged third and binds area 123, and third binding area 123 is provided with several third pins, and third binds the third pin in area 123
For being connected with the external circuit for providing source signal.Same second pin and the identical material of the first pin can be used in third pin
Material, it is therefore an objective to the entire array substrate after binding be connected with external circuit, realize the due function of array substrate.
Wherein, binding area is formed by with the pin of external connection, because not being involved in the problems, such as occupying display area area,
Therefore can be as the second binding area 111, the circle around first surface is configured, or is matched with external circuit
It closes, is arranged to the binding region of various shape different location, the present invention is not specifically limited in this embodiment.
Array substrate in the present embodiment, because third binds area 123 in the second substrate 120 far from first substrate 110
One side surface is provided with several third pins, and the second substrate that binding is formed is electrically connected with external circuit realization,
And the second substrate 120 is arranged in far from a side surface of first substrate 110 in third pin, in the way of solid stacking, drops
Low border width further increases the screen accounting of screen while realizing array substrate due function.
In one embodiment, third binding area is set to the middle position of the second substrate.
As shown in Figure 1 b, specifically, the position among the second substrate 120 is provided with third binding area 123, third binding
Area 123 is provided with several third pins far from a side surface of first substrate 110 in the second substrate 120.
Array substrate provided in this embodiment, since third binding area to be arranged in the middle position of the second substrate 120, phase
Ying Di, several third pins are located at middle position of the second substrate 120 far from 110 1 side surface of first substrate, relative to general
The marginal position of the second substrate 120 is arranged in third binding area, saves track lengths, advantageously reduces the pressure drop of cabling.
In one embodiment, the pixel circuit is connected by the first conductive interconnection line with first pin, and described the
One conducting interconnection line be scan line, data line, reference voltage line it is one or more.
Specifically, the pixel circuit in first substrate 110 is connected to the first pin 113, pixel circuit and the first pin 113
Between be provided with the first conducting interconnection line, the first conducting interconnection line connected pixel circuit and the first pin 113, wherein first leads
Logical interconnection line can be scan line, one or more, scan line, data line, the reference point as a result, of data line, reference voltage line
While one or more of crimping connected pixel circuit and the first pin 113, can be also used for the second substrate 120 and
After external circuit is connected, pixel circuit is driven to work, so that corresponding pixel light emission.
In one embodiment, the scan drive circuit passes through the second conductive interconnection line and 124 phase of second pin
Even, and the scan drive circuit is connected interconnection line by the third and connect with the third pin.
Specifically, when array substrate works, external circuit provides source signal to the second substrate, and source signal control scanning is driven
Dynamic circuit, and then pixel circuit is driven to shine, interconnection line connection is connected by third between scan drive circuit and third pin,
Scan drive circuit is connected to by the second conducting interconnection line with second pin, and the second conducting interconnection line is connected mutually with third as a result,
Second pin, scan drive circuit, third pin are connected to by line, when external circuit is connected to third pin, external circuit
Start to provide source signal for array substrate, under above-mentioned conducting relationship, array substrate can make respective pixel shine.
It in one embodiment, include at least one thin film transistor (TFT) in the second substrate, the third pin connection
To the thin film transistor (TFT).
Specifically, third pin is connected to the thin film transistor (TFT) in the second substrate, and scan drive circuit is connected to
Three pins.
In one embodiment, each thin film transistor (TFT) includes channel layer, the third pin and the channel layer
Towards the first substrate a side surface contact, and the third pin from the second substrate far from the first substrate
It draws one side surface.
In the second substrate, third pin is contacted with a side surface of thin film transistor channel layer towards first substrate, and
It is drawn from the second substrate far from a side surface of first substrate.
Specifically, Fig. 3 show the schematic diagram of the section structure of the second substrate of one embodiment of the invention offer, second base
Plate 300 includes: substrate layer 310, channel layer 320, gate insulation layer 330, grid layer 340, separation layer 350 and organic layer 360, can be with
It is interpreted as 370 one end of third pin and starts with channel layer 320 close to the side of first substrate, cross over grid towards first substrate direction
Insulating layer 330, grid layer 340, separation layer 350 are re-directed towards substrate layer 310 through separation layer 350, grid layer 340, gate insulation layer
330 and substrate layer 310, and drawn from the second substrate far from a side surface of first substrate.Third pin runs through multilayer as a result,
It can be preferably connected to scan drive circuit, be conducive to preferably transmit source signal for scan drive circuit.
In one embodiment, the second substrate includes the multilayered structure being stacked, and the multilayered structure is described in
The side of first substrate is provided with organic layer, and the second pin is set in the organic layer.
Specifically, as shown in figure 3, the second substrate has multilayered structure, wherein multilayered structure includes above-mentioned substrate layer
310, channel layer 320, gate insulation layer 330, grid layer 340, separation layer 350, organic layer 360 are located at the multilayered structure towards first
The side of substrate, second pin are arranged in organic layer.Connect in this way, second pin is only played with scanning circuit in the second substrate
Effect that is logical and then drawing scanning circuit signal, second pin does not occupy the space in the second substrate excessively, by second
More spaces leave scan drive circuit and cabling in substrate, and then are conducive to suitably increase trace width, reduce cabling
Pressure drop.
In one embodiment, at least one set of first pin, and the first pin described in every group are provided on the first substrate
Several described first pins of extending direction arrangement including the respective side edge along the first substrate；And/or
At least one set of second pin is provided in the second substrate, and second pin described in every group includes along described second
Several described second pins of the extending direction arrangement of the respective side edge of substrate.
First edge binding area on the first substrate is provided at least one set of first pin, and every group of first pin includes edge
The extending direction of the respective side edge of first substrate arranges.Specifically, when first edge binding area is provided with one group of first pin,
Every row pixel circuit is connected to first pin, and multirow pixel circuit is connected to multiple first pins, and multiple first pins are
One group, first pin of group along array substrate one side edge arrange, the side edge can for array substrate left edge or
Person's right hand edge, at this point, first pin of group forms the column arranged along array substrate one side edge, similarly, when the first binding
When area is provided with the first pin of multiple groups, the first pin of multiple groups is arranged into multiple row along the one side edge of array substrate.Second pin exists
Arrangement mode in the second substrate is similar to the arrangement mode of the first pin on the first substrate.
Array substrate provided in this embodiment, since the first pin and/or second pin are in first substrate and the second substrate
Respectively along the side edge arrangement of substrate, the width of frame is advantageously reduced.
The present invention also provides a kind of display devices, including any one of the above array substrate.
Specifically, which can be mobile phone, computer etc., be also possible to display panel.
Fig. 4 show the flow diagram of the preparation method of the array substrate of one embodiment of the invention offer, comprising:
410: first substrate is prepared in the first substrate, the first substrate includes first edge binding area and pixel row
Cloth area, the pixel arrangement area are provided with pixel circuit, and first edge binding area is provided with positioned at first substrate close to institute
Several first pins of one side surface of the first substrate are stated, the pixel circuit is electrically connected with several described first pins；
420: the second substrate is prepared in the second substrate, wherein the second substrate includes second edge binding area and electricity
Road cabling area, the circuit trace area include the scan drive circuit for being electrically connected with the pixel circuit, second side
Edge binding area is formed with several second pins positioned at the second substrate far from one side surface of the second substrate, the scan drive circuit
It is electrically connected with several described second pins；
The first substrate prepared in the first substrate can be divided into two regions from the view overlooked or looked up, point
Not Wei first edge bind area and pixel arrangement area, the relevant information in two regions and be described in detail above-mentioned,
Details are not described herein.The edge of a side surface on the first substrate that preparation finishes for contacting with the first substrate is arranged
The first exposed pin of one circle, first pin of circle surrounds first edge binding region, for drawing with second in the second substrate
Foot carries out binding connection.
Likewise, preparing the second substrate in the second substrate, wherein the second substrate includes second edge binding area and electricity
Road cabling area, second edge binding area are provided with the circle second pin positioned at the second substrate far from one side surface of the second substrate.
The stepped construction in the second substrate is prepared by routine techniques in the second substrate, wherein preparing the second base finished
Plate can generally comprise two regions, respectively second edge binding area and circuit trace from the view overlooked or looked up
Area, the relevant information in two regions are described in detail above-mentioned, and details are not described herein.Second finished in preparation
The edge of a side surface of the substrate far from the second substrate can see the exposed second pin of a circle, and a circle second pin is enclosed
At second edge binding region, for carrying out binding connection with the first pin on first substrate.
Further, the surrounding mark in the side surface that the second substrate that preparation finishes is used to contact with the second substrate far may be used
To see that exposed third pin, third pin form third and bind area.
Third, which binds area, can be located at the second substrate margin location similar to the first binding area, the second binding area setting, a corral
It sets, it is preferable that the middle position of the second substrate is arranged in third binding area.
430: the first substrate of removing and the second substrate obtain first substrate and the second substrate；
The first substrate and the second substrate are removed using such as laser lift-off technique, obtain first substrate and the second substrate.
After first substrate and the removing of the first substrate, the first pin on first substrate can just be exposed；Likewise, in the second base
After plate and the removing of the second substrate, the third pin in the second substrate can just be exposed.
440: by the first pin and second pin binding connection, obtaining array substrate.
First pin and second pin are aligned and bind connection, the first pin and second on the first substrate after connection
Second pin on substrate is due to being connected, so that the array substrate formed after binding is displayed for.
The array substrate of method preparation through this embodiment, so that the battle array as made of first substrate and the second substrate binding
Column substrate has function identical with existing array substrate, while effectively reducing occupied by scan drive circuit and binding region
Rim space, be conducive to the screen accounting for further increasing screen, can also substantially reduce the pressure drop of cabling, while what is separated sets
Meter can be by the first substrate of display is used for and the second substrate with turntable driving function realizes individually management control, can also have
Effect reduces maintenance cost.
In one embodiment, preparing first substrate in the first substrate includes:
The first peeling layer, the first substrate layer 210, the first channel layer 220, the first gate insulation are sequentially prepared in the first substrate
Layer 230, first grid layer 240, the first separation layer 250；In the first substrate layer 210, the first channel layer 220, the first gate insulation layer
230, the first via hole is etched on first grid layer 240 and the first separation layer 250.
In simple terms, the first peeling layer, the first substrate layer are successively prepared in the first substrate using existing technical method
210, the first channel layer 220, the first gate insulation layer 230, first grid layer 240, the first separation layer 250, then in these preparations
The first via hole is etched using such as photoetching technique on good layer, the first via hole is reserved to prepare the first pin below
Space out.
The deposited metal in the first via hole forms the first metallic vias and the first pin.
Deposited metal in the first via hole in above-mentioned steps, metal can be first deposited upon the position nearest from first substrate
It sets, is exactly the first pin after the first substrate is stripped；Then metal will continue to deposit the first metallic vias, metallic vias
For forming access between the first pin and subsequent light emitting device layer.
Planarization layer, light emitting device layer and encapsulated layer are prepared on first separation layer.
After having carried out metal deposition process, planarization layer, hair are prepared using existing technology on the layer prepared before
Optical device layer and encapsulated layer, these layers are all the display function services for first substrate.
The first substrate of method preparation in the present embodiment passes through provided with the first pin being connected with light emitting device layer
First pin is tied up with the second pin in the second substrate and is connect, and realizes the due function of array substrate, and further increase screen
The screen accounting of curtain.
In one embodiment, the second substrate is prepared in the second substrate includes:
Be sequentially prepared in the second substrate peeling layer, substrate layer 310, channel layer 320, gate insulation layer 330, grid layer 340,
Separation layer 350；The second mistake is etched on substrate layer 310, channel layer 320, gate insulation layer 330, grid layer 340 and separation layer 350
Hole.
In simple terms, peeling layer, substrate layer 310, channel are successively prepared in the second substrate using existing technical method
Then layer 320, gate insulation layer 330, grid layer 340 and separation layer 350 use such as photoetching technique on the layer that these are prepared
The second via hole is etched, the second via hole is the space reserved to prepare third pin below.
The deposited metal in the second via hole forms the second metallic vias, third pin and second pin.
Deposited metal in the second via hole in above-mentioned steps, metal can be first deposited upon the position nearest from the second substrate
It sets, it is corresponding to expose third pin after the second substrate is stripped；Then metal will continue to heavy along the direction far from the second substrate
Product, metallic vias namely second be connected interconnection line, third be connected interconnection line, for second pin, scan drive circuit and
Access is formed between third pin；Second pin is formed in side of the separation layer 350 far from the second substrate.
Organic layer is prepared in the second substrate.
In the top layer of the second substrate, prepare organic layer, for during subsequent binding, provide certain buffering and
Insulation performance.
Organic layer is etched, to expose second pin.
The organic layer prepared is etched, until exposing second pin, second pin is for carrying out with the first pin
Binding connection, therefore the etching of organic layer is also to etch according to identical as the shape of the first pin.
The second substrate prepared in the present embodiment again, first substrate are real by the second pin and third pin of the second substrate
The existing due function of array substrate, and further increase the screen accounting of screen.And it is a large amount of empty due to existing in the second substrate
Between, be conducive to suitably increase trace width, to reduce the pressure drop of cabling.
In one embodiment, include: by the first pin and second pin binding connection
In the binding junction of the first pin and second pin, anisotropic conductive film is set.
Binding between first pin and second pin needs good conduction, therefore, connects in the binding of two pins
Place's setting anisotropic conductive film is connect, this conductive film is a kind of only conductive in one direction, and very big in other direction resistance
Or almost nonconducting special conducting resinl, it is mainly used for electronic component manufacture and assembling process, makes closely two conductive connections
Point will not generate the short circuit between route.
Pressure is applied to first substrate and the second substrate, so that the two is bound together.
Anisotropic conductive film after setting completed, pressure is applied respectively to first substrate and the second substrate, to allow two
The edge surrounding of a substrate is adhered to each other, to complete the binding of first substrate and the second substrate.
The method of the present embodiment, by binding region be added anisotropic conductive film, thus increase first substrate and
The conductive capability of the second substrate also ensures the short-circuit conditions that will not be generated between route between two substrates, increases the present invention
Array substrate safety and stability.
In one embodiment, the preparation method of array substrate further include: in being bonded to each other for first substrate and the second substrate
Region in addition to edge binding area Optical transparent adhesive is set.
Specifically, in first substrate and the binding procedure of the second substrate, in addition to anisotropic is arranged in binding region
Except conductive film, Optical transparent adhesive can be set in other regions, the optical clear of large area is used on the basis of original
Glue adheres to two substrates, and the fastness of the array substrate after can greatly increasing adherency further increases array substrate
Stability and reliability.
According to an aspect of the present invention, a kind of display device is provided, including above-mentioned array substrate.
Specifically, display device can be the common devices such as mobile phone, computer, be also possible to display panel.
Array substrate of the invention, be by made of first substrate and the second substrate binding, using three-dimensional stack manner,
The width at array substrate edge is effectively reduced, and then reduces the border width of display panel, is conducive to further increase screen
Screen accounting, substrate that the design that also can be effectively reduced the pressure drop of cabling, while separating is displayed for and for scanning
The substrate of driving realizes individually management control, also can effectively reduce maintenance cost.Therefore array substrate of the invention can be applied
On the display panel of any required array substrate, and in the display device of any required array substrate, such as TV, hand
Machine, tablet computer etc., any display device for applying array substrate of the present invention, all should belong to protection scope of the present invention.
Fig. 5 show the flow diagram of the preparation method for the array substrate that an exemplary embodiment of the invention provides, should
Each step in preparation method has carried out detailed statement in explanation above-mentioned, therefore each step is not reinflated superfluous
It states.The preparation method includes:
510: the first peeling layer, the first substrate layer, the first channel layer, the first gate insulation are sequentially prepared in the first substrate
Layer, first grid layer, the first separation layer.
515: being etched on the first substrate layer, the first channel layer, the first gate insulation layer, first grid layer and the first separation layer
First via hole.
520: the deposited metal in the first via hole forms the first metallic vias and the first pin.
525: preparing planarization layer, light emitting device layer and encapsulated layer on first separation layer.
530: the first substrate of removing obtains first substrate.
540: peeling layer, substrate layer, channel layer, gate insulation layer, grid layer, separation layer are sequentially prepared in the second substrate.
545: the etching vias on substrate layer, channel layer, gate insulation layer, grid layer and separation layer.
550: deposited metal in the vias forms metallic vias, pin and pin.
555: organic layer is prepared in the second substrate.
560: etching organic layer, to expose second pin.
565: the second substrate of removing obtains the second substrate.
570: anisotropic conductive film being set in the binding junction of the first pin and second pin, in first substrate and the
The region setting Optical transparent adhesive in addition to edge binding area of two substrates being bonded to each other, applies first substrate and the second substrate
Plus-pressure, so that the two is bound together.
The array substrate prepared using the present exemplary embodiment, when preparing the second substrate by metal deposit and
The modes such as removing prepare second pin and third pin, by the first pin of preparation when preparing first substrate, are formed
Pixel arrangement area and the direct access of second pin, and second pin, scan drive circuit and third pin in the second substrate
There is also accesses, therefore entire array substrate is the equal of that it is wide to effectively reduce array substrate edge using three-dimensional stack manner
Degree, can increase the screen accounting of screen, can also substantially reduce the pressure drop of cabling, while the design separated can be to for display
Substrate and for turntable driving substrate realize individually management control, can effectively reduce maintenance cost.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, made any modification, equivalent replacement etc. be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of array substrate, which is characterized in that including the first substrate being stacked and the second substrate, wherein
The first substrate includes first edge binding area and pixel arrangement area, and the pixel arrangement area is provided with pixel electricity
Road, first edge binding area are formed with several first pins being arranged towards the second substrate, the pixel circuit
It is electrically connected with several described first pins；
The second substrate includes second edge binding area and circuit trace area, the circuit trace area include for it is described
The scan drive circuit of pixel circuit electrical connection, if second edge binding area is formed with towards first substrate setting
Dry second pin, the scan drive circuit are electrically connected with several described second pins,
Several described first pins and several described second pin bindings connect.
2. array substrate according to claim 1, which is characterized in that the second substrate further includes third binding area, institute
It states third binding area and a side surface of the first substrate is provided with several third pins in the second substrate, it is described
Third pin is used to bind with external circuit and connect.
3. array substrate according to claim 2, which is characterized in that third binding area is set to the second substrate
Middle position.
4. array substrate according to claim 1, which is characterized in that the pixel circuit by the first conductive interconnection line with
First pin be connected, it is described first conducting interconnection line be scan line, data line, reference voltage line it is one or more.
5. array substrate according to claim 1, which is characterized in that the scan drive circuit passes through the second conductive interconnection
Line is connected with the second pin, and interconnection line is connected by the third for the scan drive circuit and the third pin connects
It connects.
6. array substrate according to claim 5, which is characterized in that include that at least one film is brilliant in the second substrate
Body pipe, the third pin are connected to the thin film transistor (TFT).
7. array substrate according to claim 6, which is characterized in that each thin film transistor (TFT) includes channel layer, institute
It states third pin to contact with a side surface of the channel layer towards the first substrate, and the third pin is from described second
Substrate is drawn far from a side surface of the first substrate.
8. array substrate according to claim 1, which is characterized in that the second substrate includes the multilayer knot being stacked
Structure, the side of the multilayered structure towards the first substrate are provided with organic layer, and the second pin is set to described organic
In layer.
9. array substrate according to claim 1, which is characterized in that be provided at least one set first on the first substrate
Pin, and the first pin described in every group includes described in several of the extending direction arrangement along the respective side edge of the first substrate
First pin；And/or
At least one set of second pin is provided in the second substrate, and second pin described in every group includes along the second substrate
Respective side edge extending direction arrangement several described second pins.
10. a kind of display device, including array substrate as claimed in any one of claims 1-9 wherein.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910252188.1A CN109949705A (en) | 2019-03-29 | 2019-03-29 | A kind of array substrate and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910252188.1A CN109949705A (en) | 2019-03-29 | 2019-03-29 | A kind of array substrate and display device |
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| CN109949705A true CN109949705A (en) | 2019-06-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910252188.1A Pending CN109949705A (en) | 2019-03-29 | 2019-03-29 | A kind of array substrate and display device |
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| CN112366220A (en) * | 2020-11-10 | 2021-02-12 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
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