CN109947019A - The processing unit and concurrent working control method of train network input-output system - Google Patents
The processing unit and concurrent working control method of train network input-output system Download PDFInfo
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Abstract
The present invention provides the processing unit and concurrent working control method of a kind of train network input-output system, two network interfaces and two CPU are connected to chips of Ethernet exchange, two CPU are connected to programming device, programming device connects parallel bus interface by bus driver, passes sequentially through Interbus protocol chip with serial ports transceiving chip and connects Interbus bus interface；Two SPI interfaces are respectively connected to two CPU, I/O interface connects programming device, that is: by using double CPU for redundant framework, the cpu chip of two master-slave modes or the mode that works asynchronously, shared memory between two chips are integrated on one piece of board, and arbitration management is realized by logic chip, effectively increase the safety and flexibility of input-output system, in addition, efficiently solving the problems, such as that compatibility is bad by integrated interbus communication interface and parallel bus interface.
Description
Technical field
The present invention relates to Train Control Technology field more particularly to a kind of processing for train network input-output system
Device and concurrent working control method.
Background technique
Modernization EMU generallys use train network control system and is detected, controlled and diagnosed to vehicle, as dynamic
The nerve center of vehicle group, train network control system can control and manage train traction braking car door illumination etc. it is each
Subsystem.
Train network control system includes: central control unit, repeater, human-computer interaction interface and input-output system etc.
Multiple equipment.Wherein, input-output system number is most, is distributed in the Electric Appliance Cabinet of each compartment, mainly completes TCMS system
With vehicle side unintelligent device interface.The control of a large amount of vehicle intra subsystems (traction, braking, lamp control) and signal acquisition all pass through
Rigid line is aggregated into the electrical cabinet of each compartment, and the phase intercommunication with motor-car network backbone net is then completed by input-output system
Letter, the performance of input-output system are directly related to monitoring of the train central control unit to each vehicle unit equipment state.And
The compatible bad and safety of existing input-output system and flexibility are lower.
Summary of the invention
In view of this, the present invention provides a kind of processing unit for train network input-output system and control is double
The method of CPU concurrent working integrates two master-slave modes or synchronous work using double CPU for redundant framework on one piece of board
The cpu chip of operation mode, shared memory between two chips, and arbitration management is realized by logic chip, it effectively increases
The safety and flexibility of input-output system, in addition, by integrated interbus communication interface and parallel bus interface, effectively
Solve the problems, such as that compatibility is bad.
To achieve the goals above, the present invention adopts the following technical scheme:
In a first aspect, providing a kind of processing unit for train network input-output system, comprising: front port module,
Processing module, arbitration management module and backplane interface module,
The front port module includes: two network interfaces and chips of Ethernet exchange；
The processing module includes: two CPU；
The arbitration management module includes: programming device；
The backplane interface module includes: bus driver, Interbus protocol chip, serial ports transceiving chip, parallel bus
Interface, Interbus bus interface, two SPI interfaces and I/O interface；
Wherein, each network interface is connected to corresponding CPU by the chips of Ethernet exchange, and two CPU connect
It is connected to the programming device,
The programming device connects parallel bus interface by bus driver, and passes sequentially through Interbus protocol chip
Interbus bus interface is connected with serial ports transceiving chip；
Each SPI interface is respectively connected to corresponding CPU, which connects the programming device.
Further, front port module further include: two LED display units, two LED display units are respectively connected to
Two CPU, for showing the working condition of CPU.
Further, processing module further include: crystal oscillator unit, voltage management unit and RC unit.
Further, front port module further include: four network transformers, two network interfaces pass through two nets respectively
Network transformer is connected to the chips of Ethernet exchange, and two CPU pass through two network transformers respectively and are connected to the Ethernet
Exchanger chip.
Further, the backplane interface module further include: electrical level transferring chip, in the Interbus bus interface, the SPI
An electrical level transferring chip is respectively provided with before interface and the I/O interface.
Further, which uses 485 transceivers.
Further, which uses SUPI3 chip.
Further, arbitration management module further include: memory, the memory connect the programming device.
Further, which uses FPGA or CPLD.
Second aspect provides a kind of method for controlling dual processors concurrent working, inputs applied to above-mentioned for train network
The processing unit of output system, the control logic in CPU includes multiple program segments, is inserted into synchronization node journey after each program segment
The method of sequence, the control dual processors concurrent working includes:
Two CPU initialize and the synchronization signal of two CPU is driven to low level；
Programming device initialize and the enabling signal of programming device is driven to low level；
CPU execution phase simultaneously triggers the synchronization node program after the program segment, the synchronization node journey after the completion of execution
Sequence includes: that the synchronization signal is driven to high level, judges whether enabling signal is high level, if then driving the synchronization signal
It moves as low level and executes next program segment；
After FPGA receives the high level synchronization signal of a CPU, judge whether to receive another CPU's in preset period of time
High level synchronization signal, if enabling signal is then driven to high level.
Provided by the present invention for the processing unit of train network input-output system, comprising: front port module, processing mould
Block, arbitration management module and backplane interface module；The front port module includes: two network interfaces and Ethernet switch
Chip；The processing module includes: two CPU；The arbitration management module includes: programming device；The backplane interface module includes:
Bus driver, Interbus protocol chip, serial ports transceiving chip, parallel bus interface, Interbus bus interface, two
SPI interface and I/O interface；Wherein, two network interfaces and two CPU are connected to the chips of Ethernet exchange, and two
CPU is connected to the programming device, which connects parallel bus interface by bus driver, passes sequentially through
Interbus protocol chip connects Interbus bus interface with serial ports transceiving chip；Two SPI interfaces are respectively connected to two
CPU, the I/O interface connect the programming device, it may be assumed that by using double CPU for redundant framework, two masters are integrated on one piece of board
From operating mode or the cpu chip for the mode that works asynchronously, shared memory between two chips, and realized by logic chip secondary
Cut out management, effectively increase the safety and flexibility of input-output system, in addition, by integrated interbus communication interface and
Parallel bus interface efficiently solves the problems, such as that compatibility is bad.
For above and other objects, features and advantages of the invention can be clearer and more comprehensible, preferred embodiment is cited below particularly,
And cooperate institute's accompanying drawings, it is described in detail below.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the application
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.In the accompanying drawings:
Fig. 1 shows structural block diagram one of the embodiment of the present invention for the processing unit of train network input-output system；
Structural block diagram two Fig. 2 shows the embodiment of the present invention for the processing unit of train network input-output system；
Fig. 3 shows partial circuit diagram of the embodiment of the present invention for the processing unit of train network input-output system；
Fig. 4 shows the embodiment of the present invention for synchronous control in the CPU of the processing unit of train network input-output system
Method flow diagram one processed；
Fig. 5 shows the embodiment of the present invention for synchronous control in the FPGA of the processing unit of train network input-output system
Method flow diagram one processed；
Fig. 6 shows the embodiment of the present invention for synchronous control in the CPU of the processing unit of train network input-output system
Method flow diagram two processed；
Fig. 7 shows the embodiment of the present invention for synchronous control in the FPGA of the processing unit of train network input-output system
Method flow diagram two processed；
Fig. 8 shows in the embodiment of the present invention register in FPGA.
Specific embodiment
In order to make those skilled in the art more fully understand application scheme, below in conjunction in the embodiment of the present application
Attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is only
The embodiment of the application a part, instead of all the embodiments.Based on the embodiment in the application, ordinary skill people
Member's every other embodiment obtained without making creative work, all should belong to the model of the application protection
It encloses.
It should be noted that term " includes " and " tool in the description and claims of this application and above-mentioned attached drawing
Have " and their any deformation, it is intended that cover it is non-exclusive include, for example, containing a series of steps or units
Process, method, system, product or equipment those of are not necessarily limited to be clearly listed step or unit, but may include without clear
Other step or units listing to Chu or intrinsic for these process, methods, product or equipment.
It should be noted that in the absence of conflict, the features in the embodiments and the embodiments of the present application can phase
Mutually combination.The application is described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
Input-output system in existing train network control system is communicated using interbus bus as device bus,
Single CPU is cooperated to work, compatible bad and safety and flexibility are lower.
To solve above-mentioned technical problem in the prior art, the embodiment of the present invention provides a kind of defeated for train network input
The processing unit of system out integrates two master-slave modes or synchronization by using double CPU for redundant framework on one piece of board
The cpu chip of operating mode, shared memory between two chips, and arbitration management is realized by logic chip, it effectively improves
The safety and flexibility of input-output system, in addition, having by integrated interbus communication interface and parallel bus interface
Effect solves the problems, such as that compatibility is bad.
Fig. 1 shows structural block diagram one of the embodiment of the present invention for the processing unit of train network input-output system.
As shown in Figure 1, the processing unit (alternatively referred to as central processing unit board) for being used for train network input-output system includes:
Front port module 10, processing module 20, arbitration management module 30 and backplane interface module 40.
Specifically, which provides Ethernet interface, is used for external equipment (such as computer, laptop
Or each subsystem in train network) access board, with board in CPU interact.
The processing module 20 is for handling its received signal, and the signal that exports that treated.
The arbitration management module 30 is used to control the working sequence and working condition of the processing module 20, is specifically used for processing
The scheduling and management of two CPU in module 20.The arbitration management module 30 and the processing module 20 are believed by some buses and I/O
Number connection.
The backplane interface module 40 is for providing multiple interfaces, so as to logical by interface with each subsystem in train network
Letter connection.
Wherein, the front port module 10 include: two network interfaces and for make receive data carry out conflict-free
Chips of Ethernet exchange.The processing module 20 includes: CPU1 and CPU2.The arbitration management module 30 includes: Programmable
Part.The backplane interface module 40 includes: that bus driver, Interbus protocol chip, serial ports transceiving chip, parallel bus connect
Mouth, Interbus bus interface, two SPI interfaces and I/O interface.
Two network interfaces and two CPU are connected to the chips of Ethernet exchange (such as KSZ8895), and two CPU are equal
It is connected to the programming device.The programming device connects parallel bus interface by bus driver, passes sequentially through
Interbus protocol chip connects Interbus bus interface with serial ports transceiving chip.Two SPI interfaces are respectively connected to two
CPU, the I/O interface connect the programming device.
In addition, 485 transceivers can be used in the serial ports transceiving chip.SUPI3 chip can be used in the Interbus protocol chip.
The programming device can be used FPGA or CPLD and realize, such as EP4CE15Fxx.
ARM microcontroller (such as STM32F4xx) realization can be used in CPU.
In the following, citing is illustrated the working principle of processing unit provided in an embodiment of the present invention:
When laptop needs two CPU in access process device, which can be connected by cable
Two network interfaces are connect, are interacted respectively with CPU1 and CPU2 by chips of Ethernet exchange, programming device can be controlled
CPU1 and CPU2 processed work in active-standby mode or synchronous working mode.
When a certain subsystem in train network is needed through parallel bus interface access process device, by the subsystem
It is connected to the parallel bus interface by data line, data are transmitted to programmable by the parallel bus interface, bus driver
Device is operate on active-standby mode or synchronous mode according to dual processors by programming device and is transmitted to the data corresponding
CPU is handled, and data that treated feed back to the subsystem again.
It is worth noting that the processing and control of data are carried out by a CPU when two CPU work are in master slave mode,
Another CPU is in hot standby state, can acquire the data of shared memory, but does not participate in control directly.Work is in synchronization
When mode, synchronization mechanism are as follows: certain synchronization node can be set in the logical internal of two CPU operation, after synchronization node reaches
Inform that FPGA, FPGA give two CPU synchronism output one after receiving two CPU and reaching certain synchronization node by I/O
Enabling signal allows CPU to carry out next step operation.Operation result can be sent respectively to FPGA, FPGA judgement by data/address bus
The consistency of operation result.
Interface section will realize interbus communication function, the communication interface of SUPI3 chip is connected to by FPGA, then
485 signals are obtained by differential driving chip (such as SP490).
Through the above technical solution it is known that the processing provided by the present invention for train network input-output system fills
It sets by using double CPU for redundant framework, the CPU core of two master-slave modes or the mode that works asynchronously is integrated on one piece of board
Piece, shared memory between two chips, and arbitration management is realized by logic chip, effectively increase input-output system
Safety and flexibility, integrated level is higher, in addition, effectively being solved by integrated interbus communication interface and parallel bus interface
It has determined compatible bad problem, favorable expandability.
In addition, processing unit provided in an embodiment of the present invention, each CPU picks out a SPI interface, for do not need it is double
CPU principal and subordinate or it is synchronous when, directly interacted by the SPI interface with each subsystem, be equivalent to the centre of a binary channels dual processors
Unit board is managed, each CPU executes respective task respectively, thereby increases the processing unit of the train network input-output system
Function, improve versatility.
Also, two CPU can realize master-slave mode and concurrent operating modes under the control of the programming device,
And two operating modes can be replaced according to actual task demand, further improve the flexible in application of processing unit
Property, moreover, completing the scheduling and management of two CPU using programming device, it can be realized quick processing.
In an alternative embodiment, referring to fig. 2, which can also include: two LED display units,
Two LED display units are respectively connected to two CPU, for showing the working condition of CPU.
In an alternative embodiment, which further includes the peripheral circuit 1 and and CPU2 with CPU1 cooperation
The peripheral circuit 2 of cooperation, the peripheral circuit 1 and peripheral circuit 2 include: crystal oscillator unit, voltage management unit and RC unit
Deng.
In an alternative embodiment, the front port module further include: four network transformers (such as HX1188), two
Network interface is connected to the chips of Ethernet exchange by corresponding network transformer respectively, and two CPU pass through respectively
Two network transformers are connected to the chips of Ethernet exchange.
Specifically, which couples for signal level, can effectively enhance signal, make its transmission range more
Far；In addition, die terminals can also be made to be isolated from the outside, anti-interference ability is improved, protection chip exempts from the interference such as lightning stroke, and adapts to
Varying level improves compatibility.
In an alternative embodiment, which can also include: electrical level transferring chip, at this
It is respectively provided with an electrical level transferring chip before Interbus bus interface, the SPI interface and the I/O interface, for matching outside
Level standard effectively increases interface compatibility and stability.
In an alternative embodiment, which can be used SN74ALVC164245.
In an alternative embodiment, which can also include: memory, alternatively referred to as shared to deposit
It stores up chip (NVRAM), which connects the programming device by bus, and FPGA can directly access NVRAM, two CPU
NVRAM can also be accessed by FPGA.
Fig. 3 shows partial circuit diagram of the embodiment of the present invention for the processing unit of train network input-output system,
The fractional refinement that the circuit between FPGA and one of CPU and FPGA and interface has been shown in particular illustrates, because of FPGA and two
Signal relation between a CPU is consistent, therefore below by taking one of CPU as an example, it provides an interface between CPU and FPGA and closes
System, bus portion 21 are ISA signal, to include address signal Addr [23:17], SA [19:0], MEMCS16, read-write
(MEMR#, MEMW#), data/address bus SD [15:0], clock signal sysclk, waiting signal IOCHRDY and interrupt signal IRQ etc..
The signal that the part I/O 22 includes has CPU life signal (life), CPU main signal (Ismaster), from setting signal
(Setslave), synchronization node signal (sync), enabling signal (start), reset signal (rst), stop signal (stop).
The bus portion 23 of FPGA and external bus interface is identical as the content that bus portion 21 includes, and to pass through level-one bus driver
Output.In addition, I/O signal mainly includes that piece selects cs [5:0], reset signal rst and common input and output GPIO, this part letter
Number external interface is transmitted to by electrical level transferring chip.All bus interface are connected to the bus management program mould inside FPGA
Block, life, Ismaster, Setslave are connected to the diagnostic program module inside FPGA, sync, start, rst, stop signal
The synchronous setting program module being connected to inside FPGA.The serial ports output that CPU can be mapped inside FPGA, is connected to interbus association
Chip 24 is discussed, then is connected to external backboard by 485 transceivers 25.
In addition, the embodiment of the present invention also provides a kind of method for controlling dual processors concurrent working, applied to above-mentioned for arranging
The processing unit of vehicle netbios, the control logic in CPU includes multiple program segments, is inserted into after each program segment
The method of synchronization node program, the control dual processors concurrent working includes:
1. couple two CPU initialize and the synchronization signal of two CPU are driven to low level；
2. pair programming device initialize and the enabling signal of programming device is driven to low level；
3.CPU execution phase simultaneously triggers the synchronization node program after the program segment, the synchronization node after the completion of execution
Program includes: that the synchronization signal is driven to high level, judges whether enabling signal is high level, if then by the synchronization signal
It is driven to low level and executes next program segment；
After 4.FPGA receives the high level synchronization signal of a CPU, judge whether to receive another CPU in preset period of time
High level synchronization signal, if enabling signal is then driven to high level.
Specifically, when two CPU synchronous workings, can specifically two kinds of control modes be used:
1. initializing after powering on to CPU1 and CPU2, synchronization signal is driven to low level.FPGA initialization is internal
Register is 0, and enabling signal is low level.Synchronization node, the effect of synchronization node are previously inserted in the software of CPU1 and CPU2
It is high level for driving synchronization signal output, while waits whether enabling signal is high level.FPGA receives the height of some CPU
Start timing after level synchronization signal, and wait the high level synchronization signal of another CPU, if in time Tdown still
The high level synchronization signal of only one right CPU then outputting alarm signal and judges whether to need to close based on the actual application requirements
Close CPU etc..If the high level synchronization signal of two CPU all reaches in time Tdown, FPGA can be delayed a time
Enabling signal is exported high level by tdelay.CPU receive synchronization signal can be exported after high level enabling signal it is low, after
Continuous calculation process.
2. initializing after powering on to CPU1 and CPU2, synchronization signal is driven into low level.FPGA is initialized inside it
All SYN registers be 0, enabling signal is low level.Synchronization node is previously inserted in the software of CPU1 and CPU2, each
Synchronization node corresponds to a SYN register, and the effect of synchronization node is when being triggered by the corresponding synchronization in the area FPGAbuffer
Register write-in 1, while waiting whether enabling signal is high level.That is: it is triggered after a certain CPU has executed a program segment
One synchronization node, at this point, output high level synchronization signal, after FPGA is connected to the high level synchronization signal, interior corresponding CPU
The signal of SYN register of the synchronization node can change, become 1 from 0.
FPGA starts timing after the corresponding SYN register signal intensity of some CPU, and waits another CPU pairs
The SYN register signal intensity answered, if it is 1 that two SYN registers are inconsistent in time Tdown, outputting alarm letter
Number and can judge whether based on the actual application requirements close CPU.If two SYN registers are simultaneously in time Tdown
1, then FPGA can be delayed a time tdelay, and enabling signal is exported high level.CPU can be incited somebody to action after receiving high level enabling signal
Synchronization signal output be it is low, into subsequent calculation process.
In the following, dual processors synchronously control is described in detail in conjunction with Fig. 4 to Fig. 8.
As shown in Figure 4 and Figure 5, above-mentioned synchronous control mode 1 is shown in detail.
Fig. 4 is the synchronisation control means flow chart one in CPU, and the control logic in CPU includes multiple program segments, Mei Gecheng
The identical synchronization node program after executing initialization of sequence Duan Houjun insertion, CPU can trigger this after having executed a certain program segment
Synchronization node program, the synchronization node program specifically: setting synchronization signal sync be 1, judge enabling signal start whether be
1, continue judgement circulation if not 1 and execute, until enabling signal start is 1, into next step program segment.
Fig. 5 is synchronisation control means flow chart one in FPGA, and FPGA starting after executing initialization is counted and waited point
High level synchronization signal sync1 and high level synchronization signal sync2 not from CPU1 and CPU2, receive one of them and then represent
CPU synchronization request starts, if time-out does not have synchronization request, enters timeout treatment.When receiving high level synchronization signal sync1
Afterwards, start time synchronisation, if having received high level synchronization signal sync2 in preset period of time, FPGA output high level is opened
Dynamic signal start informs that two CPU can carry out next step operation, and if it exceeds preset period of time receives sync2 not yet, then
Into timeout treatment.
As shown in Figure 6 and Figure 7, above-mentioned synchronous control mode 2 is shown in detail.
Fig. 6 shows the embodiment of the present invention for synchronous control in the CPU of the processing unit of train network input-output system
Method flow diagram two processed；Referring to Fig. 6, the control logic in CPU includes multiple program segments, is inserted into after each program segment identical
The synchronization node program after executing initialization, CPU can trigger the synchronization node program after having executed a certain program segment, synchronous
Node procedure number is cumulative, is arranged the SYN register inside FPGA by write signal, the offset of register address number with it is synchronous
Node sequence number is consistent.
The synchronization node program specifically: by corresponding SYN register be written 1, judge enabling signal start whether be
1, continue judgement circulation if not 1 and execute, enters next step program segment when enabling signal start is 1.
Fig. 7 shows the embodiment of the present invention for synchronous control in the FPGA of the processing unit of train network input-output system
Method flow diagram two processed；Referring to Fig. 7, FPGA starting after executing initialization counts and checks SYN register (CPU1 corresponding A
Register, CPU2 correspond to B-register), there is one to start to represent CPU synchronization request if 1 if two registers, if time-out does not have
There is synchronization request, then enters timeout treatment.After receiving synchronization request, start time synchronisation, and whether judge two registers
All it is 1, is all that 1 explanation, two CPU reach the same synchronization node, then FPGA exports high level enabling signal start and informs CPU
Next step operation, while register number cumulative 1 can be carried out, convenient for checking synchronization request next time, and if it exceeds default
After period, two registers are not all to enter timeout treatment then for 1.
Fig. 8 shows in the embodiment of the present invention register in FPGA.It is respectively two CPU settings referring to Fig. 8, inside FPGA
Corresponding SYN register, also, each CPU corresponds to multiple SYN registers, for respectively recording corresponding synchronous section
The triggering state of point.
It, can through the above technical solution it is known that the present invention provides two different dual processors synchronously control schemes
It effectively realizes the synchronously control of dual processors, and makes the synchronization accuracy of dual processors high, and then effectively increase the place of processing unit
Manage precision.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for system reality
For applying example, since it is substantially similar to the method embodiment, so being described relatively simple, related place is referring to embodiment of the method
Part explanation.
The above description is only an example of the present application, is not intended to limit this application.For those skilled in the art
For, various changes and changes are possible in this application.All any modifications made within the spirit and principles of the present application are equal
Replacement, improvement etc., should be included within the scope of the claims of this application.
Claims (10)
1. a kind of processing unit for train network input-output system characterized by comprising front port module, processing
Module, arbitration management module and backplane interface module,
The front port module includes: two network interfaces and chips of Ethernet exchange；
The processing module includes: two CPU；
The arbitration management module includes: programming device；
The backplane interface module includes: that bus driver, Interbus protocol chip, serial ports transceiving chip, parallel bus connect
Mouth, Interbus bus interface, two SPI interfaces and I/O interface；
Wherein, each network interface is connected to corresponding CPU by the chips of Ethernet exchange, and two CPU are connected to
The programming device,
The programming device by bus driver connect parallel bus interface, and pass sequentially through Interbus protocol chip and
Serial ports transceiving chip connects Interbus bus interface；
Each SPI interface is respectively connected to corresponding CPU, and the I/O interface connects the programming device.
2. the processing unit according to claim 1 for train network input-output system, which is characterized in that before described
Interface module further include: two LED display units, two LED display units are respectively connected to two CPU, for showing CPU's
Working condition.
3. the processing unit according to claim 1 for train network input-output system, which is characterized in that the place
Manage module further include: crystal oscillator unit, voltage management unit and RC unit.
4. the processing unit according to claim 1 for train network input-output system, which is characterized in that before described
Interface module further include: four network transformers, two network interfaces pass through respectively two network transformers be connected to it is described with
Too network switch chip, two CPU pass through two network transformers respectively and are connected to the chips of Ethernet exchange.
5. the processing unit according to claim 1 for train network input-output system, which is characterized in that the back
Plate interface module further include: electrical level transferring chip connects in the Interbus bus interface, the SPI interface and the I/O
An electrical level transferring chip is respectively provided with before mouthful.
6. the processing unit according to claim 1 for train network input-output system, which is characterized in that the string
Mouth transceiving chip uses 485 transceivers.
7. the processing unit according to claim 1 for train network input-output system, which is characterized in that described
Interbus protocol chip uses SUPI3 chip.
8. the processing unit according to claim 1 for train network input-output system, which is characterized in that described secondary
Cut out management module further include: memory, the memory connect the programming device.
9. the processing unit according to claim 1 for train network input-output system, which is characterized in that it is described can
Programming device uses FPGA or CPLD.
10. a kind of method for controlling dual processors concurrent working, which is characterized in that be applied to as described in any one of claim 1 to 9
The processing unit for train network input-output system, the control logic in CPU includes multiple program segments, each program segment
It is inserted into synchronization node program afterwards, the method for the control dual processors concurrent working includes:
Two CPU initialize and the synchronization signal of two CPU is driven to low level；
Programming device initialize and the enabling signal of programming device is driven to low level；
CPU execution phase simultaneously triggers the synchronization node program after the program segment, the synchronization node program after the completion of execution
Include: that the synchronization signal is driven to high level, judges whether enabling signal is high level, if then driving the synchronization signal
It moves as low level and executes next program segment；
After FPGA receives the high level synchronization signal of a CPU, judge whether the height electricity that another CPU is received in preset period of time
Flat synchronization signal, if enabling signal is then driven to high level.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN112810647A (en) * | 2021-01-06 | 2021-05-18 | 中车唐山机车车辆有限公司 | Motor train unit and illumination control system and method thereof |
| CN112810647B (en) * | 2021-01-06 | 2022-07-22 | 中车唐山机车车辆有限公司 | Motor train unit and illumination control system and method thereof |
| CN113032325A (en) * | 2021-03-09 | 2021-06-25 | 中车青岛四方车辆研究所有限公司 | Processor board card, control method thereof, and storage medium |
| CN113050485A (en) * | 2021-03-12 | 2021-06-29 | 山西国惠光电科技有限公司 | Core control platform for intelligent control system |
| CN113050485B (en) * | 2021-03-12 | 2023-07-04 | 山西国惠光电科技有限公司 | Core control platform for intelligent control system |
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