CN109906507A - The semiconductor devices of multi-chip structure and the semiconductor module for using it - Google Patents
The semiconductor devices of multi-chip structure and the semiconductor module for using it Download PDFInfo
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- CN109906507A CN109906507A CN201780066704.0A CN201780066704A CN109906507A CN 109906507 A CN109906507 A CN 109906507A CN 201780066704 A CN201780066704 A CN 201780066704A CN 109906507 A CN109906507 A CN 109906507A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L23/00—Details of semiconductor or other solid state devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/112—Mixed assemblies
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Abstract
Disclose the semiconductor devices of multi-chip structure and the semiconductor module of the semiconductor devices using the multi-chip structure.The unit chip of such as source electrode driver is configured to the semiconductor devices with multi-chip structure, so that the packing density of adding unit chip, and input pad and the o pads structure having the same of unit chip or different structures, to increase packing density by multiple choices.
Description
Technical field
This disclosure relates to semiconductor devices, and more particularly, to the multi-chip structure that can improve packing density
Semiconductor devices, and the semiconductor module of the semiconductor devices using the multi-chip structure.
Background technique
Display device includes display panel, driver, sequence controller etc., wherein pixel passes through in display panel
OLED, LED or LCD realize that driver is used to drive the pixel on screen, and sequence controller is used to control the operation of driver.
In general, driver can be divided into source electrode driver and gate drivers, wherein source electrode driver is mentioned to the pixel of display panel
For source drive signal corresponding with data, gate drivers provide grid signal line by line on the screen.
Wherein, according to the size of screen and resolution ratio, multiple source electrode drivers can be arranged on the side of display panel, together
When source electrode driver be separated from each other.
For example, source electrode driver is bound to display surface in the case where chip on glass (hereinafter referred to " COG ") scheme
The glass of plate.
In the case where COG scheme, source electrode driver is fabricated to by semiconductor chip by saw chip, and source electrode is driven
Dynamic device is bound to glass as semiconductor chip itself, without being used to encapsulating the molding or epoxy resin of (packaging)
Encapsulation.
In addition, source electrode driver can be according to the type of display panel with chip on such as film (hereinafter referred to " COF ")
Various ways are installed.
In display panel, when screen size reduces and screen resolution increases, it is arranged on the side of display panel
The density of source electrode driver gradually increase.
In the case where COG scheme, source electrode driver is bound to glass by using combination tool.Combination tool includes cloth
Set rows of multiple bonding pads.Combination tool picks up a source electrode driver for each bonding pad, makes on bonding pad
The predetermined position of the source electrode driver alignment glass of pickup, is in close contact source electrode driver and glass, and then drive source electrode
Dynamic device is bound to glass.
In the case where COG scheme, the compartment between source electrode driver installed is away from the combination weldering by combination tool
Compartment between disk is away from decision.In general, source electrode driver has rectangular shape, and by according to the dicing lane by chip
(scribe lane) divide chip area and individuation encapsulation constitute.Source electrode driver is arranged on major axes orientation embarks on journey,
And it is subsequent binding to glass.
Combine above-mentioned individual source electrode driver in the case where, combination tool require chip between have 5,000 μm or
Bigger exemplary minimum separation spacing.Therefore, four source electrode driver (length of the long side of each source electrode driver are being combined
It is 16,500 μm) in the case where, the length in conjunction with needed for four source electrode drivers is the length of the long side of four source electrode drivers
Spend three bonding pads between compartment away from summation (=4 × 16,500 μm+3 × 5,000 μm).
As described above, the minimum point between the chip needed for combining individual source electrode driver to meet combination tool simultaneously
Compartment away from the case where, deposit by the packing density for improving source electrode driver while for meeting the minimum separation spacing between chip
It is limiting.
Source electrode driver needs to have improved wiring density and improved packing density.In addition, source electrode driver needs
There are the multiple choices for installation.
Summary of the invention
Various embodiments are related to the semiconductor devices of multi-chip structure and the semiconductor devices using the multi-chip structure
Semiconductor module, with increase such as source electrode driver unit chip packing density.
Various embodiments are related to a kind of semiconductor devices and the semiconductor module using the semiconductor devices, wherein
The semiconductor devices includes the two unit chips adjacent relative to dicing lane in a semiconductor substrate with adding unit core
The packing density of piece.
Various embodiments are related to the semiconductor devices of multi-chip structure and the semiconductor device using the multi-chip structure
The semiconductor module of part, wherein in the semiconductor devices of multi-chip structure, in semiconductor processing in a semiconductor substrate
It is upper to manufacture two unit chips being same or different to each other, and be with crystalline substance by two unit chips that dicing lane is connected to each other
Piece rank carries out sawing, to be embodied as semiconductor packages.
Various embodiments are related to a kind of semiconductor module, wherein wiring is by being formed in a semiconductor substrate and wrapping
The two unit chips included in a semiconductor devices are shared, or wiring is formed in for the more of described two unit chips
In layer, make it possible to improve wiring density.
Various embodiments are related to the semiconductor devices of multi-chip structure and the semiconductor device using the multi-chip structure
The semiconductor module of part, in the semiconductor devices of multi-chip structure, two unit cores being formed in a semiconductor substrate
Piece structure having the same or different structures make it possible to improve packing density by various selections.
In embodiments, the semiconductor devices of multi-chip structure includes: first unit chip, second unit chip and draws
Film channel, wherein form the first input pad and the first o pads in first unit chip, formed in second unit chip
Second input pad and the second o pads, dicing lane is between first unit chip and second unit chip, wherein partly leads
Body device is formed in the form of semiconductor packages, in semiconductor packages, first unit chip, dicing lane and second unit chip
Longitudinal direction along the long side of first unit chip is connected to each other on the same semiconductor substrate.
In embodiments, using the semiconductor module of the semiconductor devices of multi-chip structure include: semiconductor devices and
Flexible printed circuit board, wherein semiconductor devices has rectangular shape and is formed in including the longitudinal direction along long side identical
First unit chip, dicing lane and second unit chip in semiconductor substrate, in flexible printed circuit board, semiconductor devices
It installs to bond area, and is formed with input line and output line in flexible printed circuit board, input line will be located at first end
Input terminal be connected to bond area, the output terminal being located at the second end opposite with first end is connected to knot by output line
Close region, wherein be formed in first unit chip and the first input pad for contacting with bond area and be formed in second
The second input pad contacted in unit chip and with bond area is electrically connected to the end for extending to bond area of input line,
And it is formed in first unit chip and the first o pads for contacting with bond area and is formed in second unit chip
In and the second o pads for being contacted with bond area be electrically connected to the end for extending to bond area of output line.
According to the present invention, semiconductor devices is formed with multi-chip structure, in the multi-chip structure, such as source electrode driver
Two unit chips be formed in a semiconductor substrate, so as to improve the packing density of unit chip.
In addition, according to the present invention, two unit chips being same or different to each other are in semiconductor processing one and half
It is manufactured on conductor substrate, and is embodied as semiconductor packages by two unit chips that dicing lane is connected to each other, from
And the packing density of unit chip can be improved.
In addition, according to the present invention, wiring is shared by two unit chips being formed in a semiconductor substrate, Huo Zhebu
Line is formed in the multilayer for two unit chips, makes it possible to improve the wiring density of semiconductor module.
In addition, according to the present invention, two unit chips structure having the same for being formed in a semiconductor substrate or
Different structures makes it possible to improve by various selections the packing density of unit chip.
In addition, according to the present invention, the packing density of semiconductor devices and semiconductor module is improved, so as to provide packet
The advantages of including the device design of semiconductor devices and semiconductor module.
Detailed description of the invention
Fig. 1 is the plan view for showing the preferred embodiment of semiconductor devices of multi-chip structure of the invention.
Fig. 2 is the plan view for the semiconductor substrate of the manufacturing method of the semiconductor devices of explanatory diagram 1.
Fig. 3 is the plan view for showing the preferred embodiment of semiconductor module of the semiconductor devices using Fig. 1.
Fig. 4 is the view for illustrating to combine the method for semiconductor devices by using combination tool.
Fig. 5 is the plan view for showing another embodiment of semiconductor devices of multi-chip structure of the invention.
Fig. 6 is the plan view for showing the preferred embodiment of semiconductor module of the semiconductor devices using Fig. 5.
Fig. 7 is the plan view for showing the another embodiment of semiconductor devices of multi-chip structure of the invention.
Fig. 8 is the cross-sectional view for showing the output line connection status of second unit chip CH2 of Fig. 7.
Fig. 9 is the cross-sectional view for showing the output line connection status of first unit chip CH1 of Fig. 7.
Figure 10 is the plan view for showing the another embodiment of semiconductor devices of multi-chip structure of the invention.
Specific embodiment
Hereinafter, embodiments of the present invention are described in detail with reference to the accompanying drawings.In specification and claims
The wording used is not construed as limited to typical definition or dictionary definition, but rather interpreted that with technical concept one of the invention
The meaning and concept of cause.
Embodiment described in this specification and configuration shown in the accompanying drawings are the preferred embodiment of the present invention, and not
Represent whole technical concepts of the invention.Therefore, when submitting the application, it is possible to provide embodiment can be replaced and configured more
Kind is equivalent and modifies.
In the present invention, unit chip can be limited in chip through the dicing lane in transverse direction and longitudinal direction
Divide the aggregate of the semiconductor circuit formed in unit area in a rectangular shape.Chip is included in transverse direction and longitudinal direction side
The unit chip of multiple rows is constituted upwards.
In the present invention, semiconductor devices has multi-chip structure, and passes through dicing lane in a semiconductor substrate
Two unit chips being connected to each other are corresponding with multi-chip.That is, in the present invention, the semiconductor devices of multi-chip structure is included in
The two unit chips connected longitudinally of one another in one semiconductor substrate by dicing lane.
In the present invention, chip expression has formed the unit chip for constituting multiple rows, and semiconductor before sawing
Substrate indicates that chip turns to semiconductor devices by individual by sawing.
Semiconductor module includes semiconductor devices and substrate, and can wherein carry out the soft of the combination of semiconductor devices
Property printed circuit board can be used as substrate use.
When applying the present invention to display device, it will be understood that, one in source electrode driver and sequence controller
As unit chip application, and in the semiconductor device, it may include two source electrode drivers as two unit chips or
It may include a source electrode driver and a sequence controller as two unit chips.It will be described below each according to staying in
Above situation is described in embodiment.In this case, semiconductor module can be bound to display panel by COG scheme
Glass, or flexible printed circuit board can be bound to by COF scheme.
In addition, semiconductor module can be regarded as wherein semiconductor devices and be bound to when the present invention is applied to display device
The COF module of flexible printed circuit board.
Hereinafter, embodiments of the present invention are described in detail with reference to the accompanying drawings.
Fig. 1 is the plan view for showing the preferred embodiment of semiconductor devices of multi-chip structure of the invention.
The semiconductor devices PKG of Fig. 1 is formed in the form of semiconductor packages, wherein the first unit chip CH1 of rectangle,
The second unit chip CH2 of dicing lane SL and rectangle is formed in a semiconductor substrate and is connected to each other in a longitudinal direction.
The semiconductor devices PKG of Fig. 1 is configured to rectangular shape
First unit chip CH1 on bonding position with the first surface of rectangle, and the first input pad IP1 and the
One o pads OP1 is formed on the first surface.
Second unit chip CH2 on bonding position with the second surface of rectangle, and the second input pad IP2 and the
Two o pads OP2 are formed on a second surface.
Dicing lane SL is formed between first unit chip CH1 and second unit chip CH2.
Hereinbefore, bonding position refers to the direction towards flexible printed circuit board.That is, first unit chip CH1
The second surface of first surface and second unit chip CH2 are the surfaces towards flexible printed circuit board.
In addition, first surface can be regarded as whole surface of the first unit chip CH1 on bonding position, which passes through
COG scheme is bound to the bond area of glass or is bound to the bond area of flexible printed circuit board by COF scheme.This
Outside, second surface can be regarded as whole surface of the second unit chip CH2 on bonding position, which passes through COG scheme knot
It is bonded to the bond area of glass or is bound to the bond area of flexible printed circuit board by COF scheme.
In addition, in first unit chip CH1 and second unit chip CH2, the input weldering of the first input pad IP1 and second
Disk IP2 can be configured to go, and the first o pads OP1 and the second o pads OP2 can be configured to multiple rows.First is defeated
Enter the quantity of pad IP1 and the second input pad IP2 and the number of row and the first o pads OP1 and the second o pads OP2
Amount and row can be determined by the quantity of the quantity of input signal and output signal respectively.
The semiconductor devices PKG formed in the form of semiconductor packages can be configured to have and first unit chip CH1, scribing
The identical scale of length summation of road SL and second unit chip CH2.
The the second input pad IP2 and the second o pads OP2 of second unit chip CH2 can have and first unit chip
The identical arragement construction of arragement construction of the first input pad IP1 and the first o pads OP1 of CH1.Such as, it can be seen that
The the first input pad IP1 and the second input pad IP2 of Fig. 1 is by aforementioned arrangement structure with the order of placement of " A, B, C ... "
Be formed as mutually the same.
The chip of Fig. 2 can be used to be manufactured for the semiconductor devices PKG of Fig. 1.
Referring to Fig. 2, chip is divided by the dicing lane SL formed on longitudinal direction and transverse direction, and including arrangement
At the unit chip of columns and rows.
Each of unit chip all has the rectangle shape for being formed with a pair of opposite long side and a pair of opposite short side
Shape.For example, the length of long side may be assumed that be 16,500 μm in each unit chip.
The dicing lane SL of division unit chip refers to the space for sawing retained on chip, and dicing lane SL
It may be assumed that into the width with 80 μm.
In some dicing lane SL, sawing line SA is defined.Sawing line SA be defined as in a longitudinal direction with all scribings
Road SL is corresponding, and every two dicing lane SL limit a sawing line SA in a lateral direction.
The two unit chips surrounded by sawing line SA are the sawing units to form semiconductor devices.More specifically, first
Unit chip CH1, dicing lane SL and second unit chip CH2 are included in the region of each sawing unit.
When executing sawing, removal is formed with the dicing lane SL of the borderline region of different semiconductor devices PKG.That is, half
Conductor device PKG is with including two unit chips (having first unit chip CH1 and second unit chip CH2) and one
The structure of dicing lane SL, and with sawing state combination or with isolated structure.
That is, the length PKG_S of semiconductor devices PKG is the length CH1_S of the long side of first unit chip CH1, the second list
The summation of the width of the length CH2_S and dicing lane SL of the long side of element chip CH2.When the numerical value of application above-illustrated, partly lead
The length of body device PKG is 33,080 μm (=2 × 16,500 μm+80 μm).
The semiconductor devices PKG of Fig. 1 and Fig. 2 can be bound to the bond area of glass by COG scheme, or in combination with extremely
The flexible printed circuit board FL of the semiconductor module of Fig. 3.The combination tool BT of Fig. 4 can be used to be combined for semiconductor devices PKG.
Combination tool BT has two basic change pad PD1 and PD2.The semiconductor devices PKG picked up is illustrated in combination
On the bottom surface of pad PD1 and PD2.
It is and existing when four source electrode drivers are bound to the glass of display panel in rows by COG scheme
Technology is compared, and the effect of embodiments of the present invention can be understood as follows.
It includes that embodiments of the present invention, which need two individual semiconductor devices PKG, each semiconductor devices PKG,
One unit chip CH1 and second unit chip CH2.
Combination tool BT is distributed on bonding pad PD1 and PD2 and is picked up two semiconductor devices PKG, so that two and half
Conductor device PKG and glass are in close contact, and two semiconductor devices PKG are then bound to glass.
According to the present invention, there is 33,080 μm (=2 including the individual semiconductor devices PKG of each of two unit chips
× 16,500 μm+80 μm) length, which is the total of width and the length of the main shaft of two unit chips of a dicing lane
With.
The length of semiconductor devices PKG can meet the combinable chip size of the bonding pad PD1 and PD2 of combination tool BT
Minimum space CS (for example, 5,000 μm) needed between PS1 and PS2 and the chip picked up on bonding pad PD1 and PD2.
Embodiment according to the present invention, required total binding length are 66,180 μ of length of two semiconductor devices PKG
Between m (=2 × 33,080 μm) and bonding pad PD1 and PD2 5,000 μm of minimum separation distances of 71,180 μm of summation (=
66,180μm+5,000μm)。
However, in the prior art, source electrode driver is directed to each unit chip individuation.Therefore, when four source electrodes drive
When dynamic device is bound to the glass of display panel with row, required total binding length is the summation of the length of four source electrode drivers
15,000 μm of summation of the minimum space CS between chip in 66,000 μm (=4 × 16,500 μm) and four combinations pad
81,000 μm of the sum of (=3 × 5,000 μm) (=66,000 μm+15,000 μm).
It is observed that compared with prior art, embodiments of the present invention reduce total binding length.Therefore, according to
Embodiments of the present invention can obtain the effect that the unit chip of such as source electrode driver can be combined with high density.
Embodiment according to the present invention, can by semiconductor devices PKG is applied to the semiconductor module of Fig. 3 come with
High density combining unit chip.
Referring to Fig. 3, in semiconductor module, semiconductor devices PKG is bound to the predetermined combination of flexible printed circuit board FL
Region.The bond area of flexible printed circuit board FL can be regarded as by combining the surface covered by semiconductor devices PKG, and
It usually can be set to the middle section of flexible printed circuit board FL.
Flexible printed circuit board FL is with wherein input terminal IT, input line IL, output terminal OT and output line OL are formed
Structure on a surface, wherein upper input terminal IT is located at first end, and input terminal IT is connected to knot by input line IL
Region is closed, lower output terminal OT is located at the second end opposite with first end, and output terminal OT is connected to combination by output line OL
Region.The quantity of input terminal IT can with the first input pad IP1 of the first unit chip CH1 of semiconductor devices PKG and
The summation of the second input pad IP2 of second unit chip CH2 is corresponding, and the quantity of output terminal OT can be with semiconductor device
The second o pads OP2's of the first o pads OP1 and second unit chip CH2 of the first unit chip CH1 of part PKG is total
And correspondence.Input line IL and output line OL may be formed to have from bond area to the width of input terminal IT or output terminal OT
The pattern to extend on region.
The case where being bound to the flexible printed circuit board FL of Fig. 3 by COF scheme with four source electrode drivers is corresponding, and existing
There is technology to compare, the effect of embodiments of the present invention can be understood as follows.
It in embodiments of the present invention, respectively include the two and half of first unit chip CH1 and second unit chip CH2
Conductor device PKG is bound to a flexible printed circuit board FL.Therefore, in order to combine four source electrode drivers, need two it is soft
Property printed circuit board FL.
However, when source electrode driver is bound to each flexible printed circuit board FL as in the state of the art one by one, knot
It closes four source electrode drivers and needs four flexible printed circuit board FL.I.e., it is possible to find out, existing method need further exist for two it is soft
Length needed for property printed circuit board FL.
Therefore, in embodiments of the present invention, even if can also be obtained in the combination of COF scheme as shown in Figure 3
Obtain the effect that the unit chip of such as source electrode driver can be combined with high density.
In addition, in embodiments of the present invention, due to improving packing density, it is thus possible to ensure semiconductor devices
PKG, semiconductor module and using the semiconductor module device planning and design convenience.
Meanwhile including in a semiconductor devices PKG first unit chip CH1 and second unit chip CH2 can match
It is set to structure and function having the same, or is configured to have the function of different structure and different.
For example, first unit chip CH1 and second unit chip CH2 may be designed as source electrode driver.In addition, first unit
Chip CH1 may be designed as source electrode driver, and second unit chip CH2 may be designed as sequence controller.It can be according in design
Variation be various applications increase component combination density.
In addition, in embodiments of the present invention, including the first unit chip CH1 in a semiconductor devices PKG
The first input pad IP1 and the first o pads OP1 and second unit chip CH2 the second input pad IP2 and second
The arragement construction of o pads OP2 is made it possible to increase the combination density of component and is provided for reducing wiring by various modifications
The multiple choices of density.
As shown in Figure 5, semiconductor devices PKG can be configured to have such arragement construction: wherein second unit chip
The the second input pad IP2 and the second o pads OP2 of CH2 and the first input pad IP1 and first of first unit chip CH1
O pads OP1 is arranged symmetrically relative to dicing lane SL.
For example, it is observed that the first input pad IP1 and the second input pad IP2 of Fig. 5 relative to dicing lane SL with
The order of placement of " A, B, C ... " is mutually symmetrical.
When semiconductor devices PKG is configured according to the embodiment of Fig. 5, the flexible printed circuit board FL of semiconductor module can
To be configured to have by the first input pad IP1 as shown in Figure 6 (closest to dicing lane among the first input pad IP1
The A of SL) and the second input pad IP2 (closest to the first input line that the A of dicing lane SL) is shared among the second input pad IP2
SIL。
The embodiment of Fig. 6 is only the example of a shared input line IL, and design is like that, more as shown in Figure 6
Input line SIL shares the symmetrical input pad of first unit chip CH1 and second unit chip CH2, makes it possible to reduce cloth
Line density.
In fig. 5 and fig., component identical with the component in Fig. 1 and Fig. 3 is indicated by the same numbers, and is omitted
Redundancy description.
In addition, as shown in Figure 7, semiconductor devices PKG may be arranged so that the second input weldering of second unit chip CH2
Disk IP2 and the second o pads OP2 has and the first input when first unit chip CH1 rotates 180 ° relative to its center
The identical arragement construction of arragement construction of pad IP1 and the first o pads OP1.
For example, the first input pad IP1 of first unit chip CH1 is arranged to, and second unit core adjacent with upper long side
The second input pad IP2 of piece CH2 is arranged to adjacent with lower long side.That is, the first input pad IP1 of first unit chip CH1
It is arranged in and wherein first unit chip CH1, dicing lane SL and second with the second input pad IP2 of second unit chip CH2
In the position that the longitudinal direction that unit chip CH2 is connected to each other intersects.
In addition, the first o pads OP1 of first unit chip CH1 is arranged to, and second unit core adjacent with lower long side
The second o pads OP2 of piece CH2 is arranged to adjacent with upper long side.That is, the first o pads OP1 of first unit chip CH1
It is arranged in and wherein first unit chip CH1, dicing lane SL and second with the second o pads OP2 of second unit chip CH2
In the position that the longitudinal direction that unit chip CH2 is connected to each other intersects.
In addition, the semiconductor devices PKG of Fig. 7 also has the first input pad IP1 and first of first unit chip CH1 defeated
The the second input pad IP2 and the second o pads OP2 of pad OP1 and second unit chip CH2 is relative to dicing lane SL out
The structure being mutually symmetrical.
For example, it is observed that the first input pad IP1 and the second input pad IP2 of Fig. 7 relative to dicing lane SL with
The order of placement of " A, B, C ... " is mutually symmetrical.
In the case of fig. 7, the first o pads OP1 of first unit chip CH1 be formed as near output terminal OT1
Long side it is adjacent, and the second o pads OP2 of second unit chip CH2 be formed as and far from output terminal OT2 long side phase
It is adjacent.
Therefore, first unit chip CH1 can form the first output line OL1 with structure as shown in Figure 8, and second is single
Element chip CH2 can form the second output line OL2 with structure as shown in Figure 9.
In order to describe Fig. 8 and Fig. 9, the top of flexible printed circuit board FL is referred to as first layer, and its underpart is referred to as
The second layer.In addition, the output terminal OT corresponding with first unit chip CH1 of first layer is represented by " first lead-out terminal OT1 "
Property indicate, and the output line OL corresponding with first unit chip CH1 of first layer is by " the first output line OL1 " representative earth's surface
Show.In addition, the output terminal OT corresponding with second unit chip CH2 of first layer by " the sub- OT2 of second output terminal " typically
It indicates, and the output line OL corresponding with second unit chip CH2 of the second layer is typically indicated by " the second output line OL2 ".
Referring to Fig. 8, first output line OL1 and first lead-out terminal OT1 corresponding with first unit chip CH1 is formed in soft
Property printed circuit board FL first layer on, and first unit chip CH1 and second unit chip CH2 is combined.
The both ends of first output line OL1 are connected to the of first unit chip CH1 and longitudinally extending in first layer
One o pads OP1 and first lead-out terminal OT1.
It is formed in flexible printed circuit board FL's referring to Fig. 9, second output line OL2 corresponding with second unit chip CH2
On the second layer.
The both ends of second output line OL2 are connected to the of first layer by the through-hole BH1 and BH2 of flexible printed circuit board FL
The second o pads OP2, the second o pads OP2 and second output terminal of two output terminal OT2 and second unit chip CH2
OT2 is bound to first layer.
In Fig. 9, it is second defeated to can be regarded as the second unit chip CH2 for electrical connection by appended drawing reference " IB " and " OB "
The extension of the extension of pad OP2 and the second input pad IP2 out.
As shown in Fig. 7 to Fig. 9, in first unit chip CH1 and second unit chip CH2, even if when the first output
When pad OP1 and the second o pads OP2 are arranged at different location corresponding with output terminal OT, it can be also routed reducing
Output line OL is readily formed while density.
In addition, as shown in Figure 10, semiconductor devices PKG can have such arragement construction: first unit chip CH1's
The output of the second input pad IP2 of first input pad IP1 and the first o pads OP1 and second unit chip CH2 and second
Pad OP2 is intersected with each other in a longitudinal direction.
For example, it is observed that the first input pad IP1 and the second input pad IP2 of Figure 10 pass through aforementioned arrangement knot
Structure is mutually symmetrical with the order of placement of " C, B, A ... ".
In the semiconductor devices PKG of Figure 10, first unit chip CH1 and second unit chip CH2 can be according to output ends
The position of sub- OT is readily formed output line OL while reducing wiring density using structure shown in Fig. 8 and Fig. 9.
Claims (12)
1. the semiconductor devices of multi-chip structure, comprising:
First unit chip forms the first input pad and the first o pads in the first unit chip；
Second unit chip forms the second input pad and the second o pads in the second unit chip；And
Dicing lane, the dicing lane between the first unit chip and the second unit chip,
Wherein, the semiconductor devices is formed in the form of semiconductor packages, in the semiconductor packages, the first unit
Chip, the dicing lane and the second unit chip along the long side of the first unit chip longitudinal direction identical half
It is connected to each other on conductor substrate.
2. the semiconductor devices of multi-chip structure according to claim 1, wherein the semiconductor packages have with it is described
The identical scale of summation of the length of first unit chip, the dicing lane and the second unit chip.
3. the semiconductor devices of multi-chip structure according to claim 1, wherein the second of the second unit chip is defeated
Entering pad and the second o pads has and the first input pad of the first unit chip and the arrangement of the first o pads
The identical arragement construction of structure.
4. the semiconductor devices of multi-chip structure according to claim 1, wherein the second of the second unit chip is defeated
The first input pad and the first o pads for entering pad and the second o pads and the first unit chip are relative to described
Dicing lane is arranged symmetrically.
5. the semiconductor devices of multi-chip structure according to claim 1, wherein the second of the second unit chip is defeated
Entering pad and the second o pads has and the center rotation when the first unit chip relative to the first unit chip
The identical arragement construction of arragement construction of first input pad and first o pads at 180 °.
6. the semiconductor devices of multi-chip structure according to claim 1, wherein the first unit chip and described
Two unit chips have different function and structures.
7. the semiconductor module of the semiconductor devices using multi-chip structure, comprising:
Semiconductor devices, the semiconductor devices have rectangular shape and including first unit chip, dicing lane and second units
Chip, the first unit chip, the dicing lane and the second unit chip are formed in identical along the longitudinal direction of long side
Semiconductor substrate on；And
Flexible printed circuit board, in the flexible printed circuit board, the semiconductor devices is mounted on bond area, and
Input line and output line are formed in the flexible printed circuit board, the input line connects the input terminal at first end is located at
It is connected to the bond area, the output terminal being located at the second end opposite with the first end is connected to institute by the output line
Bond area is stated,
Wherein, it is formed in the first unit chip and the first input pad for being contacted with the bond area and is formed in
The second input pad contacted in the second unit chip and with the bond area is electrically connected to the extension of the input line
The extremely end of the bond area, and
It is formed in the first unit chip and the first o pads for being contacted with the bond area and is formed in described
What the second o pads contacted in second unit chip and with the bond area were electrically connected to the output line extends to institute
State the end of bond area.
8. the semiconductor module of the semiconductor devices according to claim 7 using multi-chip structure, wherein described second
The second input pad and the second o pads of unit chip have and the first input pad of the first unit chip and the
The identical arragement construction of the arragement construction of one o pads.
9. the semiconductor module of the semiconductor devices according to claim 7 using multi-chip structure, wherein described second
The second input pad and the second o pads and the first input pad of the first unit chip and first of unit chip are defeated
Pad is arranged symmetrically relative to the dicing lane out.
10. the semiconductor module of the semiconductor devices according to claim 9 using multi-chip structure, wherein described defeated
Entering line includes the first input line, first input line by among first input pad near the of the dicing lane
The second input pad near the dicing lane among one input pad and second input pad is shared.
11. the semiconductor module of the semiconductor devices according to claim 7 using multi-chip structure, wherein described
The second input pad and the second o pads of two unit chips have and work as the first unit chip relative to described first
The arragement construction of first input pad and first o pads at 180 ° of the center rotation of unit chip is identical
Arragement construction.
12. the semiconductor module of the semiconductor devices according to claim 11 using multi-chip structure, wherein described defeated
The first output line corresponding with the first unit chip among outlet is formed in the first layer of the flexible printed circuit board
On,
The second output line corresponding with the second unit chip among the output line is formed in the flexible print circuit
On the second layer of plate,
The both ends of first output line are connected to the output terminal and the first unit chip of the first layer by extending
The first o pads, and
The both ends of second output line are connected to the output end of the first layer by the through-hole of the flexible printed circuit board
Second o pads of the sub and described second unit chip.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2016-0140380 | 2016-10-26 | ||
| KR20160140380 | 2016-10-26 | ||
| PCT/KR2017/011893 WO2018080185A1 (en) | 2016-10-26 | 2017-10-26 | Semiconductor device having multi-chip structure and semiconductor module using same |
Publications (2)
| Publication Number | Publication Date |
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| CN109906507A true CN109906507A (en) | 2019-06-18 |
| CN109906507B CN109906507B (en) | 2023-09-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201780066704.0A Active CN109906507B (en) | 2016-10-26 | 2017-10-26 | Semiconductor device of multichip structure and semiconductor module using the same |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN109906507B (en) | 2023-09-05 |
| KR20180045849A (en) | 2018-05-04 |
| KR102394796B1 (en) | 2022-05-06 |
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