CN109906507B - Semiconductor device of multichip structure and semiconductor module using the same - Google Patents
Semiconductor device of multichip structure and semiconductor module using the same Download PDFInfo
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- CN109906507B CN109906507B CN201780066704.0A CN201780066704A CN109906507B CN 109906507 B CN109906507 B CN 109906507B CN 201780066704 A CN201780066704 A CN 201780066704A CN 109906507 B CN109906507 B CN 109906507B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/112—Mixed assemblies
Abstract
A semiconductor device of a multi-chip structure and a semiconductor module using the semiconductor device of the multi-chip structure are disclosed. The unit chip such as the source driver is configured as a semiconductor device having a multi-chip structure such that the mounting density of the unit chip is increased, and the input pad and the output pad of the unit chip have the same structure or different structures, thereby increasing the mounting density through various choices.
Description
Technical Field
The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device of a multi-chip structure capable of improving mounting density, and a semiconductor module of the semiconductor device using the multi-chip structure.
Background
The display device includes a display panel in which pixels are implemented by OLEDs, LEDs, or LCDs, a driver for driving the pixels on a screen, a timing controller for controlling the operation of the driver, and the like. In general, the drivers may be divided into source drivers that supply source driving signals corresponding to data to pixels of a display panel and gate drivers that supply gate signals row by row on a screen.
Wherein a plurality of source drivers may be arranged on one side of the display panel while the source drivers are spaced apart from each other according to the size and resolution of the screen.
For example, in the case of a chip on glass (hereinafter referred to as "COG") scheme, the source driver is coupled to glass of the display panel.
In the case of the COG scheme, the source driver is manufactured as a semiconductor chip by sawing a wafer, and bonded to glass as the semiconductor chip itself, without molding for packaging (encapsulation) or encapsulation of epoxy.
In addition, the source driver may be mounted in various manners such as a chip on film (hereinafter referred to as "COF") according to the type of the display panel.
In the display panel, as the screen size decreases and the screen resolution increases, the density of source drivers disposed on one side of the display panel gradually increases.
In the case of the COG scheme, the source driver is bonded to glass by using a bonding tool. The bonding tool includes a plurality of bonding pads arranged in a row. The bonding tool picks up one source driver for each bonding pad, aligns the source driver picked up on the bonding pad to a predetermined position of the glass, brings the source driver into close contact with the glass, and then bonds the source driver to the glass.
In the case of the COG scheme, the separation pitch between the mounted source drivers is determined by the separation pitch between the bonding pads of the bonding tool. Typically, the source driver has a rectangular shape and is constituted by a package individualised according to chip areas divided by dicing streets (dicing lanes) of the wafer. The source drivers are arranged in a row in the main axis direction and then bonded to the glass.
In the case of combining the above-described individual source drivers, the bonding tool requires an exemplary minimum separation pitch of 5,000 μm or more between chips. Therefore, in the case of combining four source drivers (the length of the long side of each source driver is 16,500 μm), the length required for combining four source drivers is the sum (=4×16,500 μm+3×5,000 μm) of the length of the long side of four source drivers and the separation pitch between three bonding pads.
As described above, in the case of combining individual source drivers while satisfying the minimum separation pitch between chips required for the combining tool, there is a limit to improving the mounting density of the source drivers while satisfying the minimum separation pitch between chips.
The source driver is required to have an improved wiring density and an improved mounting density. In addition, the source driver needs to have various choices for mounting.
Disclosure of Invention
Various embodiments relate to a semiconductor device of a multi-chip structure and a semiconductor module using the same to increase the mounting density of unit chips such as source drivers.
Various embodiments relate to a semiconductor device including two unit chips adjacent to each other with respect to a scribe line on one semiconductor substrate to increase a mounting density of the unit chips, and a semiconductor module using the same.
Various embodiments relate to a semiconductor device of a multi-chip structure in which two unit chips identical to or different from each other are manufactured on one semiconductor substrate in a semiconductor process and the two unit chips connected to each other through scribe lanes are sawed at a wafer level to be implemented as a semiconductor package, and a semiconductor module using the semiconductor device of the multi-chip structure.
Various embodiments relate to a semiconductor module in which a wiring is shared by two unit chips formed on one semiconductor substrate and included in one semiconductor device, or a wiring is formed in a multilayer for the two unit chips, so that a wiring density can be improved.
Various embodiments relate to a semiconductor device of a multi-chip structure in which two unit chips formed on one semiconductor substrate have the same structure or different structures so that mounting density can be improved through various choices, and a semiconductor module using the semiconductor device of the multi-chip structure.
In an embodiment, a semiconductor device of a multi-chip structure includes: the semiconductor device includes a first unit chip, a second unit chip, and a scribe lane, wherein a first input pad and a first output pad are formed in the first unit chip, a second input pad and a second output pad are formed in the second unit chip, and the scribe lane is located between the first unit chip and the second unit chip, wherein the semiconductor device is formed in the form of a semiconductor package in which the first unit chip, the scribe lane, and the second unit chip are connected to each other on the same semiconductor substrate along a longitudinal direction of a long side of the first unit chip.
In an embodiment, a semiconductor module using a semiconductor device of a multi-chip structure includes: a semiconductor device and a flexible printed circuit board, wherein the semiconductor device has a rectangular shape and includes a first unit chip, a scribe line, and a second unit chip formed on the same semiconductor substrate in a longitudinal direction of a long side, in the flexible printed circuit board, the semiconductor device is mounted to a bonding region, and an input line connecting an input terminal at a first end to the bonding region and an output line connecting an output terminal at a second end opposite to the first end to the bonding region are formed in the flexible printed circuit board, wherein a first input pad formed in the first unit chip and in contact with the bonding region and a second input pad formed in the second unit chip and in contact with the bonding region are electrically connected to an end portion of the input line extending to the bonding region, and a first output pad formed in the first unit chip and in contact with the bonding region and a second output pad formed in the second unit chip and in contact with the bonding region are electrically connected to an end portion of the output line extending to the bonding region.
According to the present application, the semiconductor device is formed in a multi-chip structure in which two unit chips such as a source driver are formed on one semiconductor substrate, so that the mounting density of the unit chips can be improved.
Further, according to the present application, two unit chips identical to or different from each other are manufactured on one semiconductor substrate in a semiconductor process, and two unit chips connected to each other through scribe lanes are implemented as a semiconductor package, so that the mounting density of the unit chips can be improved.
Further, according to the present application, the wiring is shared by two unit chips formed on one semiconductor substrate, or the wiring is formed in a multilayer for the two unit chips, so that the wiring density of the semiconductor module can be improved.
Further, according to the present application, two unit chips formed on one semiconductor substrate have the same structure or different structures, so that the mounting density of the unit chips can be improved by various choices.
Further, according to the present application, the mounting density of the semiconductor device and the semiconductor module is improved, so that the advantage of the device design including the semiconductor device and the semiconductor module can be provided.
Drawings
Fig. 1 is a plan view showing a preferred embodiment of a semiconductor device of a multi-chip structure of the present application.
Fig. 2 is a plan view of a semiconductor substrate for explaining a manufacturing method of the semiconductor device of fig. 1.
Fig. 3 is a plan view showing a preferred embodiment of a semiconductor module using the semiconductor device of fig. 1.
Fig. 4 is a view for explaining a method of bonding semiconductor devices by using a bonding tool.
Fig. 5 is a plan view showing another embodiment of the semiconductor device of the multi-chip structure of the present application.
Fig. 6 is a plan view showing a preferred embodiment of a semiconductor module using the semiconductor device of fig. 5.
Fig. 7 is a plan view showing still another embodiment of the semiconductor device of the multi-chip structure of the present application.
Fig. 8 is a cross-sectional view showing an output line connection state of the second unit chip CH2 of fig. 7.
Fig. 9 is a cross-sectional view showing an output line connection state of the first unit chip CH1 of fig. 7.
Fig. 10 is a plan view showing still another embodiment of the semiconductor device of the multi-chip structure of the present application.
Detailed Description
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings. The words used in the present specification and claims are not to be construed as limited to typical definitions or dictionary definitions, but to be construed as meaning and concepts consistent with the technical concept of the present application.
The embodiments described in the present specification and the configurations shown in the drawings are preferred embodiments of the present application and do not represent the entire technical concept of the present application. Thus, upon submission of the present application, various equivalents and modifications capable of replacing the embodiments and configurations may be provided.
In the present application, a unit chip may be defined as an aggregate of semiconductor circuits formed in unit regions of a wafer divided into rectangular shapes by dicing streets in the lateral and longitudinal directions. The wafer includes unit chips constituting a plurality of rows in the lateral direction and the longitudinal direction.
In the present application, the semiconductor device has a multi-chip structure, and two unit chips connected to each other through scribe lanes on one semiconductor substrate correspond to the multi-chip. That is, in the present application, a semiconductor device of a multi-chip structure includes two unit chips connected to each other longitudinally by scribe lanes on one semiconductor substrate.
In the present application, the wafer means that unit chips constituting a plurality of rows have been formed before sawing, and the semiconductor substrate means that the wafer is singulated into semiconductor devices by sawing.
The semiconductor module includes a semiconductor device and a substrate, and a flexible printed circuit board in which bonding of the semiconductor device can be performed can be used as the substrate.
When the present application is applied to a display device, it is understood that one of the source driver and the timing controller is applied as a unit chip, and in the semiconductor device, two source drivers may be included as two unit chips or one source driver and one timing controller may be included as two unit chips. The above case will be described according to each embodiment to be described below. In this case, the semiconductor module may be bonded to glass of the display panel by a COG scheme, or may be bonded to a flexible printed circuit board by a COF scheme.
Further, when the present application is applied to a display device, a semiconductor module may be understood as a COF module in which a semiconductor device is bonded to a flexible printed circuit board.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Fig. 1 is a plan view showing a preferred embodiment of a semiconductor device of a multi-chip structure of the present application.
The semiconductor device PKG of fig. 1 is formed in the form of a semiconductor package in which a rectangular first unit chip CH1, scribe lanes SL, and a rectangular second unit chip CH2 are formed on one semiconductor substrate and connected to each other in the longitudinal direction. The semiconductor device PKG of fig. 1 is configured to have a rectangular shape
The first unit chip CH1 has a rectangular first surface in the bonding direction, and the first input pad IP1 and the first output pad OP1 are formed on the first surface.
The second unit chip CH2 has a rectangular second surface in the bonding direction, and the second input pad IP2 and the second output pad OP2 are formed on the second surface.
The scribe line SL is formed between the first unit chip CH1 and the second unit chip CH2.
In the above, the bonding direction refers to a direction facing the flexible printed circuit board. That is, the first surface of the first unit chip CH1 and the second surface of the second unit chip CH2 are surfaces facing the flexible printed circuit board.
Further, the first surface may be understood as the entire surface of the first unit chip CH1 in the bonding direction, which is bonded to the bonding region of the glass by the COG scheme or to the bonding region of the flexible printed circuit board by the COF scheme. Further, the second surface may be understood as the entire surface of the second unit chip CH2 in the bonding direction, which is bonded to the bonding region of the glass by the COG scheme or to the bonding region of the flexible printed circuit board by the COF scheme.
Further, in the first and second unit chips CH1 and CH2, the first and second input pads IP1 and IP2 may be configured in rows, and the first and second output pads OP1 and OP2 may be configured in a plurality of rows. The number and rows of the first and second input pads IP1 and IP2 and the number and rows of the first and second output pads OP1 and OP2 may be determined by the number of input signals and the number of output signals, respectively.
The semiconductor device PKG formed in the form of a semiconductor package may be configured to have the same scale as the sum of the lengths of the first unit chip CH1, the scribe lane SL, and the second unit chip CH2.
The second input pad IP2 and the second output pad OP2 of the second unit chip CH2 may have the same arrangement structure as the arrangement structure of the first input pad IP1 and the first output pad OP1 of the first unit chip CH 1. For example, it can be seen that the first and second input pads IP1 and IP2 of fig. 1 are formed to be identical to each other in the arrangement order of "a, B, C … …" by the foregoing arrangement structure.
The semiconductor device PKG of fig. 1 may be manufactured using the wafer of fig. 2.
Referring to fig. 2, the wafer is divided by scribe lanes SL formed in the longitudinal direction and the lateral direction, and includes unit chips arranged in columns and rows.
Each of the unit chips has a rectangular shape formed with a pair of opposite long sides and a pair of opposite short sides. For example, in each unit chip, the length of the long side may be assumed to be 16,500 μm.
The scribe lane SL dividing the unit chips refers to a space reserved on the wafer for sawing, and the scribe lane SL can be assumed to have a width of 80 μm.
In some scribe lanes SL, sawing lines SA are defined. The saw cut line SA is defined to correspond to all the dicing streets SL in the longitudinal direction, and one saw cut line SA is defined for every two dicing streets SL in the lateral direction.
The two unit chips surrounded by the sawing wire SA are sawing units forming the semiconductor device. More specifically, the first unit chip CH1, the scribe lane SL, and the second unit chip CH2 are included in the region of each sawing unit.
When sawing is performed, the scribe lanes SL formed with the boundary regions of the different semiconductor devices PKG are removed. That is, the semiconductor device PKG has a structure including two unit chips (having the first unit chip CH1 and the second unit chip CH 2) and one scribe line SL, and is bonded in a sawing state or has a separate structure.
That is, the length pkg_s of the semiconductor device PKG is the sum of the length ch1_s of the long side of the first unit chip CH1, the length ch2_s of the long side of the second unit chip CH2, and the width of the scribe lane SL. When the above-exemplified values are applied, the length of the semiconductor device PKG is 33,080 μm (=2×16,500 μm+80 μm).
The semiconductor device PKG of fig. 1 and 2 may be bonded to a bonding region of glass by a COG scheme, or may be bonded to the flexible printed circuit board FL of the semiconductor module of fig. 3. The semiconductor device PKG can be bonded using the bonding tool BT of fig. 4.
The bonding tool BT has two bonding pads PD1 and PD2. The picked-up semiconductor device PKG is shown on the bottom surfaces of the bonding pads PD1 and PD2.
When four source drivers are coupled to the glass of the display panel in a row form by the COG scheme, the effect of the embodiment of the present application can be understood as follows, compared to the related art.
Embodiments of the present application require two separate semiconductor devices PKG, each including a first unit chip CH1 and a second unit chip CH2.
The bonding tool BT distributes and picks up the two semiconductor devices PKG on the bonding pads PD1 and PD2 to bring the two semiconductor devices PKG into close contact with the glass, and then bonds the two semiconductor devices PKG to the glass.
According to the present application, each individual semiconductor device PKG including two unit chips has a length of 33,080 μm (=2×16,500 μm+80 μm), which is the sum of the width of one scribe lane and the length of the principal axes of the two unit chips.
The length of the semiconductor device PKG can satisfy the bondable chip sizes PS1 and PS2 of the bonding pads PD1 and PD2 of the bonding tool BT and the minimum space CS (e.g., 5,000 μm) required between the chips picked up on the bonding pads PD1 and PD2.
According to the embodiment of the present application, the total required bonding length is the sum 71,180 μm (= 66,180 μm+5,000 μm) of the lengths 66,180 μm (=2× 33,080 μm) of the two semiconductor devices PKG and the minimum spacing distance between the bonding pads PD1 and PD2 of 5,000 μm.
However, in the related art, the source driver is individualized for each unit chip. Therefore, when four source drivers are bonded to the glass of the display panel in a row, the total required length is the sum of 66,000 μm (=4×16,500 μm) of the lengths of the four source drivers and the sum of 15,000 μm (=3×5,000 μm) of the minimum spaces CS between the chips in the four bonding pads, 81,000 μm (=66,000 μm+15,000 μm).
It can be observed that embodiments of the present application reduce the overall joint length compared to the prior art. Therefore, according to the embodiment of the present application, an effect that a unit chip such as a source driver can be combined at high density can be obtained.
According to an embodiment of the present application, it is possible to bond unit chips at high density by applying the semiconductor device PKG to the semiconductor module of fig. 3.
Referring to fig. 3, in the semiconductor module, a semiconductor device PKG is bonded to a predetermined bonding area of a flexible printed circuit board FL. The bonding area of the flexible printed circuit board FL can be understood as a surface covered by the semiconductor device PKG by bonding, and may be generally provided as a central area of the flexible printed circuit board FL.
The flexible printed circuit board FL has a structure in which an input terminal IT, an input line IL, an output terminal OT and an output line OL are formed on one surface, wherein the upper input terminal IT is located at a first end, the input line IL connects the input terminal IT to a bonding region, the lower output terminal OT is located at a second end opposite to the first end, and the output line OL connects the output terminal OT to the bonding region. The number of input terminals IT may correspond to the sum of the first input pad IP1 of the first unit chip CH1 and the second input pad IP2 of the second unit chip CH2 of the semiconductor device PKG, and the number of output terminals OT may correspond to the sum of the first output pad OP1 of the first unit chip CH1 and the second output pad OP2 of the second unit chip CH2 of the semiconductor device PKG. The input line IL and the output line OL may be formed to have a pattern extending over a wide area from the bonding area to the input terminal IT or the output terminal OT.
The effects of the embodiments of the present application can be understood as follows, compared to the related art, corresponding to the case where four source drivers are coupled to the flexible printed circuit board FL of fig. 3 through the COF scheme.
In the embodiment of the present application, two semiconductor devices PKG each including the first unit chip CH1 and the second unit chip CH2 are bonded to one flexible printed circuit board FL. Therefore, in order to combine four source drivers, two flexible printed circuit boards FL are required.
However, when the source drivers are coupled to each of the flexible printed circuit boards FL one by one as in the related art, four flexible printed circuit boards FL are required for coupling four source drivers. That is, it can be seen that the existing method further requires the length required for the two flexible printed circuit boards FL.
Therefore, in the embodiment of the present application, even in the combination of the COF scheme as shown in fig. 3, an effect that the unit chips such as the source driver can be combined at high density can be obtained.
Further, in the embodiment of the present application, since the mounting density is improved, convenience in planning and design of the semiconductor device PKG, the semiconductor module, and the apparatus using the semiconductor module can be ensured.
Meanwhile, the first unit chip CH1 and the second unit chip CH2 included in one semiconductor device PKG may be configured to have the same structure and function, or configured to have different structures and different functions.
For example, the first and second unit chips CH1 and CH2 may be designed as source drivers. In addition, the first unit chip CH1 may be designed as a source driver, and the second unit chip CH2 may be designed as a timing controller. The bond density of the components may be increased for various applications according to design variations.
Further, in the embodiment of the present application, the arrangement structure of the first input pad IP1 and the first output pad OP1 of the first unit chip CH1 and the second input pad IP2 and the second output pad OP2 of the second unit chip CH2 included in one semiconductor device PKG is variously modified, so that it is possible to increase the bonding density of components and provide various options for reducing the wiring density.
As shown in fig. 5, the semiconductor device PKG may be configured to have an arrangement structure of: wherein the second input pad IP2 and the second output pad OP2 of the second unit chip CH2 are symmetrically arranged with the first input pad IP1 and the first output pad OP1 of the first unit chip CH1 with respect to the scribe lane SL.
For example, it can be observed that the first input pad IP1 and the second input pad IP2 of fig. 5 are symmetrical to each other in the arrangement order of "a, B, C … …" with respect to the scribe lane SL.
When the semiconductor device PKG is configured according to the embodiment of fig. 5, the flexible printed circuit board FL of the semiconductor module may be configured as shown in fig. 6 to have the first input line SIL shared by the first input pads IP1 (a closest to the scribe lane SL among the first input pads IP 1) and the second input pads IP2 (a closest to the scribe lane SL among the second input pads IP 2).
The embodiment of fig. 6 is only an example of sharing one input line IL, and as the concept shown in fig. 6, a plurality of input lines SIL share symmetrical input pads of the first and second unit chips CH1 and CH2, so that the wiring density can be reduced.
In fig. 5 and 6, the same components as those in fig. 1 and 3 are denoted by the same reference numerals, and redundant description is omitted.
Further, as shown in fig. 7, the semiconductor device PKG may be configured such that the second input pad IP2 and the second output pad OP2 of the second unit chip CH2 have the same arrangement as the arrangement of the first input pad IP1 and the first output pad OP1 when the first unit chip CH1 is rotated 180 ° with respect to its center.
For example, the first input pad IP1 of the first unit chip CH1 is disposed adjacent to the upper long side, and the second input pad IP2 of the second unit chip CH2 is disposed adjacent to the lower long side. That is, the first input pad IP1 of the first unit chip CH1 and the second input pad IP2 of the second unit chip CH2 are arranged in a position crossing the longitudinal direction in which the first unit chip CH1, the scribe lane SL, and the second unit chip CH2 are connected to each other.
Further, the first output pad OP1 of the first unit chip CH1 is disposed adjacent to the lower long side, and the second output pad OP2 of the second unit chip CH2 is disposed adjacent to the upper long side. That is, the first output pad OP1 of the first unit chip CH1 and the second output pad OP2 of the second unit chip CH2 are arranged in a position crossing the longitudinal direction in which the first unit chip CH1, the scribe lane SL, and the second unit chip CH2 are connected to each other.
Further, the semiconductor device PKG of fig. 7 also has a structure in which the first input pad IP1 and the first output pad OP1 of the first unit chip CH1 and the second input pad IP2 and the second output pad OP2 of the second unit chip CH2 are symmetrical to each other with respect to the scribe lane SL.
For example, it can be observed that the first input pad IP1 and the second input pad IP2 of fig. 7 are symmetrical to each other in the arrangement order of "a, B, C … …" with respect to the scribe lane SL.
In the case of fig. 7, the first output pad OP1 of the first unit chip CH1 is formed adjacent to the long side near the output terminal OT1, and the second output pad OP2 of the second unit chip CH2 is formed adjacent to the long side distant from the output terminal OT 2.
Accordingly, the first unit chip CH1 may form the first output line OL1 having the structure as shown in fig. 8, and the second unit chip CH2 may form the second output line OL2 having the structure as shown in fig. 9.
For describing fig. 8 and 9, an upper portion of the flexible printed circuit board FL is referred to as a first layer, and a lower portion thereof is referred to as a second layer. Further, the output terminal OT of the first layer corresponding to the first unit chip CH1 is representatively represented by "first output terminal OT1", and the output line OL of the first layer corresponding to the first unit chip CH1 is representatively represented by "first output line OL 1". Further, the output terminal OT of the first layer corresponding to the second unit chip CH2 is representatively represented by "second output terminal OT2", and the output line OL of the second layer corresponding to the second unit chip CH2 is representatively represented by "second output line OL 2".
Referring to fig. 8, the first output line OL1 and the first output terminal OT1 corresponding to the first unit chip CH1 are formed on the first layer of the flexible printed circuit board FL, and the first unit chip CH1 and the second unit chip CH2 are combined.
Both ends of the first output line OL1 are connected to the first output pad OP1 and the first output terminal OT1 of the first unit chip CH1 by extending longitudinally in the first layer.
Referring to fig. 9, the second output line OL2 corresponding to the second unit chip CH2 is formed on the second layer of the flexible printed circuit board FL.
Both ends of the second output line OL2 are connected to the second output terminal OT2 of the first layer and the second output pad OP2 of the second unit chip CH2 through the through holes BH1 and BH2 of the flexible printed circuit board FL, and the second output pad OP2 and the second output terminal OT2 are bonded to the first layer.
In fig. 9, reference numerals "IB" and "OB" may be understood as an extension portion of the second output pad OP2 and an extension portion of the second input pad IP2 of the second unit chip CH2 for electrical connection.
As shown in fig. 7 to 9, in the first and second unit chips CH1 and CH2, even when the first and second output pads OP1 and OP2 are arranged at different positions corresponding to the output terminals OT, the output lines OL can be easily formed while reducing the wiring density.
Further, as shown in fig. 10, the semiconductor device PKG may have an arrangement structure such that: the first input pad IP1 and the first output pad OP1 of the first unit chip CH1 and the second input pad IP2 and the second output pad OP2 of the second unit chip CH2 cross each other in the longitudinal direction.
For example, it can be observed that the first input pad IP1 and the second input pad IP2 of fig. 10 are symmetrical to each other in the arrangement order of "C, B, a … …" by the foregoing arrangement structure.
In the semiconductor device PKG of fig. 10, the first unit chip CH1 and the second unit chip CH2 can easily form the output line OL while reducing the wiring density with the structure shown in fig. 8 and 9 according to the position of the output terminal OT.
Claims (5)
1. A semiconductor module using a semiconductor device of a multi-chip structure, comprising:
a semiconductor device having a rectangular shape and including a first unit chip, a scribe line, and a second unit chip, the first unit chip, the scribe line, and the second unit chip being formed on the same semiconductor substrate along a longitudinal direction of a long side; and
a flexible printed circuit board in which the semiconductor device is mounted on a bonding region, and in which an input line connecting an input terminal at a first end to the bonding region and an output line connecting an output terminal at a second end opposite to the first end to the bonding region are formed,
wherein a first input pad formed in the first unit chip and contacting the bonding region and a second input pad formed in the second unit chip and contacting the bonding region are electrically connected to an end portion of the input line extending to the bonding region, and
a first output pad formed in the first unit chip and contacting the bonding region, and a second output pad formed in the second unit chip and contacting the bonding region, electrically connected to an end portion of the output line extending to the bonding region, and
wherein a first output line corresponding to the first unit chip among the output lines is formed on a first layer located at an upper portion of the flexible printed circuit board,
a second output line corresponding to the second unit chip among the output lines is formed on a second layer located at a lower portion of the flexible printed circuit board,
the two ends of the first output line are connected to the output terminal of the first layer and the first output pad of the first unit chip by extending in the first layer, and
two ends of the second output line are connected to the output terminal of the first layer and the second output pad of the second unit chip through the through hole of the flexible printed circuit board.
2. The semiconductor module using the semiconductor device of the multi-chip structure according to claim 1, wherein the second input pad and the second output pad of the second unit chip have the same arrangement as the first input pad and the first output pad of the first unit chip.
3. The semiconductor module using the semiconductor device of the multi-chip structure according to claim 1, wherein the second input pad and the second output pad of the second unit chip are symmetrically arranged with respect to the scribe lane with the first input pad and the first output pad of the first unit chip.
4. A semiconductor module using a semiconductor device of a multi-chip structure according to claim 3, wherein the input line includes a first input line shared by a first input pad closest to the scribe lane among the first input pads and a second input pad closest to the scribe lane among the second input pads.
5. The semiconductor module using the semiconductor device of the multi-chip structure according to claim 1, wherein the second input pad and the second output pad of the second unit chip have the same arrangement as the first input pad and the first output pad when the first unit chip is rotated 180 ° with respect to the center of the first unit chip.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2016-0140380 | 2016-10-26 | ||
| KR20160140380 | 2016-10-26 | ||
| PCT/KR2017/011893 WO2018080185A1 (en) | 2016-10-26 | 2017-10-26 | Semiconductor device having multi-chip structure and semiconductor module using same |
Publications (2)
| Publication Number | Publication Date |
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| CN109906507A CN109906507A (en) | 2019-06-18 |
| CN109906507B true CN109906507B (en) | 2023-09-05 |
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| CN201780066704.0A Active CN109906507B (en) | 2016-10-26 | 2017-10-26 | Semiconductor device of multichip structure and semiconductor module using the same |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN109906507A (en) | 2019-06-18 |
| KR102394796B1 (en) | 2022-05-06 |
| KR20180045849A (en) | 2018-05-04 |
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