CN109904272A - A kind of pixel detector of high-conversion-gain and low crosstalk - Google Patents
A kind of pixel detector of high-conversion-gain and low crosstalk Download PDFInfo
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Abstract
The invention discloses the pixel detectors of a kind of high-conversion-gain and low crosstalk, comprising: low-resistance silicon layer (circuit layer), High Resistivity n-Type substrate, back electrode, n+ detection trap, n+ detection trap read-out electrode, buries p trap extraction electrode, buries p trap, the buried p trap in back at buried oxide layer；The present invention can effectively inhibit the crosstalk between back-gate effect and sensor and circuit；Reduce total depletion voltage；The sensitive nodes capacitor at charge-trapping end is effectively reduced, improves conversion gain.
Description
Technical field
The present invention relates to CMOS active pixel sensor field, mainly a kind of silicon-on-insulator (SOI) pixel detector structure.
Background technique
Silicon pixel detector is divided into mixed type (Hybrid) and single-chip integration formula (Monolithic) two major classes.With radiation
The single-chip integration formula detector of sensing layer and circuit layer integration is become high-performance radiation image detector by the development of detector
A kind of demand, and the improvement to hybrid detector: reducing cost and reduces amount of substance.And SOI technology gets a good chance of completely
Sufficient above-mentioned requirements.
The sensing layer (High resistivity substrate) and circuit layer (Si layers of low-resistance) of SOI pixel detector are directly integrated in one single chip
On, integrated level is very high, eliminates the latch-up of Bulk CMOS, does not need bonding (BumpBonding) packaging technology, technique
Difficulty and cost are improved.But there is the problems such as crosstalk such as back-gate effect, between circuit and sensor in SOI pixel detector.
Article " F.F.Khalid, G.W.Deptuch, A.Shenai, et al.Monolithic Active Pixel
Matrix with Binary Counters(MAMBO)ASIC.Nuclear Science Symposium Conference
Record NSS/MIC), 2010IEEE.2010,1544-1550. " are middle to propose nested well structure (Nested well
Structure), which can isolate the crosstalk between circuit and sensor, inhibit back-gate effect, but p-well structure completely includes
Circuit part, sensitive nodes capacitor are larger.Article " H.Kamehama, et al., Fully depleted SOI pixel
photo detectors with backgate surface potential pinning,International Image
Sensor Workshop (IISW), 2015. " propose a kind of backgate clamping structure, but not identical as structure of the invention,
And performance of the invention is more excellent.
Summary of the invention
In view of the deficiencies of the prior art, the present invention proposes the pixel detector of a kind of high-conversion-gain and low crosstalk, packets
Include: low-resistance silicon layer (circuit layer), High Resistivity n-Type substrate, back electrode, n+ detection trap, n+ detection trap read-out electrode, buries p at buried oxide layer
Trap extraction electrode buries p trap, the buried p trap in back；
The back electrode is arranged below the buried p trap in back；The High Resistivity n-Type substrate is arranged in the buried p in back
Above trap, n+ detection trap is arranged above High Resistivity n-Type substrate with p trap is buried, and the low-resistance silicon layer and High Resistivity n-Type substrate are by burying oxygen
Layer separates；The n+ detects trap and buries p trap and separated by buried oxide layer；Buried oxide layer setting is in n+ detection trap and buries above p trap；Bury p
Trap extraction electrode is connect with p trap is buried, and n+ detects trap read-out electrode and connect with n+ detection trap.
The back electrode is arranged below High Resistivity n-Type substrate area, and the buried p trap in the back is that back is adulterated deeply
It is formed.
The entire High Resistivity n-Type substrate exhausts to form charge-sensitive area.N+ detects trap as detecting area, with read-out electrode
It is connected.
It is described bury p trap extraction electrode and connect a voltage appropriate can shield influence of the underlayer voltage to circuit layer；
The p trap that buries is located at below buried oxide layer；It is formed by adulterating twice: primary shallow doping, primary deep doping；Described
It buries p well depth to adulterate, 6-10 μm of junction depth, dopant dose 1-3E10cm-2。
The buried p trap in the back, 6-10 μm of junction depth, dopant dose 1-3E10cm-2。
The High Resistivity n-Type resistance substrate is 700 Ω cm, can also be other specifications 1K Ω cm -7K Ω cm.
The utility model has the advantages that of the invention provides the pixel detector structure of a kind of high-conversion-gain and low crosstalk.The structure
Back-gate effect can effectively be inhibited, further decrease the crosstalk between circuit and sensor, reduce total depletion voltage；It is effectively reduced
The sensitive nodes capacitor at charge-trapping end improves conversion gain.
Detailed description of the invention
Fig. 1 be have proposed bury p trap (BPW) SOI dot structure；
Fig. 2 is SOI dot structure proposed by the present invention；
Fig. 3 is that the total depletion voltage of the present invention and BPW structure compare；
Fig. 4 is the present invention and BPW structure charge collecting terminal trap size comparison；
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, the present invention is carried out below in conjunction with attached drawing specific
It illustrates.
As shown in Figure 1, burying p trap SOI dot structure for what is had proposed, comprising: low-resistance silicon layer (circuit layer) 101, buried oxide layer
102, High Resistivity n-Type substrate 103, back electrode 104, bury p detection trap 105, p+ detection trap read-out electrode；
For Fig. 1 SOI dot structure, a kind of reduction charge-trapping end sensitive nodes capacitor is proposed, improve conversion gain, into
One step improves the SOI dot structure of the shielding between panel detector structure Sensor section and circuit layer.
In SOI dot structure, influence of the underlayer voltage to circuit layer can be shielded by burying p trap one voltage appropriate of connection,
Inhibit the crosstalk between back-gate effect and sensor and circuit；Lesser n+ detection trap is as detecting area, with read-out electrode phase
Even.
As shown in figure 3, the pixel detector structure of a kind of high-conversion-gain and low crosstalk, including low-resistance silicon layer 201, bury oxygen
Layer 202, back electrode 204, n+ detection trap 205, n+ detection trap read-out electrode 206, buries p trap extraction electricity at High Resistivity n-Type substrate 203
P trap 208, the buried p trap 209 in back are buried in pole 207；
The back electrode 204 is arranged below the buried p trap 209 in back；The setting of High Resistivity n-Type substrate 203 exists
Buried 209 top of p trap in back, n+ detection trap 205 are arranged above High Resistivity n-Type substrate 203 with p trap 208 is buried, the low-resistance silicon
Layer 201 is separated with High Resistivity n-Type substrate 203 by buried oxide layer 202；The described n+ detection trap 205 and bury p trap 208 by buried oxide layer 202 every
It opens；The setting of buried oxide layer 202 is in n+ detection trap 205 and buries above p trap 208；It buries p trap extraction electrode 207 to connect with p trap 208 is buried, n+
Detection trap read-out electrode 206 is connect with n+ detection trap 205；
The entire High Resistivity n-Type substrate 203 exhausts to form charge-sensitive area.N+ detects trap 205 and is used as detecting area, with reading
Electrode is connected out.
It is described bury 208 extraction electrode of p trap and connect a voltage appropriate can shield underlayer voltage to the shadow of circuit layer
It rings；
The p trap 208 that buries is located at 202 lower section of buried oxide layer；It is formed by adulterating twice: primary shallow doping, primary deep doping；
The p well depth that buries adulterates, and 6-10 μm of junction depth, dopant dose 1-3E10cm-2。
The back electrode 204 is arranged below 203 region of High Resistivity n-Type substrate, and the buried p trap 209 in the back is
Back doping deeply is formed, and 6-10 μm of junction depth, dopant dose 1-3E10cm-2。
203 resistance of High Resistivity n-Type substrate is 700 Ω cm, can also be other specifications 1K Ω cm -7K Ω cm.
Fig. 3 is that the total depletion voltage of the present invention and BPW structure compare.Total depletion voltage of the present invention is about 33V, and BPW is complete
Exhausting voltage is about 44V.
Fig. 4 is the present invention and BPW structure charge collecting terminal trap size comparison.The size and conversion gain of charge-trapping trap at
Inverse ratio, size is smaller, and conversion gain is bigger.Charge-trapping trap size of the present invention only has the 1/6 of BPW structure, and high-conversion-gain obtains
To improve.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention.Reality of the invention is not being departed from
In matter and range, a little adjustment and optimization can be done, protection scope of the present invention is subject to claim.
Claims (3)
1. the pixel detector of a kind of high-conversion-gain and low crosstalk, it is characterised in that: low-resistance silicon layer, buried oxide layer, High Resistivity n-Type lining
Bottom, n+ detection trap, n+ detection trap read-out electrode, buries p trap extraction electrode, buries p trap, the buried p trap in back at back electrode；
The back electrode is arranged below the buried p trap in back；The High Resistivity n-Type substrate is arranged on the buried p trap in back
Side, n+ detection trap and buries p trap and is arranged above High Resistivity n-Type substrate, the low-resistance silicon layer and High Resistivity n-Type substrate by buried oxide layer every
It opens；The n+ detects trap and buries p trap and separated by buried oxide layer；Buried oxide layer setting is in n+ detection trap and buries above p trap；P trap is buried to draw
Electrode is connect with p trap is buried out, and n+ detects trap read-out electrode and connect with n+ detection trap.
2. the pixel detector of a kind of high-conversion-gain and low crosstalk according to claim 1, it is characterised in that: it is described
Entire High Resistivity n-Type substrate exhausts to form charge-sensitive area；N+ detects trap as detecting area, is connected with read-out electrode.
3. the pixel detector of a kind of high-conversion-gain and low crosstalk according to claim 1, it is characterised in that: it is described
It buries p trap and connects influence of the voltage shield underlayer voltage to circuit layer.
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| CN109904272B CN109904272B (en) | 2021-02-09 |
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| US20120273653A1 (en) * | 2011-04-27 | 2012-11-01 | Aptina Imaging Corporation | Image sensor array for the back side illumination with junction gate photodiode pixels |
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| CN103928560A (en) * | 2014-04-29 | 2014-07-16 | 哈尔滨工程大学 | Pixel structure of radiation detector |
| CN105185796A (en) * | 2015-09-30 | 2015-12-23 | 南京邮电大学 | High-detective-efficiency single photon avalanche diode detector array unit |
| CN107154413A (en) * | 2016-03-03 | 2017-09-12 | 精工半导体有限公司 | Semiconductor device with photo detector |
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| CN102142447A (en) * | 2009-12-04 | 2011-08-03 | 卡尔斯特里姆保健公司 | Coplanar high fill factor pixel architecture |
| US20120273653A1 (en) * | 2011-04-27 | 2012-11-01 | Aptina Imaging Corporation | Image sensor array for the back side illumination with junction gate photodiode pixels |
| CN103165631A (en) * | 2011-12-12 | 2013-06-19 | 普廷数码影像控股公司 | Image sensors with vertical junction gate source follower pixels |
| CN103515465A (en) * | 2012-06-29 | 2014-01-15 | 英飞凌科技股份有限公司 | Photoelectric detector and manufacturing method thereof |
| CN203377243U (en) * | 2013-06-26 | 2014-01-01 | 林大伟 | Photoelectric diode |
| CN103928560A (en) * | 2014-04-29 | 2014-07-16 | 哈尔滨工程大学 | Pixel structure of radiation detector |
| CN105185796A (en) * | 2015-09-30 | 2015-12-23 | 南京邮电大学 | High-detective-efficiency single photon avalanche diode detector array unit |
| CN107154413A (en) * | 2016-03-03 | 2017-09-12 | 精工半导体有限公司 | Semiconductor device with photo detector |
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| Title |
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