CN106783900B - SOI pixel detector structure - Google Patents
SOI pixel detector structure Download PDFInfo
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- CN106783900B CN106783900B CN201611094845.7A CN201611094845A CN106783900B CN 106783900 B CN106783900 B CN 106783900B CN 201611094845 A CN201611094845 A CN 201611094845A CN 106783900 B CN106783900 B CN 106783900B
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- 238000001514 detection method Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 230000005540 biological transmission Effects 0.000 claims abstract description 11
- 238000003860 storage Methods 0.000 claims abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 3
- 239000001301 oxygen Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 8
- 238000000605 extraction Methods 0.000 claims description 7
- 230000002265 prevention Effects 0.000 claims description 2
- -1 boron ions Chemical class 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14607—Geometry of the photosensitive area
Abstract
The invention discloses an SOI pixel detector structure, which comprises a low-resistance silicon layer, an oxygen burying layer, a gate oxide layer, a high-resistance n-type substrate, a buried p-well, a buried n-well, a p-type detection well, a buried n-well leading-out electrode, a transmission gate electrode, a p-type detection well reading electrode and a back electrode, wherein the low-resistance silicon layer is arranged on the low-resistance silicon layer; wherein the low-resistance silicon layer (circuit layer) and the high-resistance n-type substrate are separated by a buried oxide layer; the buried n-well is surrounded by a deeper buried p-well, and the entire high-resistance n-type substrate is depleted to form a charge sensitive region. The buried n-well of the structure is connected with a proper voltage so as to shield the influence of the substrate voltage on the circuit layer; the larger buried p-well forms a large charge collection and storage region, while the smaller p-type sensing well serves as a sensing region and is connected to the readout electrode, thereby reducing the capacitance of the sensitive node of the SOI pixel sensor.
Description
Technical Field
The invention relates to the field of active pixel sensors, in particular to a silicon-on-insulator (SOI) pixel detector structure.
Background
Silicon pixel detectors are divided into two main categories, Hybrid (Hybrid) and Monolithic (Monolithic). With the development of radiation detectors, monolithic integrated detectors, which integrate a sensing layer and a circuit layer, become a demand for high-performance radiation image detectors, and are also an improvement on hybrid detectors: reduce the cost and reduce the quality. SOI technology holds promise for meeting these requirements.
The sensing layer (high-resistance substrate) and the circuit layer (low-resistance Si layer) of the SOI pixel detector are directly integrated on a single chip, the integration level is very high, the latch-up effect of a bulk silicon CMOS is eliminated, a Bump Bonding assembly process is not needed, and the process difficulty and the manufacturing cost are improved. However, the SOI pixel detector has problems such as back gate effect and crosstalk between a circuit and a sensor.
The article "f.f. khalid, g.w. depth, a.shenai, et al, monolithic Active pixel matrix with Binary Counters (MAMBO) asic. nuclear Science Symposium conductive record NSS/MIC), 2010ieee.2010, 1544-1550" proposes a Nested well structure (Nested well structure) which can isolate crosstalk between a circuit and a sensor and suppress the backgate effect, but the P-well structure completely contains a circuit portion and has a large capacitance of a sensitive node. Patent publication "application No.: the structure of the image sensor of CN200910083526.X, Gaoyu, Chenjie, spacious chapter, SOICMOS and the manufacturing method thereof' provides a monolithic integrated structure, but is irrelevant to the structure and the problem to be solved of the invention.
To maximize the charge collection efficiency, the charge collection well connecting the readout electrodes needs to be as large as possible; however, good gain or sensitivity requires a small sense node capacitance, which requires a relatively small charge collection well under the same conditions.
Disclosure of Invention
The invention aims to provide an SOI pixel detector structure which has smaller sensitive node capacitance, larger charge collection region and uniform electric field of a sensitive region.
The purpose of the invention is realized as follows:
an SOI pixel detector structure comprises a low-resistance silicon layer, an oxygen burying layer, a gate oxide layer, a high-resistance n-type substrate, a buried p-well, a buried n-well, a p-type detection well, a buried n-well leading-out electrode, a transmission gate electrode, a p-type detection well reading electrode and a back electrode;
the low-resistance silicon layer and the high-resistance n-type substrate are separated by the buried oxide layer; three buried oxide layers are arranged on the high-resistance n-type substrate, the three buried oxide layers are separated by a transmission gate electrode, and the low-resistance silicon layer is arranged above the buried oxide layers on the two sides; reverse bias buried n wells are respectively arranged below the two buried oxide layers; the reverse bias buried n-well is surrounded by the buried p-well; the leading-out electrode penetrates through the low-resistance silicon layer and the buried oxide layer to be connected with the buried n well so as to shield the influence between the substrate and the circuit layer and a diode formed between the reverse-bias buried n well and the buried p well; the p-type detection trap is arranged below the two buried oxide layers, the p-type detection trap is arranged below the buried oxide layer in the middle, the reading electrode penetrates through the buried oxide layer to be connected with the p-type detection trap, and the gate oxide layer is arranged below the transmission gate electrode; the bottom of the high-resistance n-type substrate is provided with a back electrode.
The whole high-resistance n-type substrate is used up as a charge sensitive area; namely a buried p-well for charge collection and storage and a p-type detection well for charge detection with a cross-talk prevention doped region in between.
The two p-wells are two n-wells, at the moment, the corresponding substrate is of a p type, and the original reverse bias buried n-well is the p-well.
The p-type detection well 306 for charge detection is much smaller than the buried p-well 304 for charge collection.
The invention has the beneficial effects that: the invention provides an SOI pixel detector structure. The structure keeps the characteristic of shielding the influence of the substrate voltage on the circuit layer; the larger buried p-well forms a large charge collection and storage area, and a more uniform electric field is formed in the sensitive area, so that the charge collection efficiency is improved; and the smaller p-type detection well is used as a detection area and is connected with a reading electrode, so that the capacitance of a sensitive node of the SOI pixel detector is reduced.
Drawings
Fig. 1 shows a proposed structure of a buried p-well SOI pixel.
Fig. 2 shows a proposed nested-well SOI pixel structure.
Fig. 3 shows an SOI pixel structure proposed by the present invention.
Fig. 4-7 are schematic diagrams of specific steps of a pixel structure according to an embodiment of the invention.
FIG. 8 is a graph of the pixel readout signal versus the amount of collected charge according to the present invention.
Detailed Description
The invention is further described below with reference to the following figures.
Aiming at the SOI pixel structure in the figures 1 and 2, an SOI pixel detector structure which has high detection efficiency and high gain is provided, and meanwhile, the shielding performance between a sensor part and a circuit layer of the detector structure is ensured.
In the SOI pixel structure, two embedded p-wells are formed, a larger embedded p-well is used for forming a large charge collection and storage area, and a more uniform electric field is formed in a sensitive area; the smaller p-type detection wells serve as detection regions and are connected to readout electrodes.
The technical scheme of the invention is as follows:
according to the invention, an SOI pixel detector structure comprises a low-resistance silicon layer 301, a buried oxide layer 302, a gate oxide layer 302a, a high-resistance n-type substrate 303, a buried p-well 304, a buried n-well 305, a p-type detection well 306, a buried n-well extraction electrode 307, a transmission gate electrode 308, a p-type detection well reading electrode 309 and a back electrode 310;
the low-resistance silicon layer 301 and the high-resistance n-type substrate 303 are separated by a buried oxide layer 302; three buried oxide layers 302 are arranged on the high-resistance n-type substrate 303, the three buried oxide layers 302 are separated by a transmission gate electrode 308, and the low-resistance silicon layer 301 is arranged above the buried oxide layers 302 on the two sides; reverse bias buried n wells 305 are respectively arranged below the two buried oxide layers 302; a reverse biased buried n-well 305 is surrounded by a buried p-well 304; the extraction electrode 307 passes through the low-resistance silicon layer 301 and the buried oxide layer 302 to be connected with the buried n-well so as to shield the influence between the substrate 303 and the circuit layer 301 and reversely bias a diode formed between the buried n-well 305 and the buried p-well 304; the p-type detection trap 306 is arranged below the two buried oxide layers 302, the p-type detection trap 306 is arranged below the middle buried oxide layer 302, the reading electrode 309 penetrates through the buried oxide layer 302 to be connected with the p-type detection trap, and the gate oxide layer 302a is arranged below the transmission gate electrode 308; the bottom of the high resistance n-type substrate 303 is provided with a back electrode 310.
The implementation steps are as follows:
exemplary embodiments are described with reference to the accompanying drawings. For purposes of clarity, the figures have been simplified or enlarged in nature. The position of a feature layer or region may represent a relative position, but the actual situation is not necessarily to the same scale as in the schematic.
Fig. 1 shows a proposed structure of a buried p-well SOI pixel. The structure includes a low resistance silicon layer (circuit layer) 101, a buried oxide layer 102, a high resistance substrate 103, a buried p-well or buried n-well 104, a readout electrode 105, and a back electrode 106.
Fig. 2 shows a proposed nested-well SOI pixel structure. The structure comprises a low-resistance silicon layer (circuit layer) 201, a buried oxide layer 202, a high-resistance n-type substrate 203, a buried p-well 204, a buried n-well 205, a readout electrode 206, a buried n-well extraction electrode 207 and a back electrode 208.
Fig. 3 shows an SOI pixel structure proposed by the present invention. The high-resistance buried oxide semiconductor device comprises a low-resistance silicon layer (circuit layer) 301, a buried oxide layer 302, a gate oxide layer 302a, a high-resistance n-type substrate 303, a buried p-well 304, a buried n-well 305, a p-type detection well 306, a buried n-well extraction electrode 307, a transmission gate electrode 308, a p-type detection well reading electrode 309 and a back electrode 310.
Fig. 4-7 focus on the formation of wells in pixels. The method comprises the following steps:
and selecting or preparing SOI materials. Comprises a low-resistance silicon layer (circuit layer) 301, a buried oxide layer 302 and a high-resistance n-type substrate 303. The thickness of the low-resistance silicon layer (circuit layer) 301 is 40 nanometers, the thickness of the buried oxide layer 302 is about 200 nanometers, and the resistivity of the high-resistance n-type substrate 303 is 1000 omega cm (other specifications can be selected from 1000 omega cm-10000 omega cm according to requirements).
The buried p-well 304, the buried n-well 304, and the p-type probe well 306 are formed by using a mask lithography technique and an ion implantation method.
As shown in FIG. 4, the buried p-well 304 is formed by implanting boron ions, e.g., at an energy of 150kev and a dose of 7E11/cm2。
As shown in FIG. 5, the buried n-well 305 is formed by implanting phosphorus ions, for example, at 200kev energy and 5E12/cm dose2。
The energy of the buried p-well and the buried n-well needs to be controlled, so that the doping concentration peak value is positioned below the buried oxide layer.
As shown in FIG. 6, p-type detection trap 306 is formed by implanting boron ions, e.g., at an energy of 60kev and a dose of 1E15/cm2。
Forming a transfer gate, as shown in FIG. 7, using etching technique and dry oxidation to form a gate oxide layer 302a with a thickness of 10 nm, doping the channel region, and adjusting the threshold of the transfer gate by implanting phosphorus ions, such as with an energy of 10kev and a dose of 4E11/cm2. Forming a penetration-preventing doped region between the buried p-well 304 and the p-type detection well 306 by implanting phosphorus ions, for example, performing doping twice with energy of 200kev and 500kev respectively and dose of 2E12/cm2。
Forming an electrode. Polysilicon is deposited and excess portions are removed to form the transfer gate electrode 308. By etching technique and filling, a buried n-well lead-out electrode 307 and a p-type detection well readout electrode 309 are formed. The backside uses ohmic metal contacts to form the backside electrode 310.
FIG. 8 is a graph of the pixel readout signal versus the amount of collected charge according to the present invention. The transfer curve possesses good linearity.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention. Many modifications and variations may be made without departing from the spirit or scope of the invention as defined in the appended claims.
Claims (2)
1. An SOI pixel detector structure comprises a low-resistance silicon layer (301), a buried oxide layer (302), a gate oxide layer (302a), a high-resistance n-type substrate (303), a buried p-well (304), a reverse bias buried n-well (305), a p-type detection well (306), a buried n-well extraction electrode (307), a transmission gate electrode (308), a p-type detection well reading electrode (309) and a back electrode (310);
the method is characterized in that: the left side and the right side of the top of the high-resistance n-type substrate (303) are respectively provided with a low-resistance silicon layer (301), and the two low-resistance silicon layers (301) and the high-resistance n-type substrate (303) are separated by an oxygen burying layer (302); the left side and the right side of the high-resistance n-type substrate (303) are respectively provided with an anti-bias buried n well (305); the two reverse-bias buried n wells (305) respectively correspond to the two low-resistance silicon layers (301) up and down in position, the reverse-bias buried n wells (305) are separated from the low-resistance silicon layers (301) by the buried oxide layer (302), and the reverse-bias buried n wells (305) are surrounded by deepened buried p wells (304); the buried n-well extraction electrode (307) penetrates through the low-resistance silicon layer (301) and the buried oxide layer (302) to be connected with the buried n-well (305); a p-type detection well (306) is arranged between the two reverse bias buried n wells (305), a buried oxide layer (302) is arranged above the p-type detection well (306), and a readout electrode (309) penetrates through the buried oxide layer (302) and is connected with the p-type detection well (306); the buried oxide layer (302) below the low-resistance silicon layer (301) is separated from the buried oxide layer (302) above the p-type detection trap (306) through a transmission gate electrode (308), and a gate oxide layer (302a) is arranged below the transmission gate electrode (308); a back electrode (310) is arranged at the bottom of the high-resistance n-type substrate (303);
the entire high-resistance n-type substrate (303) is depleted into a charge sensitive region; the buried n-well extraction electrode (307) is connected with a voltage to shield the influence between the high-resistance n-type substrate (303) and the low-resistance silicon layer (301) and to reversely bias a diode formed between the buried n-well (305) and the buried p-well (304); the buried p-well (304) is used for charge collection and storage, the p-type detection well (306) is used for charge detection, and a cross-over prevention doped region exists between the buried p-well (304) and the p-type detection well (306);
the p-type detection well (306) for charge detection is smaller than the buried p-well (304) for charge collection.
2. An SOI pixel detector structure as claimed in claim 1, wherein: the buried p-well (304) and the p-type detection well (306) are replaced by n-wells, the reverse bias buried n-well (305) is replaced by a p-well, and at the moment, the corresponding substrates are p-type.
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