經濟部智慧財產局員工消費合作社印製 493073 A7 B7 五、發明說明（/) 本發明係關於一種單片式半導體檢測器。本發明更關 於一種低溫半導體檢測器，以及一種增加該檢測器中之電 荷收集深度的方法。 供檢測離子化粒子與離子化放射線之半導體檢測器係 普遍使用於各式各樣之應用中，例如使用於高能量物理實 驗、使用於供檢測X射線與r射線之醫藥領域、以及使用 於大量之工業控制製程中。此等檢測器係敘述於G.F.Knoll 所著並由L Wiley & Sons出版之”放射線檢測及測量”一書 中。 一種最簡單之習知的放射線檢測器係顯示於第一圖。 此檢測器包含一 p-n二極體10，其係建立於一半導體基板 11。該二極體之端子12係連接至一用以偏壓該二極體接合 面14之一直流偏壓電路13，以及連接至用以將端子12所 *二 收到訊號轉換爲可讀出格式之讀出電路15。典型而言，讀 出電路包括一放大器16與一儀表17。 使用時，一電壓係施加至端子12，俾使該二極體係逆 向偏壓。此舉引起半導體基板11之空乏(depletion)。入射 於空乏基板11上之離子化放射線將建立電子-電洞對。歸 因於基板11中之電場，所建立之該等電子與電洞係加速並 以相反方向行進穿過基板。此舉引起電荷將係感應於二極 體之端子上。連接至二極體端子12之讀出電子電路15係 接著用以放大該電荷，將其轉變爲供讀出之一適當格式。 於第一圖所示型式之一些檢測器中，在讀出電路之第 一放大級的輸入處之電容係高的。此係不佳，因爲其具有 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------訂‘----<-----線 (請先閱讀背面之注意事項再填寫本頁) 493073 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（y) 不利的效應於訊號至雜訊比。 第一圖之檢測器的另一個缺點爲，槪括而言，所使用 之半導體材料必須是商純度者以得到足夠大的收集深度， 意謂著該材料含有少量摻雜之雜質與建立電荷陷阱〇rap)之 少量雜質。低摻雜位準有助基板之空乏。電荷陷阱必須最 小化，以防止電荷在其到達收集電極或基板背側之前被捕 捉。典型而言，係使用非常純之矽，舉例而言，其具有雜 質密度範圍爲1012至ΙΟ13 αιΓ3。然而，對於某些應用，例如 檢測可見光，離子化放射線將不會穿透深入至基板，因此 可使用較低純度之材料。此係因爲所需電荷集中深度並不 非常高。不過，於多數放射線檢測器之發展中係有一限制 ，即欲達成足夠之電荷收集深度，於製造處理中必須使用 高純度之半導體。此係排除運用基於低純度材料之商用製 程以製造檢測器的可能性。 過去數年以來，具有積體檢測器電子電路與讀出電子 電路於同一片半導體上之單片式半導體檢測器已廣受注目 。此係因爲僅使用單一晶片而非二個晶片之單片式元件係 較爲強健(robust)、較爲便宜且較薄。此外，典型而言，於 一單片式檢測器之第一放大級的輸入之電容係小的。此係 有利的，因其提高訊號至雜訊比，且降低於讀出電路之需 求。然而，當以第一圖之檢測器來達成足夠之電荷收集深 度時，單片式檢測器通常必須由高純度半導體所作成。此 舉排除了使用標準商用製程之可能性，其係基於低純度材 料。 4 $紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------訂·----：-----線 (請先閱讀背面之注意事項再填寫本頁) 493073 經濟部智慧財產局員工消費合作社印製 A7 ___Β7__ 五、發明說明（^ ) 不過，藉著運用於高純度基板上所開發之標準化互補 金氧半導體(CMOS)製程，已可製造出具有結果成功之單片 式檢測器。CMOS係一種眾所周知的製程，其涉及構成串 列組合之η型(NM0S)與p型(PM0S)電晶體於一半導體基板 上。數位靜態CMOS電路並不會消耗固定(常駐)功率，因 爲當該電路使用時在電流路徑中之任一 NM0S電晶體或 PM0S電晶體係不導通，因而防止靜態電流之流動。 第二圖顯示一種CMOS單片式檢測器，其係由 Sherwood Parker 於 Nucl· Instr. & Meth· A275，494(1989 年) 之論文“供粒子檢測之建議VLSI圖素裝置”中提出。此種 檢測器具有一 n型基板20，於基板之一正面係設有在一 p 型電極22的相對側上之二個η型井21。ρ型電極22係與η 型基板20構成一個二極體，且作用爲供收集歸因於入射放 射線之離子化電荷的集極。於Ρ型電極22上之一逆向偏壓 將使基板20空乏。讀出電路係含於η型井21中，供將歸 因於Ρ型電極22所收集的電荷轉換爲可讀出之格式，該讀 出電路係連接至收集電極22。 η型井21係作用爲拉第籠(Faraday cage)，用於讀出電 路，俾使電路中之暫態將無法耦合至檢測元件22。η型井 21另外提供一電場，其將歸因於離子化放射線所產生的訊 號電荷導引朝向ρ型收集電極22。然而，爲使基板20完 全空乏，且爲使電荷流線轉向至收集電極22，則於電極22 與η型井21之間係施加大的電位差，且收集電極22之面 積必須爲相當大。此係不佳的，因爲連接至收集電極22之 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I---------------訂r I丨—----線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 493073 A7 B7 五、發明說明（中） 讀出電路係暴露於大電位差’其可能造成損壞。此外，可 用以容納此讀出電路之空間係受限。 爲克服有關第二圖之檢測器的井所需高電壓之問題， 另一種運用CMOS製程所製造之放射線檢測器係開發。此 係顯示於第三圖中。於此例中’一 P-n接合面檢測元件係 藉著一同質N+植入物23於一 p型基板24之背側而構成。 一金屬接點25係設於N+植入物23之上，以允許施加一偏 壓電壓至該二極體。收集電極26係設於基板24之正面上 ，電極26係p型擴散接點。η型井27係相鄰於p型收集電 極26，並含有讀出電路。 藉著施加電壓至接點25以逆向偏壓該接合面，基板 24可係作空乏。入射於空乏之基板24上的離子化放射線 產生電子一電洞對。歸因於基板24中之電場，所產生的電 子與電洞係加速並以相反方向行進穿過基板24。此舉使得 電荷係感應於收集電極26。於η型井27·中之讀出電子電 路係接著用以放大電荷，將其轉變爲可供讀出之適當格式 〇 第三圖之檢測器的一個優點爲，二極體之高電場區域 係與前電路分離。以此方式，欲將電荷流由電路其餘部分 轉向至收集電極26所需於并27上的偏壓係降低。此舉允 許低電壓，以及介於收集電極26與η型井27中的讀出電 路間之一直接的直流連接。 第三圖之檢測器的一個缺點爲，介於裝置背側接合面 與前側收集電極26之間的區域需作完全空乏，以避免將所 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------訂—^-----線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 493073 A7 B7 五、發明說明（Γ) 有之收集電極26短路。此結構之另一個缺點爲，若使用一 η型井，僅有PMOS電晶體可係實施用於各檢測元件部分 之讀出電路，雖然CMOS電路可係使用於在檢測區域外側 之裝置周邊。此檢測器之又一個缺點爲，基板必須係成型 於二側上。此舉係難以實行，而使得製程較爲複雜。 本發明之一個目的係提出一種單片式半導體放射線檢 測器，其可克服前技上述缺點之至少一者。 本發明之另一個目的係提出一種提高於半導體放射線 檢測器中之電荷收集深度的方法。 根據本發明之第一個特點，係提出一種半導體放射線 檢測器，其包含一半導體基板，於半導體基板之正(前)面 上係設有第一半導體井與第二半導體井，第一井係與半導 體基板構成一個二極體並係作用爲一集極以收集歸因於入 、㈣ 射放射線之訊號，第二井含有係連接至集極之讀出電路， 其中一偏壓接點係提供用以偏壓該二極體，且讀出電路係 交流耦合至集極。 此種檢測器之一個優點爲，讀出電路係與施加以偏壓 該檢測器之直流電壓隔離。此舉允許使用足夠高之偏壓以 將電荷由第二井之下而吸引至收集井，俾使終止於第二井 之電荷係最小化。藉此方式，在不直接施加高電壓至第二 井中的電路之下，可改善電荷之收集，且可偵出放射線， 即使當其係入射於覆蓋有讀出電路之區域中。 較佳而言，藉著運用電容器將讀出電路連接至集極， 交流耦合係可達成。該電容器可係由金屬互連或者介於擴 7 本紙張尺度適用中國國家標準(cnS)A4規格（210 X 297公釐） ' ------：---------------訂-•丨—：-----線 (請先閱讀背面之注意事項再填寫本頁) 493073 經濟部智慧財產局員工消費合作社印製 A7 __B7 五、發明說明（t ) 散與金屬互連而構成。 半導體基板可係η型或P型。當基板係η型’則構成 二極體之第一井係Ρ型井，而含有讀出電路之井可係η型 或ρ型。當基板係？型，則構成二極體之第一井係11型， 而含有讀出電路之井可係Ρ型或η型。 將可理解的是，若第一與第二井係相同型式之半導體 材料，則其須作彼此隔離。此係因爲其將係以極爲不同之 電位而作偏壓。 第一與第二井可係運用CMOS製程而作限定。 當第一井係n型時該偏壓接點可包含P+植入物，或者 是，當第一井係ρ型時該偏壓接點可包含Ν+植入物。當第 一井係η型時該偏壓接點可包含PM0S電晶體，或者是， 當第一井係Ρ型時該偏壓接點可包含NM0S電晶體。 ，二 根據本發明之另一個特點，係提出一種製造放射線檢 測器之方法，該檢測器係實施本發明之第一個特點，該種 方法包含運用CMOS製程技術。 根據本發明之又一個特點，係提出一種放射線檢測系 統，其包含如本發明第一個特點所界定之一放射線檢測器 ，以及用以冷却放射線檢測器之一冷却系統。 較佳而言，該冷却系統係適以冷却檢測器至低溫。 運用CMOS製程技術以製造本發明此特點之檢測器的 一個優點爲，CMOS裝置可操作於低溫下，俾使無需特殊 之製程技術。此外，整體電力消耗係相當低，其意謂著冷 却系統不必吃力地運轉以維持所欲之溫度。 8 t氏張尺度適用中國國家標準（CNS)A4規格_ (21〇 X 297公爱)--- -----I---------------訂-----_-----線 (請先閱讀背面之注意事項再填寫本頁) 493073 Α7 Β7 五、發明說明（j ) 根據本發明之再一個特點，係提出一種提高於半導體 放射線檢測器中之電荷收集深度的方法，包含冷却該半導 體放射線檢測器。 此種方法之一個優點爲，可使用相當低純度之半導體 於放射線檢測器，而先前係需高純度材料。當需要大面積 之檢測器時，此優點可代表一實質上的成本節省。 較佳而言，該檢測器係冷却至50K到200K(絕對溫度) 之範圍的溫度。 本發明所實施之一種方法及檢測器將藉由僅爲舉例用 之實例而作說明，並參照下列圖式，其中： 第一圖係顯示一種習知檢測器； 第二圖係顯示一種前技CMOS單片式檢測器； 第三圖係顯示另一種前技之檢測器； 第四圖係一半導體裝置之橫截面； 第五圖係透過一測試裝置之橫截面； 第六圖顯示對於第五圖之裝置而於室溫下所取得之電 荷譜；及 第七圖顯示對於不同施加偏壓電壓而於77K下所取得 之電荷譜。 第四圖之半導體裝置係一 CMOS裝置，其包含一 p型 基板30，於基板30之正面上爲一串列交替之η型井與p 型井。井31係η型井’其係與ρ型基板30構成一個一極 體，且作爲用以收集歸因於離子化放射線所產生在基板30 中的電荷之一集極。一重度摻雜Ρ+植入物34係位於η型井 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) --------訂----；-----線· 經濟部智慧財產局員工消費合作社印製 493073 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（& ) 31之中而遠離與ρ型基板30之邊界33，植入物34係使用 作爲供偏壓該二極體之一高電壓偏壓電極。該植入物係與 η型井31構成一個二極體，而η型井31依次係與基板30 構成一個二極體。以此方式，藉著施加電壓至植入物34， 可偏壓由η型井31與基板30所構成之二極體。Ρ+植入物 34另外作用爲供檢測器漏電流之一排出物(sink)。一重度摻 雜N+植入物35係亦設於η型井31中而與高電壓電極34分 離’其用以作爲供量測於η型井31中收集的電荷之一接點 〇 Ρ型井36係設於η型井31之相對側上。於η型井中 之Ν+植入物35係連接至位於一 ρ型井36中之讀出電路37 。讀出電路係用以將Ν+植入物35處所收到之訊號轉換爲 可讀取之格式。更多的η型井38係相鄰於各個ρ型并36 且係於基板30上，並含有另外的讀出電路。 一交流耦合電路39係連接於井31的接點35與井36 的讀出電路37之間，且包含一電容器40。此可係運用介 於金屬互連或者介於擴散與金屬互連之間的電容而實行。 此電路係作用爲介於井電位與讀出電路之間的一隔離電路 ，且允許於接點35所收集的電荷可係通過至讀出電路。 使用時，一高電壓係施加至偏壓電極34。此舉使得包 含η型井31與ρ型基板30的二極體之空乏。反之，含有 s買出電路之井係運用低電壓而作偏壓，以防止電荷係收集 於其中。 當發生離子化放射線時，電子電洞對係產生於空乏基 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------訂-—：-----線，j^^· (請先閱讀背面之注意事項再填寫本頁) 493073 經濟部智慧財產局員Η消費合作社印製 A7 _ B7_ 五、發明說明（1 ) 板中，其引起朝向η型井31之電荷流。爲了使電荷流轉向 朝向集極31而離開於相鄰的井36與38中之讀出電路37， 必須確保介於施加至η型井31以及井36與38之電位間係 有一足夠大的差距。以此方式，可使得訊號電荷之損失爲 最小。如前所述，過去以來此舉須施加高電壓至二極體而 引起問題。然而，因爲第四圖之裝置中係設有交流耦合電 路，讀出電路37係與高偏壓電壓隔離，故可避免對其之損 壞。 一旦電荷係收集於η型井31，其係通過接點35經由 交流耦合電路而轉移至讀出電路37。 作爲於η型井31中以偏壓η型井31的Ρ+植入物34之 一替代者，係可能使用包括PMOS電晶體之一電路。於此 情形時，必須留意將接近高電壓偏壓之電路部分由電路其 ，二 餘部分所分離。於各例中，必須留意適當偏壓該等含有讀 出電路之井以及讀出電路本身。 當第四圖之檢測器係使用一 Ρ+植入物34或PMOS電晶 體時，除了收集電極31之外的其他η型井的電荷收集應作 最小化，且歸因於電位障壁降低之貫穿應避免。此外，介 於收集電極31以及含有讀出電路37的井36與38之間的 擊穿應避免。爲達此目的，舉例而言，可使用一防護環， 或者可於相鄰ρ型井與收集電極之間形成一非常漸進之接 合面。 雖然運用CMOS製程所製造之檢測器已係說明，將可 瞭解的是，舉例而言，檢測器之井可含有諸如雙極性電晶 — 11 本^尺度適用中國國家標準（CNS)A4規格（210 X 297公髮) "" (請先閱讀背面之注意事項再填寫本頁) 訂----：-----線- 經濟部智慧財產局員工消費合作社印製 493073 A7 _ B7 五、發明說明（丨0 ) 體之其他元件。 桌四圖之裝置的優點可藉著將其冷却至例如之低 溫而作改善。已係發現的是，此舉可提高該裝置之電荷收 集涂度’且因此提局其整體靈敏度。誠然，提高電荷收集 深度之此種方法可係應用至任何放射線檢測器。舉例而言 ，第六與七圖顯示取自第五圖之放射線檢測器的電荷譜。 第五圖顯示一種放射線檢測器，其包含以商用CMOS 製程構成一 η型擴散層41於一 P型基板43之一個二極體 。基板43係例如1歐姆公分之低電阻率者，且係覆以較基 板爲少量摻雜之ρ型外延層45。建構成二極體之η型擴散 層41係一般使用於CMOS製程之η型井。一電極47係設 於該η型擴散層上，用以施加偏壓電壓至該二極體。該二 極體面積係爲500乘300平方微米之大小。 先前已曾思及，諸如第五圖者之低純度裝置將不適用 以收集歸因於離子化放射線而具有大穿透深度之電荷。誠 然，當此裝置係由室溫下之一 9°Sr(緦的人工放射性同位素) 源之電子所照射時，係不會偵出由該離子化放射線所產生 的任何電荷。此係可由第六圖看出，其顯示當施加偏壓爲 9.0伏特時取得之檢測器的電荷譜。此譜僅係訊號雜訊位階 。然而，當該取樣係冷却至77k時，可偵出歸因於具有大 穿透深度之離子化放射線的電荷。 第七(a)圖顯示當第五圖之檢測器係以來自9()Sr源之電 子而照射時於77k所收集的不同電荷譜。曲線A係施加電 壓爲0伏特之譜；曲線B係2.25伏特時之譜；曲線C係針 12 _ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------訂----τ-----線 (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 493073 A7 B7 V. Description of the Invention (/) The present invention relates to a single-chip semiconductor detector. The invention is more about a low temperature semiconductor detector and a method for increasing the depth of charge collection in the detector. Semiconductor detectors for detecting ionized particles and ionizing radiation are commonly used in a variety of applications, such as in high-energy physics experiments, in the medical field for detecting X-rays and r-rays, and in a large number of In the industrial control process. These detectors are described in the book "Radiation Detection and Measurement" by G.F. Knoll and published by L Wiley & Sons. One of the simplest known radiation detectors is shown in the first figure. The detector includes a p-n diode 10 which is built on a semiconductor substrate 11. The terminal 12 of the diode is connected to a DC bias circuit 13 for biasing one of the junction surfaces 14 of the diode, and is connected to convert the received signal of terminal 12 into a readable signal. Format readout circuit 15. Typically, the readout circuit includes an amplifier 16 and a meter 17. In use, a voltage is applied to terminal 12 to reverse-bias the bipolar system. This causes depletion of the semiconductor substrate 11. The ionized radiation incident on the empty substrate 11 will establish an electron-hole pair. Due to the electric field in the substrate 11, the established electrons and holes are accelerated and travel through the substrate in opposite directions. This will cause the charge to be induced on the diode terminals. The readout electronic circuit 15 connected to the diode terminal 12 is then used to amplify the charge and convert it into an appropriate format for readout. In some detectors of the type shown in the first figure, the capacitance at the input of the first amplifier stage of the readout circuit is high. This series is not good because it has 3 paper sizes that are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) --------------------- Order '---- < ----- line (please read the precautions on the back before filling out this page) 493073 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (y) Adverse effects on Signal to noise ratio. Another disadvantage of the detector of the first figure is that, in general, the semiconductor material used must be of commercial purity to obtain a sufficient collection depth, which means that the material contains a small amount of doped impurities and establishes charge traps. 〇rap) a small amount of impurities. The low doping level helps to empty the substrate. The charge trap must be minimized to prevent charge from being captured before it reaches the collection electrode or the backside of the substrate. Typically, very pure silicon is used. For example, it has a impurity density ranging from 1012 to 1013 αιΓ3. However, for some applications, such as detecting visible light, ionized radiation will not penetrate deep into the substrate, so lower purity materials can be used. This is because the required charge concentration depth is not very high. However, there is a limitation in the development of most radiation detectors, that is, to achieve a sufficient charge collection depth, a high-purity semiconductor must be used in the manufacturing process. This excludes the possibility of using a commercial process based on low purity materials to make the detector. Over the past few years, monolithic semiconductor detectors with integrated detector electronic circuits and readout electronic circuits on the same semiconductor have attracted much attention. This is because monolithic components that use only a single chip rather than two are more robust, cheaper, and thinner. In addition, typically, the capacitance at the input of the first amplifier stage of a monolithic detector is small. This is advantageous because it increases the signal-to-noise ratio and reduces the need for readout circuits. However, when sufficient charge collection depth is achieved with the detector of the first figure, the monolithic detector must usually be made of a high-purity semiconductor. This eliminates the possibility of using standard commercial processes, which are based on low purity materials. 4 $ Paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) --------------------- Order · ----:- --- Line (Please read the precautions on the back before filling this page) 493073 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ___ Β7__ V. Description of the Invention (^) However, it is developed for use on high-purity substrates. Standardized complementary metal-oxide-semiconductor (CMOS) processes have made it possible to produce monolithic detectors with successful results. CMOS is a well-known process that involves forming n-type (NM0S) and p-type (PM0S) transistors in a serial combination on a semiconductor substrate. Digital static CMOS circuits do not consume fixed (resident) power, because any NM0S transistor or PM0S transistor system in the current path is not conducting when the circuit is used, preventing static current from flowing. The second figure shows a CMOS monolithic detector, which was proposed by Sherwood Parker in Nucl. Instr. &Amp; Meth. A275, 494 (1989) "Proposed VLSI Pixel Device for Particle Detection". This type of detector has an n-type substrate 20, and two n-type wells 21 on opposite sides of a p-type electrode 22 are provided on one front surface of the substrate. The p-type electrode 22 forms a diode with the n-type substrate 20 and functions as a collector for collecting ionized charges due to incident radiation. A reverse bias on the P-type electrode 22 will leave the substrate 20 empty. A readout circuit is contained in the n-type well 21 for converting the charge collected due to the P-type electrode 22 into a readable format, and the readout circuit is connected to the collection electrode 22. The η-type well 21 is used as a Faraday cage for reading the circuit, so that the transient state in the circuit cannot be coupled to the detection element 22. The n-type well 21 additionally provides an electric field that directs the signal charge due to ionizing radiation toward the p-type collecting electrode 22. However, in order to completely empty the substrate 20 and to turn the charge flow line to the collecting electrode 22, a large potential difference is applied between the electrode 22 and the n-type well 21, and the area of the collecting electrode 22 must be relatively large. This is not good because the size of the paper connected to the collector electrode 22-5 applies to the Chinese National Standard (CNS) A4 (210 X 297 mm). I --------------- Order r I 丨 —---- line (please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 493073 A7 B7 V. Description of the invention (middle) The readout circuit is exposed to a large potential difference 'It may cause damage. In addition, the space available to accommodate this readout circuit is limited. In order to overcome the problem of the high voltage required for the wells of the detector of the second figure, another radiation detector manufactured using a CMOS process was developed. This system is shown in the third figure. In this example, the '-P-n junction detection element is constituted by a homogeneous N + implant 23 on the back side of a p-type substrate 24. A metal contact 25 is provided on the N + implant 23 to allow a bias voltage to be applied to the diode. The collecting electrode 26 is provided on the front surface of the substrate 24, and the electrode 26 is a p-type diffusion contact. The n-type well 27 is adjacent to the p-type collecting electrode 26 and includes a readout circuit. By applying a voltage to the contact 25 to reverse bias the joint surface, the substrate 24 can be left empty. The ionized radiation incident on the empty substrate 24 generates an electron-hole pair. Due to the electric field in the substrate 24, the generated electrons and holes are accelerated and travel through the substrate 24 in opposite directions. This causes the charge to be induced in the collecting electrode 26. The readout electronic circuit in the n-type well 27 · is then used to amplify the charge and convert it into a suitable format for readout. One advantage of the detector in the third figure is that the high electric field region of the diode is Separate from the front circuit. In this way, the bias system required to divert the charge flow from the rest of the circuit to the collector electrode 26 is reduced. This allows a low voltage and a direct DC connection between the collection electrode 26 and the readout circuit in the n-well 27. One disadvantage of the detector in the third figure is that the area between the rear-side joint surface of the device and the front-side collecting electrode 26 needs to be completely empty to avoid applying the 6 paper sizes to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) --------------------- Order — ^ ----- line (Please read the precautions on the back before filling this page) Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 493073 A7 B7 V. Description of the Invention (Γ) Some of the collecting electrodes 26 are short-circuited. Another disadvantage of this structure is that if an n-type well is used, only the PMOS transistor can be implemented as a readout circuit for each detection element portion, although the CMOS circuit can be used around the device outside the detection area. Another disadvantage of this detector is that the substrate must be formed on both sides. This is difficult to implement and makes the process more complicated. It is an object of the present invention to provide a monolithic semiconductor radiation detector which can overcome at least one of the aforementioned disadvantages of the prior art. Another object of the present invention is to provide a method for increasing the depth of charge collection in a semiconductor radiation detector. According to a first feature of the present invention, a semiconductor radiation detector is provided. The semiconductor radiation detector includes a semiconductor substrate. A first semiconductor well and a second semiconductor well are arranged on the front (front) surface of the semiconductor substrate. Forms a diode with the semiconductor substrate and acts as a collector to collect signals due to incoming and outgoing radiation. The second well contains a readout circuit connected to the collector. One of the bias contacts is provided It is used to bias the diode, and the readout circuit is AC-coupled to the collector. One advantage of this type of detector is that the readout circuit is isolated from the DC voltage applied to bias the detector. This allows the use of a sufficiently high bias voltage to draw the charge from below the second well to the collection well, minimizing the charge system terminating in the second well. In this way, the collection of charge can be improved without directly applying a high voltage to the circuit in the second well, and radiation can be detected even when it is incident in an area covered with a readout circuit. Preferably, by using a capacitor to connect the readout circuit to the collector, AC coupling can be achieved. The capacitor can be interconnected by metal or expanded between 7 paper sizes. Applicable to China National Standard (cnS) A4 specification (210 X 297 mm) '------: ---------- ----- Order- • 丨 —: ----- line (please read the notes on the back before filling this page) 493073 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 __B7 V. Description of Invention (t) The powder is interconnected with metal. The semiconductor substrate may be of an n-type or a P-type. When the substrate is η-type ', the first well constituting the diode is a P-type well, and the well containing the readout circuit may be an η-type or a ρ-type. When the substrate system? Type, the first well system that constitutes the diode is the 11 type, and the well containing the readout circuit can be the P type or the η type. It will be understood that if the first and second well systems are of the same type, they must be isolated from each other. This is because it will be biased at a very different potential. The first and second wells can be defined using a CMOS process. The bias contact may include a P + implant when the first well system is n-type, or the bias contact may include an N + implant when the first well system is p-type. When the first well system is of the n-type, the bias contact may include a PMOS transistor, or when the first well system is of the P-type, the bias contact may include a NMOS transistor. According to another feature of the present invention, a method for manufacturing a radiation detector is proposed. The detector implements the first feature of the present invention. The method includes the use of CMOS process technology. According to another feature of the present invention, a radiation detection system is provided, which includes a radiation detector as defined by the first feature of the present invention, and a cooling system for cooling the radiation detector. Preferably, the cooling system is adapted to cool the detector to a low temperature. An advantage of using the CMOS process technology to manufacture the detector with this feature of the present invention is that the CMOS device can be operated at low temperatures, so that no special process technology is required. In addition, the overall power consumption is quite low, which means that the cooling system does not have to work hard to maintain the desired temperature. 8 t's scale is applicable to China National Standard (CNS) A4 specifications _ (21〇X 297 public love) --------------------------------------------- ---_----- line (please read the precautions on the back before filling out this page) 493073 Α7 Β7 V. Description of the invention (j) According to another feature of the present invention, it is proposed to improve a semiconductor radiation detector The method of charge collection depth includes cooling the semiconductor radiation detector. One advantage of this method is that relatively low purity semiconductors can be used for radiation detectors, which previously required high purity materials. This advantage can represent a substantial cost savings when large area detectors are required. Preferably, the detector is cooled to a temperature ranging from 50K to 200K (absolute temperature). A method and detector implemented by the present invention will be described by way of example only, and with reference to the following drawings, wherein: the first diagram shows a conventional detector; the second diagram shows a former technique CMOS single-chip detector; the third figure shows a cross section of another prior art detector; the fourth figure shows a cross section of a semiconductor device; the fifth figure shows a cross section through a test device; the sixth figure shows the fifth Figure 7 shows the charge spectrum obtained at room temperature; and the seventh figure shows the charge spectrum obtained at 77K for different applied bias voltages. The semiconductor device of the fourth figure is a CMOS device, which includes a p-type substrate 30. On the front side of the substrate 30, there are a series of alternating n-type wells and p-type wells. The well 31 is an n-type well ', which forms a monopolar body with the p-type substrate 30 and serves as a collector for collecting the electric charges generated in the substrate 30 due to ionizing radiation. A heavily doped P + implant 34 is located in the n-type well 9 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) (Please read the precautions on the back before filling this page)- ------ Order ----; ----- Line · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 493073 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. & Description of Invention 31, and away from the boundary 33 with the p-type substrate 30, the implant 34 is used as a high voltage bias electrode for biasing one of the diodes. The implant system and the n-type well 31 form a diode, and the n-type well 31 and the substrate 30 in turn form a diode. In this way, by applying a voltage to the implant 34, the diode composed of the n-type well 31 and the substrate 30 can be biased. The P + implant 34 additionally functions as a sink for one of the detector leakage currents. A heavily doped N + implant 35 is also located in the n-type well 31 and is separated from the high-voltage electrode 34. It is used as a contact for measuring the charge collected in the n-type well 31. 36 is provided on the opposite side of the n-type well 31. The N + implant 35 in the n-well is connected to a readout circuit 37 in a p-well 36. The readout circuit is used to convert the signal received at the N + implant 35 into a readable format. More n-type wells 38 are adjacent to each p-type and 36 and are on the substrate 30, and contain additional readout circuits. An AC coupling circuit 39 is connected between the contact 35 of the well 31 and the readout circuit 37 of the well 36 and includes a capacitor 40. This can be done using a capacitor between the metal interconnect or between the diffusion and the metal interconnect. This circuit acts as an isolation circuit between the well potential and the readout circuit, and allows the charge collected at the contact 35 to be passed to the readout circuit. In use, a high voltage is applied to the bias electrode 34. This makes the diode including the n-type well 31 and the p-type substrate 30 empty. Conversely, the well system containing the s-buy circuit uses a low voltage to bias it to prevent the charge system from collecting in it. When ionizing radiation occurs, the electron hole pairs are generated on the empty base. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm). -------------- ------- Order ---: ----- line, j ^^ · (Please read the precautions on the back before filling this page) 493073 Printed by A7 _ B7_, a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives Explanation of the invention (1) In the plate, it causes a charge flow toward the n-type well 31. In order for the charge flow to turn toward the collector 31 and leave the readout circuit 37 in the adjacent wells 36 and 38, it is necessary to ensure that there is a sufficient gap between the potentials applied to the n-type well 31 and the potentials in the wells 36 and 38. . In this way, the loss of signal charge can be minimized. As mentioned earlier, this has required applying high voltages to the diodes in the past to cause problems. However, because the device of the fourth figure is provided with an AC coupling circuit and the readout circuit 37 is isolated from the high bias voltage, damage to it can be avoided. Once the charge is collected in the n-type well 31, it is transferred to the readout circuit 37 through the contact 35 through the AC coupling circuit. As an alternative to the P + implant 34 in the n-well 31 with a biased n-well 31, it is possible to use a circuit including a PMOS transistor. In this case, care must be taken to separate the parts of the circuit close to the high-voltage bias from the rest of the circuit. In each case, care must be taken to properly bias the wells containing the readout circuit and the readout circuit itself. When the detector in the fourth figure uses a P + implant 34 or a PMOS transistor, the charge collection of other n-type wells other than the collection electrode 31 should be minimized and attributed to the reduction of the potential barrier. Should be avoided. In addition, breakdown between the collecting electrode 31 and the wells 36 and 38 containing the readout circuit 37 should be avoided. To this end, for example, a guard ring may be used, or a very progressive interface may be formed between an adjacent p-well and the collecting electrode. Although the detector manufactured using the CMOS process has been described, it will be understood that, for example, the well of the detector may contain, for example, a bipolar transistor — 11 This standard applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public) " " (Please read the notes on the back before filling this page) Order ----: ----- line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 493073 A7 _ B7 5 And other components of the invention description (丨 0). The advantages of the device of Table 4 can be improved by cooling it to, for example, a low temperature. It has been found that this can increase the charge collection coverage of the device 'and therefore improve its overall sensitivity. Indeed, this method of increasing the depth of charge collection can be applied to any radiation detector. For example, Figures 6 and 7 show the charge spectrum of the radiation detector taken from Figure 5. The fifth figure shows a radiation detector, which includes a diode comprising an n-type diffusion layer 41 and a P-type substrate 43 in a commercial CMOS process. The substrate 43 is, for example, one having a low resistivity of 1 ohm centimeter, and is covered with a p-type epitaxial layer 45 which is slightly doped than the substrate. The n-type diffusion layer 41 constituting the diode is generally used in an n-type well of a CMOS process. An electrode 47 is provided on the n-type diffusion layer to apply a bias voltage to the diode. The area of the diode is 500 by 300 square microns. It has been previously considered that a low purity device such as the one in the fifth figure would not be suitable for collecting charges with a large penetration depth due to ionizing radiation. It is true that when this device is irradiated with electrons from a 9 ° Sr (thorium artificial radioisotope) source at room temperature, it will not detect any charge generated by the ionized radiation. This series can be seen in the sixth figure, which shows the charge spectrum of the detector obtained when a bias voltage of 9.0 volts is applied. This spectrum is only the signal noise level. However, when the sampling system was cooled to 77k, the charge due to the ionized radiation having a large penetration depth could be detected. The seventh (a) diagram shows the different charge spectra collected at 77k when the detector of the fifth diagram is irradiated with electrons from a 9 () Sr source. Curve A is a spectrum with a voltage of 0 volts; Curve B is a spectrum with 2.25 volts; Curve C is a needle 12 _ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ----- ---------------- Order ---- τ ----- line (Please read the precautions on the back before filling this page)
五、發明說明（）V. Description of the invention ()
r 1 -七. 對4.5伏特時之譜，而曲線D則係9.0伏特時之譜。 如所預期，曲線C實質上對應於量測雜訊位階。當電 子源係移開時，此曲線係保持相同。然而，隨著施加之電 壓偏壓係提高，所收集之訊號亦提高以指出電荷收集深度 之增加。圖D顯示最大之增加。 第七(b)圖顯示曲線D，連同對於基礎雜訊之一最佳配 合（best-fit)圖E，以及所收集電荷之最佳配合的藍道 (Landau)分佈圖F。雜訊階層無法使得圖D中之藍道峰値可 被看出，但使用適當之最佳配合計算法，電子之數目係估 計爲約8000，其相當於110微米之垂直電荷收集深度。此 意謂著即便是使用相當低純度之材料，亦可偵出於檢測器 之基板深處的電荷。 ( 爲提高電荷收集深度之冷却該放射線檢測器，可提供 由相當低純度材料而製造檢測器之可能性。此外，冷却亦 使得可能運用例如CMOS或JFET製程之商用FET製程而 將粒子檢測器與讀出電路整合於單一基板上。 元件符號說明 10 二極體 11 半導體基板 12 二極體端子 13 DC偏壓電流 14 二極體接合面 15 讀出電路 16 放大器 13 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公楚) "' ------------------ ltf--------- SI (請先閱讀背面之注意事項再填寫本頁) 493073 A7 B7 參煩 請 爸委f員 無明f示 更 贲 容： | 月?日 η 〇之 五、發明說明（ 17 20 21 22 23 24 25 26 27 30 31 33 34 35 36 37 38 39 40 41 43 45 47 儀表 基板 Ν型井 電極 Ν+植入 Ρ型基板 金屬接點 收集電極 Ν型井 基板 井 、、息田 Ρ+植入 Ν+植入 Ρ型井 讀出電路 Ν型井 耦合電路 電容器 Ν型擴散層 Ρ型基板 Ρ型外延展 電極 14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)r 1-VII. For the spectrum at 4.5 volts, curve D is for the spectrum at 9.0 volts. As expected, curve C essentially corresponds to the measurement noise level. This curve remains the same when the electron source system is removed. However, as the applied voltage bias increases, so does the collected signal to indicate an increase in the depth of charge collection. Figure D shows the largest increase. The seventh (b) graph shows a curve D, along with a best-fit graph E for one of the fundamental noises, and a Landau profile F of the best fit of the collected charges. The noise level cannot make the blue channel peaks in Figure D visible, but using the appropriate best fit calculation method, the number of electrons is estimated to be about 8000, which is equivalent to a vertical charge collection depth of 110 microns. This means that even with relatively low purity materials, charges can be detected deep within the substrate of the detector. (Cooling the radiation detector to increase the depth of charge collection provides the possibility of manufacturing the detector from a relatively low purity material. In addition, cooling also makes it possible to combine particle detectors with The readout circuit is integrated on a single substrate. Component symbol description 10 Diode 11 Semiconductor substrate 12 Diode terminal 13 DC bias current 14 Diode junction surface 15 Readout circuit 16 Amplifier 13 This paper size applies to Chinese national standards ( CNS) A4 specification (21〇X 297), " '------------------ ltf --------- SI (Please read the Please fill in this page again for the matters needing attention) 493073 A7 B7 If you have any questions, please ask your dad to appoint members to clarify the situation: | Month and Day η 〇 Fifth, the invention description (17 20 21 22 23 24 25 26 27 30 31 33 34 35 36 37 38 39 40 41 43 45 47 Instrument substrate N-type well electrode N + implanted P-type substrate metal contact collection electrode N-well substrate substrate well, interest field P + implanted N + implanted P-well readout circuit N Type well coupling circuit capacitor N-type diffusion layer P-type substrate P-type epitaxial electrode 14 paper Scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm) (Please read the back of the precautions to fill out this page)