TW511287B - A CMOS image sensor device - Google Patents

Abstract

A image sensor device is formed on a semiconductor wafer comprising a silicon substrate of a first conductive type. The image sensor device includes a photo sensor, an insulation layer, a MOS transistor and a deep doped region. The photo sensor is composed of a shallow doped region of a second conductive type. The shallow doped region is formed on a surface of the substrate and has a first predetermined depth. The insulation layer has a second predetermined depth and is positioned on the surface of the substrate to surround the photo sensor. The second predetermined depth is greater than the first predetermined depth. The MOS transistor is formed on the semiconductor wafer and electrically connected with the photo sensor. The deep doped region of the first conductive type is formed in the substrate under the insulation layer, and a dopant concentration of the deep doped region has a Gauss distribution.

Description

> 11287 V. Description of the invention (1) Field of the invention The present invention is to provide a complementary metal-oxide-semiconductor image sensor (CMOS image sensor), especially one that can increase the quantum efficiency and avoid the road ▲ η ,. Complementary metal-oxide semiconductor image sensing on cross talk phenomenon. J% pieces (CMOS image sensor) ° Background description Solid-state image sensing elements, such as charge-coupled device CCD) and CMOS image sensor 'are commonly used as input devices for electronic images. Because the CMOS image sensor is manufactured using traditional semiconductor manufacturing, it has the advantages of lower manufacturing cost and smaller component size. CMOS image sensors have a wide range of applications, including personal computer cameras (PC Cameras) and digital cameras (digital cameras).

Please refer to FIG. 1 and FIG. 2. FIG. 1 is a top-view diagram of a semiconductor wafer of a conventional CMOS image sensor, and FIG. 2 is a cross-sectional view of the semiconductor wafer in FIG. diagram). The conventional CMOS image sensor contains three M0S electrical crystals, which are used as reset elements (reset M0S) and current sink elements, respectively.

Page 5 > 11287 V. Description of the invention (2) (current source follower) and 歹 selector (row selector), and a photodiode for sensing the intensity of light. As shown in FIG. 1 and FIG. 2, the conventional image sensor is fabricated on a semiconductor wafer 10 of a p-type substrate 12. The surface of the p-type substrate 12 includes an N-channel M0S region 30, which is used to make NMOS. The crystal 16 and a light sensing area 32 are used to make a photodiode 34. Each of the M0S transistors can be directly fabricated on the substrate 12, or a P-type well (not shown) or an N-type well (not shown) can be selectively formed in the substrate 12 first, and then Each MOS transistor is fabricated on the P-type well or the N-type well. The NM0S transistor 16 includes a gate formed by a conductive body 18. A sidewall 22 is provided around the gate, and a light ion implantation LDD layer 20 and a heavy ion implantation HDD (heavily doped drain) layer 24 are formed in the substrate 12 on both sides of the gate as Source and drain of NMOS transistor 16. Wherein, the HDD layer 24 of the light sensing region 32 is formed at the same time as the HDD layer 24 of the NMOS transistor 16, and the HDD layer 24 in the light sensing region 32 is bonded to the PN of the P-type substrate 12 (juncti ο η). An empty area is formed, thus forming one. Photodiode 3 4. In addition, a light trench isolation 14 is surrounded around the light sensing area 3 2, and a P-shaped well 13 is formed in the substrate 12 under each shallow trench isolation 14, the purpose of which is to avoid each photodiode 3 4 The generated junction current (juncti ο ncurrent) drifts laterally to the adjacent image sensing element, thereby reducing its resolution. ’Because of the structure of the conventional C Μ 0 S image sensing element, its light sensing area 3 2 is

V. Description of the invention (3) It is composed of a deep HDD layer 24, so the salt γ is located deep in the substrate 12. But when the empty area. —The space ϋ 孑 of the polar body 34 is converted into a predicate, and the photon number of incident light irradiates Ί, especially for short-wavelength light (for example, the incident depth light pair of θ t in blue light will be more serious. Η 面, 2?) Shallow, its sensing ί: the joint current is also located at the depth of 12 in the base, due to the μ; σ helium second zone, the effect of induced production direction drift is limited, and it is easy to cause the well 13 to block the occurrence of the joint current. Cross talk phenomenon Summary of the invention Therefore, the main purpose of the present invention is to efficiently and avoid cross talk and to provide a high-quantum sensing element. & Complementary CMOS image in the preferred embodiment of the present invention, on a semiconductor wafer, and the semiconductor image sensing element is made on a plastic substrate. The image sensing film package includes a first doped sensing region consisting of a second conductive type, which is formed on one of the substrate surfaces to a predetermined depth; a series of edge layers are provided on the surface of the substrate and surround the substrate. The predetermined depth of Zhou Bing in the light sensing area is greater than the first predetermined, laughter " and the MOS transistor is made on the semi-conductor ::::: Electrically connected to the light

Page 7> 11287 V. Description of the invention (4) The second and first conductive type deep doped regions are formed in the insulating layer H, and the dopant concentration and depth of the deep doped regions are Gaussian Knife cloth (Gauss distribution). Pinnong Zhanji The CMOS image sensing element produced by the present invention is located near the substrate surface and must be doped as a photosensitive region, so the photons and meshes received by the sensing element will not decrease with the incident depth. Especially for short-wavelength light with a shallow penetration depth (fePth), the sensing element has a Quantum efficiency. In addition, the second M0S image sensing element manufactured by the present invention further forms a deep doped region under the insulating layer, and the dopant concentration and depth of the bead doped region have a Gauss distribution (Gauss distf 1 but in). Therefore, it is possible to effectively avoid the cross-talk (c0s $ ta1k) phenomenon caused by the expansion of the junction voltage IL generated in the light sensing area to the adjacent sensing element. Detailed description of the invention

Please refer to FIG. 3 and FIG. 4. FIG. 3 is a top-view diagram of a semiconductor wafer of the CMOS image sensor of the present invention, and FIG. 4 is a cross sectional diagram of the semiconductor wafer extending along the BB direction of FIG. 3. . The CMOS image sensor of the present invention includes three M0S transistors, which are respectively used as a reset element (reset M 0 S), a current source follower, and a row selection switch (row se 1 ect 〇r). ), And a photodiode for sensing the intensity of light

Page 8> 11287 V. Description of the invention (5) Degree 0, as shown in Figs. 3 and 4, in the preferred embodiment of the present invention, the image sensor is fabricated on a p-type substrate 42 On semiconductor wafers, p-type

A surface of the ϋ42 is provided with a MOS region 52 for making NMOS transistors, and a light sensing region 54 for making a photodiode 5. As shown in FIG. 4, the image sensing of the present invention The light-sensing area 54 in the measurement element structure is composed of an N-type lightly-doped area 50, and the lightly-doped area 50 is formed on the surface of the substrate 4 2 for about 50 to 1 00A. Depth range. In addition, a sloping edge layer having a depth of about 400,000 A is disposed on the surface of the substrate 42 and surrounds the light sensing area 54. The insulating layer may be formed of a shallow trench isolation structure (^ 311 ° ~ Trench Isolation, STI) 4l or a field layer (not shown). The surface of the p-type substrate 42 of the present invention further includes a P-type deep doped region 45 formed in the substrate 4 2 below the shallow trench isolation 4 1, and the dopant concentration of the deeply doped region 4 5 and the sphericity are south. Gauss distribution. Since the depth of the shallow bead region 50 is smaller than the depth of the insulating layer in the shirt image sensing structure of the present invention, the deep doped region 45 formed below the insulating layer and the shallow doped region 50 are not adjacent to each other. . In the image-sensing 7L structure of the present invention, 'the lightly doped region constituting the light sensing region is formed in a substrate close to the surface of the wafer', so the shallowly doped region and the empty region formed by the interface of the substrate are close to the substrate surface . Since the empty 2 area

> 11287 V. Description of Invention (6) The function of receiving photons and converting them into electrons generates junction current, so the number of photons received will not be lost because the light must penetrate deeply into the substrate, which can improve The quantum efficiency of the sensing element of the present invention. In addition, a doped region formed under the insulating layer surrounding the photo-sensing region has a Gaussian distribution of dopant concentration and depth, so that the bonding current generated by the photo-sensing region can be effectively prevented from spreading to adjacent ones. The cross-ta 1 k phenomenon caused by the sensing element greatly improves the resolution of the sensing element. Compared with the conventional image sensing element structure, the image sensing element structure of the present invention uses a shallowly doped region as the light sensing region, so the quantum efficiency of the sensing element can be improved. Furthermore, the present invention is based on the light A deep doped region with a Gaussian distribution of dopant concentration and depth is formed below the insulating layer around the sensing region, so that the occurrence of crossover interference can be effectively avoided, and the resolution of the image sensing element can be improved. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the patentable scope of the present invention shall fall within the scope of the patent of the present invention. «

Page 10 > 11287 Simple explanation of the diagrams Simple explanation of the diagrams Figure 1 is a top view of a semiconductor wafer of a conventional image sensor. FIG. 2 is a cross-sectional view of the semiconductor wafer in FIG. 1 along the AA direction. FIG. 3 is a top view of the semiconductor wafer of the image sensor of the present invention. FIG. 4 is a cross-sectional view of the semiconductor wafer of FIG. Description of symbols in the illustration 10 Semiconductor wafer 12 P-type substrate 14 Shallow trench isolation 16 NMOS transistor 18 Conductor 20 LDD layer 22 Side wall 24 HDD layer 30 N-channel MOS region 32 Light sensing region 13 P-well 34 Photodiode Body 40 Semiconductor wafer 41 Shallow trench isolation 42 P-type substrate 43 NMOS transistor 45 Deeply doped region 50 Lightly doped region 51 Photodiode 52 N-channel MOS region 54 Light sensing region ❿

Page 11

Claims (1)

> 11287 6. Application scope 1. A complementary metal oxide semiconductor image sensor (CM0S image sensor), the image sensor is fabricated on a semiconductor wafer, and the surface of the semiconductor wafer contains a first A conductive type silicon substrate. The image sensing element includes: a light sensing area composed of a lightly doped area of a second conductive type, and the lightly doped area is formed on one of the substrate surfaces. A first predetermined depth; an insulation layer of a second predetermined depth is provided on the surface of the substrate and surrounds the light sensing area, and the second predetermined depth is greater than the first predetermined depth; a gold-oxide semiconductor transistor (MOS transistor) is fabricated on the semiconductor wafer and is electrically connected to the photo-sensing region; and a deeply-doped region of a first conductivity type is formed in a substrate below the insulating layer, and the dopant concentration of the deeply-doped region is The depth is a Gauss distribution. 2. For example, the CMOS image sensing element of the first patent application scope, wherein the first conductivity type is a P type and the second conductivity type is an N type. 3. For example, the CMOS image sensing element of the first patent application range, wherein the first conductivity type is N-type and the second conductivity type is P-type. 4. The CMOS image sensing element according to item 1 of the patent application scope, wherein the first predetermined depth is about 50˜100 A. Page 12 The CMOS image sensing element according to item 1 of the patent application scope, wherein the dopa margin layer sentence 4 _ s ^ 3 is a sulcus isolation structure (Shal low Trench Isolation, or Field Oxide Layer). g • _If the CMOS image sensing element in the first item of the patent application scope, where the predetermined depth is about 400 ~ 400 0 Angstroms. Γ ^ As the CMOS image sensing element in the second item of the patent application scope, where The $ 4 mixed region is a p-type well, and the depth of the p-type well is greater than 4,000 angstroms. ^ For example, the CMOS image sensing element of the scope of application for patent No. 3, wherein the 'replacement mixed region It is an N-type well, and the depth of the N-type well is greater than 4000 angstroms. 9. If the CMOS image sensing element of the first scope of the patent application, the > The cross talk phenomenon caused by the bonding current generated in the sensing area spreading to the phase sensing element. 10 on page 13 · If the CMOS image sensing element of the first patent application scope, wherein the shallowly doped region and the interface of the substrate form an empty region, the empty region can receive photons and be converted into electrons to generate a bonding current. (Juncti ο η current), because the empty region is close to the surface of the substrate, the number of received photons will not decrease with the incident depth, thereby increasing the quantum efficiency of the sensing element. 0 ^^ ~ -plane 90127194 Correction of W & W month & 'Scope of patent application ^ 1 · —A complementary metal-oxide-semiconductor image sensor (CMOS image) that can increase quantum efficiency and avoid cross talk sensor), the image sensing element is fabricated on a semiconductor wafer, and the surface of the semiconductor wafer includes a silicon substrate of a first conductivity type, and the image sensing element includes: a light sensing area, which is formed by a second The conductive type is composed of a shallowly doped region, and the shallowly doped region is formed on a surface of the substrate at a first predetermined degree; / = an insulating layer with a second predetermined depth is provided on The surface of the substrate surrounds the photo-sensing area, and the second predetermined depth is greater than the first predetermined depth; a MOS transistor is fabricated on the semiconductor wafer and electrically connected to the photo-sensing Region; and a deeply-doped region of a first conductivity type is formed in the substrate below the insulating layer, and the dopant concentration and depth of the deeply-doped region have a Gauss distribution to avoid the light sensing The bonding current generated in the region is diffused to the adjacent sensing elements, causing a phenomenon of cross interference (cr0ss t ^ lk); wherein the shallowly doped region forms an empty region with the interface of the substrate, and the empty region can receive Photons are converted into electrons to generate junction currents. Since the empty region is close to the substrate surface, the number of photons received will not decrease with the incident depth, thereby increasing the quantum efficiency of the sensing element. efficiency). No. 14 > 11287 6. Scope of patent application 1 2. The CMOS image sensing element according to item 11 of the scope of patent application, wherein the first conductivity type is P-type and the second conductivity type is N-type. 1 3. The CMOS image sensing element according to item 11 of the scope of patent application, wherein the first conductivity type is N-type and the second conductivity type is P-type. 14. The CMOS image sensing element according to item 11 of the patent application, wherein the first predetermined depth is about 50 ~ 100 0A. 15. The CMOS image sensing device according to item 11 of the application, wherein the insulating layer includes a shallow trench isolation structure (STI) or a field oxide layer. 16. The CMOS image sensing element according to item 11 of the patent application scope, wherein the second predetermined depth is about 400 ~ 400 Angstroms. 1 7. The CMOS image sensing element according to item 12 of the patent application scope, wherein the deeply doped region is a P-type well, and the depth of the P-type well is greater than 400 Angstroms. 1 8. The CMOS image sensing element according to item 13 of the patent application scope, wherein the deep doped region is an N-type well, and the depth of the N-type well is greater than 40000 Angstroms. Page 15