CN109901336A - Array substrate and its manufacturing method - Google Patents
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- CN109901336A CN109901336A CN201910259310.8A CN201910259310A CN109901336A CN 109901336 A CN109901336 A CN 109901336A CN 201910259310 A CN201910259310 A CN 201910259310A CN 109901336 A CN109901336 A CN 109901336A
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- transparency conducting
- conducting layer
- array substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 73
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 185
- 239000002184 metal Substances 0.000 claims description 52
- 229910052751 metal Inorganic materials 0.000 claims description 52
- 239000010409 thin film Substances 0.000 claims description 21
- 238000000059 patterning Methods 0.000 claims description 8
- 239000011241 protective layer Substances 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000002344 surface layer Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000012780 transparent material Substances 0.000 description 5
- 230000005611 electricity Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- Liquid Crystal (AREA)
Abstract
This announcement provides a kind of array substrate and its manufacturing method.The array substrate definition has switch region and pixel region, and the switch region of the array substrate includes: substrate；Gate, setting is on the substrate；Insulating layer is arranged on the gate；Channel layer is arranged on the insulating layer；First transparency conducting layer is arranged on the channel layer, wherein first transparency conducting layer is formed with fluting on the channel layer；Drain electrode is arranged on first transparency conducting layer, and is located at the side of the fluting；And source electrode, it is arranged on first transparency conducting layer, and be located at the other side of the fluting, wherein first transparency conducting layer extends to the pixel region from the switch region so that position the pixel region first transparency conducting layer as pixel electrode.
Description
Technical field
This announcement is related to field of display devices, more particularly to a kind of array substrate and its manufacturing method.
Background technique
As the resolution of display device improves, pixel aperture ratio decreased, thus cause the brightness of display device compared with
The problem of low and backlight cost increases.Therefore, improving pixel aperture ratio becomes development thin-film transistor LCD device (thin
Film transistor liquid crystal display, TFT-LCD) emphasis in need of consideration.
Aperture opening ratio refers to that the area of the light-permeable part of pixel accounts for the ratio between the area of pixel entirety.Pixel it is impermeable
The part of light includes the shielded area of data line, gate line, thin film transistor (TFT), storage capacitance and black matrix.Storage capacitance can be by shape
At on public electrode or being formed on gate.It, can be to avoid capacitor by the way that storage capacitance to be formed on public electrode
Coupling effect, but since this design needs to increase additional cabling, and existing public electrode uses lighttight metal material,
Cause aperture opening ratio lower.
Furthermore referring to Fig.1 and 2, Fig. 1 shows that a kind of partial schematic diagram of existing array substrate 10 and Fig. 2 are aobvious
The array substrate 10 of diagram 1 along A-A face line sectional view.As shown in Figure 1, array substrate 10 includes multiple pixels, wherein
Each pixel includes thin film transistor (TFT) 11 and pixel electrode 12.As shown in Fig. 2, thin film transistor (TFT) 11 includes gate 111, drain
112 and source electrode 113.During fabrication, it is formed after thin film transistor (TFT) 11, passivation layer 14 can be formed on thin film transistor (TFT) 11, connect
Passivation layer 14 above source electrode 113 open up via hole 13, finally pixel electrode 12 is formed on passivation layer 14 again.Via hole 13
Design be and then the signal of thin film transistor (TFT) 11 to be transferred to picture in order to ensure pixel electrode 12 and source electrode 113 are electrically connected
Plain electrode 12.However, 10 setting via holes 13 also result in aperture opening ratio reduction in array substrate.
In view of this, it is necessary to a kind of array substrate and its manufacturing method are proposed, to solve existing in the prior art ask
Topic.
Summary of the invention
To solve above-mentioned problem of the prior art, this announcement is designed to provide a kind of array substrate and its manufacturer
Method, by the way that public electrode to be used to the material of light transmission, and the structure of change array substrate, to omit for connecting film crystal
The setting of the via hole of pipe and pixel electrode, and then improve aperture opening ratio.
To reach above-mentioned purpose, this announcement provides a kind of array substrate, and the array substrate definition has switch region and pixel
Area, and the switch region of the array substrate includes: substrate；Gate, setting is on the substrate；Insulating layer, setting exist
On the gate；Channel layer is arranged on the insulating layer；First transparency conducting layer is arranged on the channel layer, wherein institute
It states the first transparency conducting layer and is formed with fluting on the channel layer；Drain electrode is arranged on first transparency conducting layer, and position
In the side of the fluting；And source electrode, it is arranged on first transparency conducting layer, and be located at the other side of the fluting,
Wherein first transparency conducting layer extends to the pixel region from the switch region, so that position is described the of the pixel region
One transparency conducting layer is as pixel electrode.
In one of them preferred embodiment of this announcement, the pixel region of the array substrate includes: the substrate；Second
Transparency conducting layer, setting is on the substrate；The insulating layer is arranged on second transparency conducting layer；And described
One transparency conducting layer is arranged on the insulating layer, wherein second transparency conducting layer transparent is led with corresponding described first
Electric layer is overlapped to constitute storage capacitance.
In one of them preferred embodiment of this announcement, the switch region of the array substrate also includes described second transparent
Conductive layer is arranged between the substrate and the gate.
In one of them preferred embodiment of this announcement, first transparency conducting layer is directly contacted with the source electrode, and institute
Pixel electrode is stated to connect with the source electrode.
This announcement also provides a kind of manufacturing method of array substrate, and the array substrate definition has switch region and pixel region,
And the manufacturing method includes: providing substrate；The first metal layer is formed on the substrate；Pattern the first metal layer
To form the gate of thin film transistor (TFT) in the switch region；Insulating layer is formed on the substrate and the first metal layer；?
Channel layer is formed on the insulating layer；The first transparency conducting layer is formed on the channel layer and the insulating layer；Described
Second metal layer is formed on one transparency conducting layer；And the patterning second metal layer is described thin to be formed in the switch region
The drain electrode of film transistor and source electrode, wherein first transparency conducting layer extends to the pixel region from the switch region, so that
Position the pixel region first transparency conducting layer as pixel electrode.
In one of them preferred embodiment of this announcement, formed after second metal layer on first transparency conducting layer,
Also include: forming the fluting for exposing the channel layer on first transparency conducting layer and the second metal layer, wherein
After patterning the second metal layer, the side and the source electrode that the drain electrode is formed in the fluting are formed in institute
State the other side of fluting.
In one of them preferred embodiment of this announcement, before the gate for forming thin film transistor (TFT), also include: in the base
The second transparency conducting layer is formed on plate；Form the first metal layer on second transparency conducting layer: patterning described the
Two transparency conducting layers and the first metal layer are existed with removing position in the first metal layer and reserved bit of the pixel region
Second transparency conducting layer of the pixel region, wherein position the pixel region second transparency conducting layer with it is corresponding
The first transparency conducting layer overlapping is to constitute storage capacitance.
In one of them preferred embodiment of this announcement, first transparency conducting layer is to be formed in the channel layer by entire surface
With on the insulating layer and the second metal layer is to be formed in first transparency conducting layer by entire surface；And in pattern
In the step of changing the second metal layer, the second metal layer of the removal position in the pixel region.
In one of them preferred embodiment of this announcement, first transparency conducting layer is directly contacted with the source electrode, and institute
Pixel electrode is stated to connect with the source electrode.
In one of them preferred embodiment of this announcement, after patterning the second metal layer, also include: described the
Two metal layers, the channel layer form protective layer on first transparency conducting layer.
Compared to prior art, this announcement embodiment is by the way that pixel electricity grade to be produced under the source electrode of thin film transistor (TFT)
Side.It designs whereby, does not need to open up for connecting thin film transistor (TFT) and pixel electricity between the switch region and pixel region of array substrate
The via hole of pole, can outputting data signals, therefore the occupied space of via hole can be saved, and then pixel unit can be effectively improved
Aperture opening ratio.Furthermore position is overlapped in the public electrode wire of pixel region with corresponding pixel electrode to form storage capacitance.Due to public affairs
Common-battery polar curve and pixel electrode are all made of to use transparent material, therefore can further improve the aperture opening ratio of pixel unit.
Detailed description of the invention
Fig. 1 shows a kind of partial schematic diagram of existing array substrate；
Fig. 2 shows the array substrate of Fig. 1 along the sectional view of A-A face line；
Fig. 3 shows the schematic diagram of the array substrate according to this announcement preferred embodiment；And
Fig. 4 A to Fig. 4 J is a series of sectional view, shows the manufacturing process of the array substrate of Fig. 3.
Specific embodiment
In order to which the above-mentioned and other purposes of this announcement, feature, advantage can be clearer and more comprehensible, it is excellent that spy is hereafter lifted into this announcement
Embodiment is selected, and cooperates institute's accompanying drawings, is described in detail below.
Referring to figure 3., the schematic diagram of the array substrate 20 according to this announcement preferred embodiment is shown.Array substrate 20 is
A portion of display panel.Array substrate 20 includes a plurality of gate line 28, multiple data lines 24, a plurality of public electrode wire
25 and multiple pixel units, plurality of pixel unit is defined by a plurality of gate line 28 and multiple data lines 24, and each
Pixel unit definition has switch region 21 and pixel region 22.Each public electrode wire 25 is arranged between two adjacent gate lines 28,
And public electrode wire 25 is Chong Die with the pixel electrode 27 of part, and then forms the storage capacitance 26 of pixel unit.
In this announcement, public electrode wire 25 is made of to use electrically conducting transparent material, therefore can effectively increase pixel list
The aperture opening ratio of member.It is understood that array substrate includes that storage capacitance is formed on public electrode will either to store electricity
Appearance is formed in this two types on gate.It is so that storage capacitance 26 is formed in 25 this type of public electrode wire in the present embodiment
Array substrate 20 for, it is only not limited to this.
As shown in figure 3, there is no be used between switch region 21 and pixel region 22 in the array substrate 20 of this announcement embodiment
The via hole (such as via hole 13 shown in FIG. 1) of thin film transistor (TFT) and pixel electrode is connected, therefore the occupied sky of via hole can be saved
Between, and then the aperture opening ratio of pixel unit can be effectively improved.Illustrate the array substrate of this announcement below by way of Fig. 4 A to Fig. 4 J
20 specific structure and manufacturing method.
A to Fig. 4 J referring to figure 4. is a series of sectional view, shows the manufacturing process of the array substrate 20 of Fig. 3.Battle array
The definition of column substrate 20 has switch region 21, pixel region 22 and contact zone 23.Firstly, as shown in Figure 4 A, provide substrate 301, and
The second transparency conducting layer of deposited in sequential 302 and the first metal layer 303 on substrate 301.Then, pass through half-tone mask (half
Tone mask, HTM) or gray tone exposure mask (gray tone mask, GTM) pattern the second transparency conducting layer 302 and the first gold medal
Belong to layer 303, to remove position in the first metal layer 303 of pixel region 22, and the second electrically conducting transparent in the reservation of pixel region 22 part
Layer 302, so that having the public electrode wire 25 being made of the second transparency conducting layer 302 in pixel region 22.Also, in switch region 21
The stepped construction being made of the second transparency conducting layer 302 and the first metal layer 303 is formed with contact zone 23.In switch region 21,
Gate of the patterned the first metal layer 303 as thin film transistor (TFT).Traditional public electrode wire is using lighttight metal
Material is made, and causes aperture opening ratio lower.It reviews, in this announcement embodiment, using the public electrode wire 25 of electrically conducting transparent material
Aperture opening ratio can effectively be increased.
Then, as shown in Figure 4 B, insulation is formed on substrate 301, the first metal layer 303 and the second transparency conducting layer 302
Layer 304.Then, as shown in Figure 4 C, patterned insulation layer 304 is with exhausted above the first metal layer 303 in contact zone 23 by position
Edge layer 304 removes.Then, as shown in Figure 4 D, channel layer 305 is formed on the insulating layer 304 of corresponding contact zone 23, wherein channel
The material of layer 305 includes amorphous silicon.
Then, as shown in Figure 4 E, the first transparency conducting layer 306 is formed by entire surface on channel layer 305 and insulating layer 304,
And second metal layer 307 is formed by entire surface on the first transparency conducting layer 306.Then, as illustrated in figure 4f, in second metal layer
Setting patterning photoresist layer 308 on 307, and by second metal layer 307 of the position above gate and position in partial pixel area 22
On second metal layer 307 it is exposed.Then, as shown in Figure 4 G, the first transparency conducting layer 306 and second metal layer are patterned
307, to form the first 309 Hes of fluting for exposing channel layer 305 on the first transparency conducting layer 306 and second metal layer 307
Expose the second fluting 310 of insulating layer 304.
Then, as shown at figure 4h, photoresist layer 308 is ashed so that the thickness of photoresist layer 308 to be thinned.After ashing, reserved bit
In the photoresist layer 308 of switch region 21, and photoresist layer 308 of the position in pixel region 22 and contact zone 23 is all removed.That is, exposing
Expose position in the second metal layer 307 of pixel region 22 and contact zone 23.
Then, as shown in fig. 41, second metal layer 307 is patterned, by position the second of pixel region 22 and contact zone 23
Metal layer 307 removes.After removing photoresist layer 308, the second metal layer 307 for being retained in switch region 21 will form thin film transistor (TFT)
Drain electrode 211 and source electrode 212, wherein drain electrode 211 is formed in the side of the first fluting 309 and source electrode 212 is formed in first and opens
The other side of slot 309.Furthermore after patterning second metal layer 307, position is exposed in the first transparency conducting layer of pixel region 22
306.In switch region 21, the first transparency conducting layer 306 is arranged in the lower section of source electrode 212 and directly contacts with source electrode 212, and the
One transparency conducting layer 306 extends to pixel region 22 from switch region 21.In pixel region 22, the first transparency conducting layer 306 is conduct
Pixel electrode 27.That is, the pixel electrode 27 of the source electrode 212 of switch region 21 and pixel region 22 is electrically connected.That is,
In this announcement, covered by the way that the first transparency conducting layer 306 to be produced on to the lower section of second metal layer 307, and using halftoning
Film carries out Patternized technique to the first transparency conducting layer 306 and second metal layer 307.It designs whereby, switch region 21 and pixel region
It does not need to open up the via hole (such as via hole 13 shown in FIG. 1) for connecting thin film transistor (TFT) and pixel electrode 27 between 22, i.e.,
Exportable data-signal, therefore the occupied space of via hole can be saved, and then the aperture opening ratio of pixel unit can be effectively improved.Again
Person, as shown in fig. 41, public electrode wire 25 (second transparency conducting layer 302 be made of) and corresponding pixel of the position in pixel region 22
Electrode 27 (being made of the first transparency conducting layer 306) is overlapped to form storage capacitance 26.Since storage capacitance 26 is using transparent
Material be made, therefore can further improve the aperture opening ratio of pixel unit.
Finally, as shown in fig. 4j, in second metal layer 307, channel layer 305, the first transparency conducting layer 306 and insulating layer
Protective layer 311 is formed on 304, and then completes the production of array substrate 20.In contact zone 23, protective layer 311 be not covered on by
First transparency conducting layer 306, the first metal layer 303 and the second transparency conducting layer 302 are formed by stepped construction, so that letter
Number it can pass through 23 input array substrate 20 of contact zone.Optionally, the material of protective layer 311 includes silicon nitride (SiNx).
In conclusion pixel electricity grade by being produced on the lower section of the source electrode of thin film transistor (TFT) by this announcement embodiment.Whereby
Design, does not need to open up the mistake for connecting thin film transistor (TFT) and pixel electrode between the switch region and pixel region of array substrate
Hole, can outputting data signals, therefore the occupied space of via hole can be saved, and then the opening of pixel unit can be effectively improved
Rate.Furthermore position is overlapped in the public electrode wire of pixel region with corresponding pixel electrode to form storage capacitance.Due to public electrode
Line and pixel electrode are all made of to use transparent material, therefore can further improve the aperture opening ratio of pixel unit.
The above is only the preferred embodiments of this announcement, it is noted that for one of ordinary skill in the art, is not departing from this
Under the premise of disclosing principle, several improvements and modifications can also be made, these improvements and modifications also should be regarded as the protection of this announcement
Range.
Claims (10)
1. a kind of array substrate, which is characterized in that the array substrate definition has switch region and pixel region, and the array base
The switch region of plate includes:
Substrate；
Gate, setting is on the substrate；
Insulating layer is arranged on the gate；
Channel layer is arranged on the insulating layer；
First transparency conducting layer is arranged on the channel layer, wherein first transparency conducting layer shape on the channel layer
At there is fluting；
Drain electrode is arranged on first transparency conducting layer, and is located at the side of the fluting；And
Source electrode is arranged on first transparency conducting layer, and is located at the other side of the fluting, wherein described first transparent leads
Electric layer extends to the pixel region from the switch region so that position the pixel region first transparency conducting layer as picture
Plain electrode.
2. array substrate as claimed in claim 1, which is characterized in that the pixel region of the array substrate includes:
The substrate；
Second transparency conducting layer, setting is on the substrate；
The insulating layer is arranged on second transparency conducting layer；And
First transparency conducting layer, be arranged on the insulating layer, wherein second transparency conducting layer with it is corresponding described
First transparency conducting layer is overlapped to constitute storage capacitance.
3. array substrate as claimed in claim 2, which is characterized in that the switch region of the array substrate also includes described second
Transparency conducting layer is arranged between the substrate and the gate.
4. array substrate as claimed in claim 1, which is characterized in that first transparency conducting layer is directly contacted with the source electrode,
And the pixel electrode is connect with the source electrode.
5. a kind of manufacturing method of array substrate, which is characterized in that the array substrate definition has switch region and pixel region, and
The manufacturing method includes:
Substrate is provided；
The first metal layer is formed on the substrate；
The first metal layer is patterned to form the gate of thin film transistor (TFT) in the switch region；
Insulating layer is formed on the substrate and the first metal layer；
It is formed on the insulating layer channel layer；
The first transparency conducting layer is formed on the channel layer and the insulating layer；
Second metal layer is formed on first transparency conducting layer；And
The second metal layer is patterned to form drain electrode and the source electrode of the thin film transistor (TFT) in the switch region, wherein described
First transparency conducting layer extends to the pixel region from the switch region, so that position transparent is led described the first of the pixel region
Electric layer is as pixel electrode.
6. the manufacturing method of array substrate as claimed in claim 5, which is characterized in that form on first transparency conducting layer
After two metal layers, also include:
The fluting for exposing the channel layer is formed on first transparency conducting layer and the second metal layer, wherein scheming
After second metal layer described in case, the drain electrode is formed in the side of the fluting and the source electrode is formed in described open
The other side of slot.
7. the manufacturing method of array substrate as claimed in claim 5, which is characterized in that before the gate for forming thin film transistor (TFT),
Also include:
The second transparency conducting layer is formed on the substrate；
The first metal layer is formed on second transparency conducting layer:
Second transparency conducting layer and the first metal layer are patterned, to remove position in first gold medal of the pixel region
Belong to layer and reserved bit in second transparency conducting layer of the pixel region, wherein position the pixel region described second thoroughly
Bright conductive layer is with the corresponding first transparency conducting layer overlapping to constitute storage capacitance.
8. the manufacturing method of array substrate as claimed in claim 5, which is characterized in that first transparency conducting layer is whole face landform
At on the channel layer and the insulating layer and the second metal layer is to be formed in first electrically conducting transparent by entire surface
Layer；And
In the step of patterning the second metal layer, the second metal layer of the removal position in the pixel region.
9. the manufacturing method of array substrate as claimed in claim 5, which is characterized in that first transparency conducting layer and the source electrode
It directly contacts, and the pixel electrode is connect with the source electrode.
10. the manufacturing method of array substrate as claimed in claim 5, which is characterized in that after patterning the second metal layer,
Also include: forming protective layer on the second metal layer, the channel layer, first transparency conducting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910259310.8A CN109901336A (en) | 2019-04-02 | 2019-04-02 | Array substrate and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910259310.8A CN109901336A (en) | 2019-04-02 | 2019-04-02 | Array substrate and its manufacturing method |
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| CN109901336A true CN109901336A (en) | 2019-06-18 |
Family
ID=66955185
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102981336A (en) * | 2012-11-29 | 2013-03-20 | 京东方科技集团股份有限公司 | Array substrate, display module and preparation method for array substrate |
| CN103235456A (en) * | 2013-04-23 | 2013-08-07 | 合肥京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN103354218A (en) * | 2013-06-28 | 2013-10-16 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, and display device |
| CN103456742A (en) * | 2013-08-27 | 2013-12-18 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN103984107A (en) * | 2014-05-04 | 2014-08-13 | 京东方科技集团股份有限公司 | Parallax error baffle, manufacturing method of parallax error baffle, display panel and display device |
| CN105137672A (en) * | 2015-08-10 | 2015-12-09 | 深圳市华星光电技术有限公司 | Array substrate and manufacture method thereof |
| CN106873272A (en) * | 2016-12-30 | 2017-06-20 | 深圳市华星光电技术有限公司 | A kind of liquid crystal display panel of multi-domain vertical orientation mode and preparation method thereof |
| CN107065359A (en) * | 2017-05-31 | 2017-08-18 | 深圳市华星光电技术有限公司 | Display panel |
-
2019
- 2019-04-02 CN CN201910259310.8A patent/CN109901336A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102981336A (en) * | 2012-11-29 | 2013-03-20 | 京东方科技集团股份有限公司 | Array substrate, display module and preparation method for array substrate |
| CN103235456A (en) * | 2013-04-23 | 2013-08-07 | 合肥京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN103354218A (en) * | 2013-06-28 | 2013-10-16 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, and display device |
| CN103456742A (en) * | 2013-08-27 | 2013-12-18 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN103984107A (en) * | 2014-05-04 | 2014-08-13 | 京东方科技集团股份有限公司 | Parallax error baffle, manufacturing method of parallax error baffle, display panel and display device |
| CN105137672A (en) * | 2015-08-10 | 2015-12-09 | 深圳市华星光电技术有限公司 | Array substrate and manufacture method thereof |
| CN106873272A (en) * | 2016-12-30 | 2017-06-20 | 深圳市华星光电技术有限公司 | A kind of liquid crystal display panel of multi-domain vertical orientation mode and preparation method thereof |
| CN107065359A (en) * | 2017-05-31 | 2017-08-18 | 深圳市华星光电技术有限公司 | Display panel |
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| CB02 | Change of applicant information |
Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190618 |