CN109885508A - High-speed peripheral component interconnection bus system and its data transmission method, device - Google Patents
High-speed peripheral component interconnection bus system and its data transmission method, device Download PDFInfo
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Abstract
The invention discloses a kind of high-speed peripheral component interconnection bus system and its data transmission methods, device, belong to field of communication technology.The described method includes: main equipment is after os starting, obtain the value of the physical parameter of the high-speed peripheral component interconnection PCI-E bus stored in the operating system, the physical parameter of the PCI-E bus includes that width is completed in PCI-E transport layer maximum load size, PCI-E transport layer maximum read request size and PCI-E read operation；Configure the physical parameter of each PCI-E bus value be obtain corresponding PCI-E bus physical parameter value；According to the physical parameter of each PCI-E bus postponed, by PCI-E bus to from equipment transmission data and control it is described from equipment by the PCI-E bus to the master transmissions data.
Description
Technical field
The present invention relates to field of communication technology, in particular to a kind of high-speed peripheral component interconnection bus system and its number
According to transmission method, device.
Background technique
PCI-E (Peripheral Componet Interconnected-Express, high-speed peripheral component interconnection mark
It is quasi-) bus is high-speed serial bus of new generation that Intel Company proposes first.PCI-E bus is commonly used for the IO of processor
(Input/Output, input/output) transfer bus, for realizing the peripheral expansion of interconnection and system between system.System
Between interconnection such as CPU (Central Processing Unit, central processing unit) between interconnection, the peripheral hardware of system expands
Open up the data transmission interface of such as network interface card, video card.
PCI-E bus transmission system (referred to as PCI-E bus system) include the main equipment that is connected by PCI-E bus and
From equipment.Main equipment is the entity for causing PCI-E transmission practice, has processing capacity, main equipment is equivalent to a bus master
Device can control bus；The entity of transmission practice is in response to from equipment.With the application of PCI-E bus transmission system
It is more and more extensive, most application requirements in the case where PCI-E bus limited transmission line width, message transmission rate it is more big more
It is good.The method of the general message transmission rate for promoting PCI-E bus transmission system is to increase transmission line width, passes through physical connection
Increased method, such as increase the quantity of PCI-E bus, so as to improve transmission rate.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems: physical connection increases
Mode not only increase system cost, and it is more demanding to power consumption and small product size etc..
Summary of the invention
The embodiment of the invention provides a kind of high-speed peripheral component interconnection bus system and its data transmission methods, dress
It sets, the message transmission rate of high-speed peripheral component interconnection bus system can be promoted under the premise of not increasing cost, and
Requirement to power consumption and small product size is lower.The technical solution is as follows:
In a first aspect, providing a kind of data transmission method of high-speed peripheral component interconnection bus system, the side
Method includes:
Main equipment obtains the high-speed peripheral component interconnection stored in the operating system after os starting
The physical parameter of the value of the physical parameter of PCI-E bus, the PCI-E bus includes, PCI-E transport layer maximum load size,
Width is completed in PCI-E transport layer maximum read request size and PCI-E read operation；
Configure the physical parameter of each PCI-E bus value be obtain corresponding PCI-E bus physical parameter value；
According to the physical parameter with each PCI-E bus postponed, number is transmitted to from equipment by PCI-E bus
According to and control it is described from equipment by the PCI-E bus to the master transmissions data.
Optionally, the value of the PCI-E transport layer maximum load size of acquisition is, the main equipment and described from equipment
The maximum maximum load size of the PCI-E transport layer supported；
The value of the PCI-E transport layer maximum read request size obtained is the PCI-E transport layer that the main equipment is supported
Maximum maximum read request size, alternatively, the maximum data packet that the practical business that the PCI-E bus transmission system provides is supported
It is long；
The value that width is completed in the PCI-E read operation obtained is that the PCI-E maximum read operation that the main equipment is supported is complete
At width.
Optionally, the maximum data packet supported when the practical business that the PCI-E bus transmission system provides it is long with it is described
When each PCI-E transport layer maximum read request that main equipment is supported is of different sizes, the PCI-E transport layer of acquisition is maximum
The value of read request size is the maximum maximum read request size of PCI-E transport layer that the main equipment is supported；
When the maximum data packet length that the practical business that the PCI-E bus transmission system provides is supported belongs to the main equipment
When the PCI-E transport layer maximum read request size of support, the value of the PCI-E transport layer maximum read request size of acquisition is institute
The maximum data packet for stating the practical business support of PCI-E bus transmission system offer is long.
Optionally, described according to the physical parameter of each PCI-E bus postponed, by PCI-E bus to from
Equipment transmission data and control it is described from equipment by the PCI-E bus to the master transmissions data, comprising:
The read request that receiving process is sent, under the instruction of the read request, according to total with each PCI-E postponed
The physical parameter of line, control it is described from equipment by the PCI-E bus to the master transmissions data；The process operation
In on the main equipment；
The write request that the process is sent is received, under the instruction of the write request, according to each described with what is postponed
The physical parameter of PCI-E bus, by the PCI-E bus to described from equipment transmission data.
Optionally, described in the control from equipment by the PCI-E bus to after the master transmissions data,
The method also includes:
By the data storage transmitted from equipment to PCI-E memory, and the data transmitted from equipment are recorded in institute
State the storage address of PCI-E memory；
It is determined as the storage address for the user's space that the data transmitted from equipment are distributed；
Based on described in record from equipment transmit data the PCI-E memory storage address, using directly addressing
The data that mode is transmitted from equipment described in the PCI-E memory lookup；
The data transmitted described in finding from equipment are from the PCI-E memory copying to the user's space.
Optionally, the method also includes:
It is sent to the process and reads feedback command, the feedback command of reading includes for the data distribution transmitted from equipment
User's space storage address, it is described to read feedback command and be used to indicate the process to divide from for the data transmitted from equipment
The storage address for the user's space matched obtains the data transmitted from equipment.
Second aspect provides a kind of data transmission device of high-speed peripheral component interconnection bus system, the dress
It sets and includes:
Module is obtained, for it is mutual to obtain the high-speed peripheral component stored in the operating system after os starting
The even value of the physical parameter of standard PCI-E bus, the physical parameter of the PCI-E bus includes PCI-E transport layer maximum load
Width is completed in size, PCI-E transport layer maximum read request size and PCI-E read operation；
Configuration module, the value of the physical parameter for configuring each PCI-E bus are the object of the corresponding PCI-E bus obtained
Manage the value of parameter；
Transmission module, for according to the physical parameter of each PCI-E bus postponed, by PCI-E bus to
It is described from equipment transmission data and control it is described from equipment by the PCI-E bus to the master transmissions data.
Optionally, the value of the PCI-E transport layer maximum load size of acquisition is, the main equipment and described from equipment
The maximum maximum load size of the PCI-E transport layer supported；
The value of the PCI-E transport layer maximum read request size obtained is the PCI-E transport layer that the main equipment is supported
Maximum maximum read request size, alternatively, the maximum data packet that the practical business that the PCI-E bus transmission system provides is supported
It is long；
The value that width is completed in the PCI-E read operation obtained is that the PCI-E maximum read operation that the main equipment is supported is complete
At width.
Optionally, the maximum data packet supported when the practical business that the PCI-E bus transmission system provides it is long with it is described
When each PCI-E transport layer maximum read request that main equipment is supported is of different sizes, the PCI-E transport layer of acquisition is maximum
The value of read request size is the maximum maximum read request size of PCI-E transport layer that the main equipment is supported；
When the maximum data packet length that the practical business that the PCI-E bus transmission system provides is supported belongs to the main equipment
When the PCI-E transport layer maximum read request size of support, the value of the PCI-E transport layer maximum read request size of acquisition is institute
The maximum data packet for stating the practical business support of PCI-E bus transmission system offer is long.
The third aspect provides a kind of high-speed peripheral component interconnection bus system, the system comprises:
Main equipment,
The slave equipment being connect by PCI-E bus with the main equipment,
The main equipment is used for, and after os starting, obtains the high-speed peripheral component stored in the operating system
The physical parameter of the value of the physical parameter of interconnection standards PCI-E bus, the PCI-E bus includes that PCI-E transport layer maximum carries
Width is completed in lotus size, PCI-E transport layer maximum read request size and PCI-E read operation；Configure each PCI-E bus
The value of physical parameter is the value of the physical parameter of the corresponding PCI-E bus obtained；According to each PCI-E bus postponed
Physical parameter, the PCI-E bus is passed through from equipment to from equipment transmission data and control are described by PCI-E bus
To the master transmissions data.
Technical solution provided in an embodiment of the present invention has the benefit that
Through main equipment after os starting, the high-speed peripheral component interconnection stored in driver is obtained
The physical parameter of the value of the physical parameter of PCI-E bus, the PCI-E bus includes, PCI-E transport layer maximum load size,
Width is completed in PCI-E transport layer maximum read request size and PCI-E read operation；The value of the physical parameter of PCI-E bus it is big
It is small related to the message transmission rate of PCI-E bus；The value for configuring the physical parameter of each PCI-E bus is the corresponding of acquisition
The value of the physical parameter of PCI-E bus；According to the physical parameter with each PCI-E bus postponed, pass through PCI-E bus
To from equipment transmission data and control it is described from equipment by the PCI-E bus to the master transmissions data；Configuration
The value of the physical parameter of each PCI-E bus afterwards can be the value for being able to ascend the message transmission rate of PCI-E bus, that
, when PCI-E bus carries out data transmission according to the value of the physical parameter with each PCI-E bus postponed, it is able to ascend
The message transmission rate of PCI-E bus, to improve the message transmission rate of PCI-E bus system, this method only relates to parameter
Configuration does not need the quantity for increasing PCI-E bus, cost can be saved, also, do not generate the increase of small product size, to power consumption
Equal requirements are also relatively low.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of data transmission device of high-speed peripheral component interconnection bus system provided in an embodiment of the present invention
Structural schematic diagram；
Fig. 2 is a kind of data transmission device of high-speed peripheral component interconnection bus system provided in an embodiment of the present invention
Structural schematic diagram；
Fig. 3 is a kind of structural schematic diagram of high-speed peripheral component interconnection bus system provided in an embodiment of the present invention；
Fig. 4 is a kind of structural block diagram of high-speed peripheral component interconnection bus system provided in an embodiment of the present invention；
Fig. 5 is a kind of data transmission method of high-speed peripheral component interconnection bus system provided in an embodiment of the present invention
Flow chart；
Fig. 6 is a kind of data transmission method of high-speed peripheral component interconnection bus system provided in an embodiment of the present invention
Flow chart；
Fig. 7 and Fig. 8 is the schematic diagram of transmission line pulse generator packet provided in an embodiment of the present invention respectively.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 shows a kind of data transmission of high-speed peripheral component interconnection bus system provided in an embodiment of the present invention
Device 100, referring to Fig. 1, which includes: to obtain module 11, configuration module 12 and transmission module 13.
Module 11 is obtained, for after os starting, obtaining the physics ginseng of the PCI-E bus stored in operating system
The physical parameter of several values, the PCI-E bus includes PCI-E transport layer MPS (Maximum Payload Size, maximum load
Size), PCI-E transport layer MRRS (Maximum Read Request Size, maximum read request size) and PCI-E RCB
(width is completed in Read Completion Boundary, read operation).
Configuration module 12, the value of the physical parameter for configuring each PCI-E bus are the corresponding of the acquisition acquisition of module 11
The value of the physical parameter of PCI-E bus.
Transmission module 13 passes through PCI- for matching the physical parameter of each PCI-E bus postponed according to configuration module 12
E bus passes through PCI-E bus to master transmissions data to from equipment transmission data and control from equipment.
Illustratively, device configuration is in the main equipment of PCI-E bus transmission system.PCI-E bus transmission system packet
Include the main equipment connected by PCI-E bus and from equipment.
Illustratively, PCI-E transport layer MPS is main equipment and the maximum MPS of PCI-E transport layer supported from equipment；
PCI-E transport layer MRRS is the maximum MRRS of PCI-E transport layer that main equipment is supported, alternatively, PCI-E transport layer MRRS is,
The maximum data packet that the practical business that PCI-E bus transmission system provides is supported is long；PCI-E RCB is, what main equipment was supported
PCI-E maximum RCB.
Illustratively, the maximum data packet length and main equipment of the practical business support provided when PCI-E bus transmission system
When each PCI-E transport layer MRRS difference supported, the PCI-E transport layer MRRS of acquisition is the PCI-E transmission that main equipment is supported
The maximum MRRS of layer；When the maximum data packet length that the practical business that PCI-E bus transmission system provides is supported belongs to main equipment branch
When the PCI-E transport layer MRRS held, the PCI-E transport layer MRRS of acquisition is the practical business that PCI-E bus transmission system provides
The maximum data packet of support is long.
Illustratively, transmission module 13 is used for: the read request that receiving process is sent, under the instruction of read request, according to matching
The physical parameter of each PCI-E bus postponed, control pass through PCI-E bus to master transmissions data from equipment；Process fortune
Row is on main equipment；And the write request that receiving process is sent, under the instruction of write request, according to each PCI-E postponed
The physical parameter of bus, by PCI-E bus to from equipment transmission data.
Referring to fig. 2, illustratively, which further includes memory copying module 14.
Memory copying module 14 is used for, by the data storage transmitted from equipment to PCI-E memory, and record it is described from
Storage address of the data of equipment transmission in the PCI-E memory；It is determined as the user that the data transmitted from equipment are distributed
The storage address in space；Based on described in record from equipment transmit data the PCI-E memory storage address, using straight
Connect the data that addressing system is transmitted from equipment described in the PCI-E memory lookup；It is transmitted described in finding from equipment
Data are from the PCI-E memory copying to the user's space.
Referring to fig. 2, illustratively, which further includes sending module 15.
Sending module 15 is used for, and is sent to process and is read feedback command, and reading feedback command includes the data to transmit from equipment
The storage address of the user's space of distribution reads feedback command and is used to indicate process from the user distributed for the data transmitted from equipment
The storage address in space obtains the data transmitted from equipment.
The embodiment of the present invention after os starting, obtains the high-speed peripheral group stored in driver by main equipment
The value of the physical parameter of part interconnection standards PCI-E bus, the physical parameter of the PCI-E bus include that PCI-E transport layer maximum carries
Width is completed in lotus size, PCI-E transport layer maximum read request size and PCI-E read operation；The physical parameter of PCI-E bus
Value size it is related to the message transmission rate of PCI-E bus；The value of the physical parameter of each PCI-E bus is configured to obtain
Corresponding PCI-E bus physical parameter value；It is total by PCI-E according to the physical parameter with each PCI-E bus postponed
Line passes through PCI-E bus to master transmissions data to from equipment transmission data and control from equipment；It is each with what is postponed
The value of the physical parameter of PCI-E bus can be the value for being able to ascend the message transmission rate of PCI-E bus, then, PCI-E is total
When line carries out data transmission according to the value of the physical parameter with each PCI-E bus postponed, it is able to ascend the number of PCI-E bus
According to transmission rate, to improve the message transmission rate of PCI-E bus system, this method only relates to parameter configuration, does not need to increase
Add the quantity of PCI-E bus, cost can be saved, also, do not generate the increase of small product size, the requirements such as power consumption are also compared
It is low.For the application scenarios that some pairs of power consumptions and volume etc. require, such as embedded scene, it can be realized and be passed using this method
The promotion of defeated rate.
Fig. 3 shows a kind of high-speed peripheral component interconnection bus system provided in an embodiment of the present invention, referring to Fig. 3,
The system includes:
Main equipment 21 and the slave equipment 23 being connect by PCI-E bus 22 with main equipment.
Main equipment 21 is used for, and after os starting, obtains the physical parameter of the PCI-E bus stored in operating system
Value, the physical parameter of the PCI-E bus includes PCI-E transport layer MPS, PCI-E transport layer MRRS and PCI-E RCB；
Configure the physical parameter of each PCI-E bus value be obtain corresponding PCI-E bus physical parameter value；It is postponed according to matching
Each PCI-E bus physical parameter, data and control are transmitted from equipment 23 to from equipment 23 by PCI-E bus 22
Data are transmitted to main equipment 21 by PCI-E bus 22.
Illustratively, the main equipment 21 can be Fig. 1 or Fig. 2 shows device 100.
Fig. 4 is the structural block diagram of provided in an embodiment of the present invention one exemplary PCI-E bus transmission system.Referring to fig. 4,
The main equipment 21 of PCI-E bus transmission system can be CPU, and the slave equipment 23 of PCI-E bus transmission system can be FPGA
(Field-Programmable Gate Array, field programmable gate array).PCI-E bus transmission system further include with
The memory DDR 24 of CPU connection.Illustratively, CPU can be Godson 2H series processors, and FPGA can be Xilinx V5 system
Arrange FPGA.The PCI-E interface of CPU and the PCI-E interface of FPGA connect, and carry out data by PCI-E bus between CPU and FPGA
Transmission.Highway width × 1 PCI-E is standardized using PCI-E 2.0.The operating system of CPU can be kylin Linux operation system
System.
It should be noted that the system does not limit the type and connection type of main equipment 21, the main equipment 21 is also
It can be the various processors such as X86, PowerPC, ARM.
The embodiment of the present invention after os starting, obtains the high-speed peripheral group stored in driver by main equipment
The value of the physical parameter of part interconnection standards PCI-E bus, the physical parameter of the PCI-E bus include that PCI-E transport layer maximum carries
Width is completed in lotus size, PCI-E transport layer maximum read request size and PCI-E read operation；The physical parameter of PCI-E bus
Value size it is related to the message transmission rate of PCI-E bus；The value of the physical parameter of each PCI-E bus is configured to obtain
Corresponding PCI-E bus physical parameter value；It is total by PCI-E according to the physical parameter with each PCI-E bus postponed
Line passes through PCI-E bus to master transmissions data to from equipment transmission data and control from equipment；It is each with what is postponed
The value of the physical parameter of PCI-E bus can be the value for being able to ascend the message transmission rate of PCI-E bus, then, PCI-E is total
When line carries out data transmission according to the value of the physical parameter with each PCI-E bus postponed, it is able to ascend the number of PCI-E bus
According to transmission rate, to improve the message transmission rate of PCI-E bus system, this method only relates to parameter configuration, does not need to increase
Add the quantity of PCI-E bus, cost can be saved, also, do not generate the increase of small product size, the requirements such as power consumption are also compared
It is low.For the application scenarios that some pairs of power consumptions and volume etc. require, such as embedded scene, it can be realized and be passed using this method
The promotion of defeated rate.
In the embodiment being described above, the place of the not detailed description of the function of each module and each equipment sees below and retouches
The embodiment of the method stated.
Fig. 5 shows a kind of data transmission of high-speed peripheral component interconnection bus system provided in an embodiment of the present invention
Method, this method can be executed by main equipment in the system shown in Fig. 3 or Fig. 4.Referring to Fig. 5, this method process includes following step
Suddenly.
Step 101, after os starting, obtain the value of the physical parameter of PCI-E bus stored in operating system.
Wherein, the physical parameter of the PCI-E bus includes, PCI-E transport layer MPS, PCI-E transport layer MRRS and
PCI-E RCB。
Step 102, the value of the physical parameter of each PCI-E bus of configuration are the physics ginseng of the corresponding PCI-E bus obtained
Several values.
Step 103, according to the physical parameter of each PCI-E bus postponed, transmitted by PCI-E bus to from equipment
Data and control are from equipment by PCI-E bus to master transmissions data.
The embodiment of the present invention after os starting, obtains the high-speed peripheral group stored in driver by main equipment
The value of the physical parameter of part interconnection standards PCI-E bus, the physical parameter of the PCI-E bus include that PCI-E transport layer maximum carries
Width is completed in lotus size, PCI-E transport layer maximum read request size and PCI-E read operation；The physical parameter of PCI-E bus
Value size it is related to the message transmission rate of PCI-E bus；The value of the physical parameter of each PCI-E bus is configured to obtain
Corresponding PCI-E bus physical parameter value；It is total by PCI-E according to the physical parameter with each PCI-E bus postponed
Line passes through PCI-E bus to master transmissions data to from equipment transmission data and control from equipment；It is each with what is postponed
The value of the physical parameter of PCI-E bus can be the value for being able to ascend the message transmission rate of PCI-E bus, then, PCI-E is total
When line carries out data transmission according to the value of the physical parameter with each PCI-E bus postponed, it is able to ascend the number of PCI-E bus
According to transmission rate, to improve the message transmission rate of PCI-E bus system, this method only relates to parameter configuration, does not need to increase
Add the quantity of PCI-E bus, cost can be saved, also, do not generate the increase of small product size, the requirements such as power consumption are also compared
It is low.For the application scenarios that some pairs of power consumptions and volume etc. require, such as embedded scene, it can be realized and be passed using this method
The promotion of defeated rate.
Fig. 6 shows a kind of data transmission of high-speed peripheral component interconnection bus system provided in an embodiment of the present invention
Method, this method can be executed by main equipment in the system shown in Fig. 3 or Fig. 4.Referring to Fig. 6, this method process includes following step
Suddenly.
Step 201, after os starting, obtain the value of the physical parameter of PCI-E bus stored in operating system.
Wherein, which is the operating system of main equipment, such as aforementioned kylin (SuSE) Linux OS.
Wherein, the physical parameter of the PCI-E bus includes, PCI-E transport layer MPS, PCI-E transport layer MRRS and
PCI-E RCB.These physical parameters are surrounded by with TLP (Transmission Line Pulse, transmission line pulse generator)
It closes.
Wherein, PCI-E bus transmission system carries out data transmitting by TLP packet.Fig. 7 is provided in 2.0 agreement of PCI-E
TLP packet schematic diagram.Referring to Fig. 7, TLP packet includes Start (beginning) field, Sequence (sequence) field, Header
(head) field, Payload field, ECRC field, LCRC field and End (end) field.Payload field is for carrying write-in
Valid data.Fig. 8 is the schematic diagram of TLP packet specified in 3.0 agreement of PCI-E.Referring to Fig. 8, TLP packet includes Start word
Section, Sequence field, Header field, Payload field, ECRC field and LCRC fields.Main equipment Xiang Congshe
It is standby to write data (main equipment transmits TLP to from equipment) and main equipment and read data (from equipment to master transmissions from from equipment
TLP during), the field length of the TLP packet of transmission can be different.
The meaning of PCI-E transport layer MPS is, in main equipment to when writing data from equipment, the Payload of the TLP packet of transmission
The magnitude of load of (payload) field carrying.MPS determines that a same bag data needs to be sent by how many TLP, MPS
Bigger, required TLP is fewer.
The meaning of PCI-E transport layer MRRS is, when main equipment is from from equipment reading data, the Payload of the TLP packet of transmission
The magnitude of load of field carrying.
The meaning of PCI-E RCB is, when main equipment is from from equipment reading data, the number for the data packet that each TLP packet includes
Amount.The size of RCB will affect the efficiency of transmission for running through TLP message.The data sent from equipment to main equipment are read
Request can be transmitted by multiple run through.Valid data can be split into 64byte or 128byte to be transmitted.
Wherein, the value of the PCI-E transport layer MPS of acquisition is main equipment and the maximum PCI-E supported from equipment transmission
Layer MPS.Illustratively, it is assumed that the PCI-E transport layer MPS that main equipment can be supported is 128byte, 256byte, 512byte；From
The PCI-E transport layer MPS that equipment can be supported is 128byte, 256byte；So, the value of the PCI-E transport layer MPS of acquisition is
256。
Wherein, the value of the PCI-E transport layer MRRS of acquisition is the maximum PCI-E transport layer MRRS that main equipment is supported, or
Person, the maximum data packet that the practical business that PCI-E bus transmission system provides is supported are long.
When the maximum data packet that the practical business that PCI-E bus transmission system provides is supported is long support with main equipment it is each
When PCI-E transport layer MRRS difference, the PCI-E transport layer MRRS of acquisition is that the PCI-E transport layer that main equipment is supported is maximum
MRRS.Illustratively, it is assumed that the PCI-E transport layer MRRS that main equipment can be supported is 256byte, 512byte, 1024byte；
The a length of 700byte of maximum data packet that the practical business that PCI-E bus transmission system provides is supported；So, the PCI-E of acquisition is passed
The value of defeated layer MRRS is 1024.
Belong to main equipment support when the maximum data packet that the practical business that PCI-E bus transmission system provides is supported is long
When PCI-E transport layer MRRS, the PCI-E transport layer MRRS of acquisition is that the practical business that PCI-E bus transmission system provides is supported
Maximum data packet it is long.Illustratively, it is assumed that the PCI-E transport layer MRRS that main equipment can be supported be 256byte, 512byte,
1024byte；The a length of 512byte of maximum data packet that the practical business that PCI-E bus transmission system provides is supported；So, it obtains
PCI-E transport layer MRRS value be 512.
Wherein, the PCI-E RCB value of acquisition is the maximum PCI-E RCB that main equipment is supported.Illustratively, it is assumed that master sets
The standby PCI-E RCB that can be supported is 64byte, 128byte；So, the value of the PCI-E RCB of acquisition is 128.
Step 202, the value of the physical parameter of each PCI-E bus of configuration are the physics ginseng of the corresponding PCI-E bus obtained
Several values.
Step 202 may include: the value of the physical parameter of each PCI-E bus based on acquisition, to storing in register
Each corresponding PCI-E bus physical parameter carry out assignment.Register is the physical parameter dedicated for storing PCI-E bus
Value register.Before configuring the value of physical parameter of each PCI-E bus, each PCI-E stored in register is total
The value of the physical parameter of line is default value.
The value of the physical parameter of each PCI-E bus based on acquisition can be evaluated whether the physics ginseng of the PCI-E bus of configuration
The influence of the transmission rate of several pairs of PCI-E bus transmission systems is so as to assess the physical parameter of the PCI-E bus of configuration
It is no to be able to ascend transmission rate.
Firstly, calculating PCI-E bus theoretical transmission rate.The single line basis speed of version can be used based on PCI-E bus
It is total to calculate PCI-E by following formula (1) for rate (rate_original) and the physical bus width (lane Width) used
Line theoretical transmission rate.
In formula (1), 2 indicate transmitted in both directions, and 10bits/byte indicates that the payload of transmission 1byte needs 10bits
It is transmitted in the space of size.
Secondly, determining the physical parameter of each PCI-E bus of configuration respectively to PCI-E bus transmission system transmission rate
Influence.
In formula (2)-(4), Overhead indicates the sum of the size of TLP message other fields in addition to Payload field,
MPS is the value of the PCI-E transport layer MPS obtained, and MRRS is the value of the PCI-E transport layer MRRS obtained, and RCB is the PCI- obtained
E RCB。
Wherein, influence of the MPS to PCI-E bus transmission system transmission rate is influence _ MPS=Theoretical Rate * transmission effect
Rate _ MPS*100%.
Influence of the MRRS to PCI-E bus transmission system transmission rate be, influence _ MRRS=Theoretical Rate * efficiency of transmission _
MRRS*100%.
Influence of the RCB to PCI-E bus transmission system transmission rate be, influence _ RCB=Theoretical Rate * efficiency of transmission _
RCB*100%.
Illustratively, the method that step 201- step 202 is realized can be realized by operating system load driver program.It should
Driver can be operating system nucleus PCI-E bus driver, and operating system is stored in the form of dynamic base
In file system.The value of the physical parameter of PCI-E bus is stored in the driver.Operating system after actuation, will be run
Driver loading function loads PCI-E bus driver, realizes the configuration of PCI-E bus physical parameter, realizes and is promoted
PCI-E Transmission system effective transmission speed function.
After the completion of driver load, it can check that PCI-E from equipment, runs PCI-E Transmission system rate by order
Test application, can test speed, compared with theoretical value.
Wherein, the value of the physical parameter of each PCI-E bus based on configuration, it can be estimated that with the PCI-E bus postponed
Bandwidth, bandwidth means that more greatly transmission rate is bigger.Illustratively, in the PCI-E bus transmission system shown in Fig. 4, one
Aspect, when write operation (main equipment to from equipment transmission data), it is assumed that 200 write operations, transmission link transmission rate are
2.5Gb/s, 1byte transmit time-consuming 4ns, 32 bit address situations, DLLP ACK (Data Link Layer Packets
Acknowledgement, data link layer message response) transmission time-consuming are as follows: 8bytes*4ns/bytes=32ns: when MPS is
When 128bytes, a TLP transmission is time-consuming are as follows: ([128+20] × 4) ns=592ns always transmits data=200 × 128bytes
=25600bytes, overall transmission time=(200 × 592ns)+(40 × 32ns)+(50 × 32ns)=121280ns, then total band
Width=25600bytes/121280ns=0.211GB/s=1.688Gbps.When MPS is 64bytes, a TLP transmission consumption
When ([64+20] × 4)=336ns, always transmit data=200 × 64bytes=12800bytes, overall transmission time=(200 ×
336ns)+(40 × 32ns)+(50 × 32ns)=70080ns, total bandwidth 12800bytes/70080ns=0.183GB/s=
1.46Gbps.As it can be seen that MPS is bigger, bandwidth is bigger, and corresponding transmission rate is faster.
On the other hand, when read operation (from equipment to master transmissions data), it is assumed that transmission link transmission rate is
2.5Gb/s, 1byte transmit time-consuming 4ns, and 32 bit address situations, one time TLP read request message transmissions are time-consuming are as follows: ([20] × 4) ns
=80ns: when RCB is 64bytes, it is time-consuming that a TLP completes message transmissions are as follows: ([64+20] × 4) ns=336ns,
DLLP ACK transmission is time-consuming are as follows: 8bytes*4ns/bytes=32ns, system finish receiving generation and complete message time-consuming
300ns.Assuming that read 4096bytes data, if MRRS be 256bytes, overall transmission time=(16 × 80ns)+(16 ×
300ns)+(64 × 336ns)+(16 × 32ns)=28096ns, total bandwidth=4096bytes/28096ns=0.145GB/s=
1.16Gbps.If MRRS be 128bytes, overall transmission time=(32 × 80ns)+(32 × 300ns)+(64 × 336ns)+
(32 × 32ns)=34688ns, total bandwidth 4096bytes/34688ns=0.118GB/s=0.944Gbps.As it can be seen that RCB
When constant, MRRS is bigger, and bandwidth is bigger, and corresponding transmission rate is bigger.
Step 203, according to the physical parameter of each PCI-E bus postponed, transmitted by PCI-E bus to from equipment
Data.
Step 203 may include:
The write request that the first step, main equipment receiving process are sent.Write request is write operation requests, at this moment, main equipment to
From equipment transmission data.
Second step, main equipment, according to the physical parameter with each PCI-E bus postponed, lead under the instruction of write request
PCI-E bus is crossed to from equipment transmission data.
Wherein, main equipment, according to the physical parameter with each PCI-E bus postponed, generates under the instruction of write request
TLP packet, and TLP packet is transferred to from equipment.In the TLP packet that main equipment generates, the payload size of Payload field carrying
For the value of the PCI-E transport layer MPS of configuration.When the value of MPS is bigger, the payload size that Payload field carries is bigger, and one
The quantity for the TLP packet that bag data is divided into is fewer, and TLP can have been passed by taking less time, and improves efficiency of transmission.
Step 204, according to the physical parameter of each PCI-E bus postponed, control from equipment by PCI-E bus to
Master transmissions data.
Step 204 may include:
The read request that the first step, main equipment receiving process are sent.Read request is read operation request, at this moment, from equipment to
Master transmissions data.
Wherein, process is run on main equipment.
Second step, main equipment are under the instruction of read request, according to the physical parameter with each PCI-E bus postponed, control
System passes through PCI-E bus to master transmissions data from equipment.
Wherein, main equipment is controlled from equipment under the instruction of read request according to the physics with each PCI-E bus postponed
Parameter generates TLP packet, and TLP packet is transferred to main equipment.From the TLP packet that equipment generates, what Payload field carried has
Effect magnitude of load is the value of the PCI-E transport layer MRRS of configuration.When effective load that the value of MRRS is bigger, and Payload field carries
Lotus size is bigger, and the quantity for the TLP packet that a bag data is divided into is fewer, and TLP can have been passed by taking less time, and improves biography
Defeated efficiency.Also, the quantity for the data packet for including in TLP packet is identical as the value of the RCB of configuration.
Step 205 moves the data transmitted from equipment to user's space from kernel spacing.
Wherein, user's space refers to that main equipment is the memory storage space of process distribution.In step 204, pass through from equipment
PCI-E bus is stored in kernel spacing to the data of master transmissions.Since process can only call the data of user's space,
Therefore, it is necessary to move data to user's space from kernel spacing.
Step 205 may include:
The first step, main equipment store the data transmitted from equipment to PCI-E memory, and record the data transmitted from equipment
In the storage address of PCI-E memory.
Wherein, memory space (also referred to as kernel spacing) of the PCI-E bus transmission system on memory is saved as in PCI-E.
PCI-E memory can be distributed by main equipment.Illustratively, the data transmitted from equipment are straight in the storage address of PCI-E memory
Connect addressable address.
The storage address for the user's space that second step, the data for being determined as transmitting from equipment are distributed.
Wherein, the user's space for the data distribution transmitted from equipment can be, and main equipment is the interior of each process distribution
Deposit memory space.
Third step, based on record slave equipment transmission data PCI-E memory storage address, using directly addressing side
The data that formula is transmitted in PCI-E memory lookup from equipment.
Since the data transmitted from equipment are directly addressing address in the storage address of PCI-E memory, using direct
Addressing system searches the data transmitted from equipment and does not need secondary calculating storage address, Neng Gouti compared to indirect addressing mode
Rise the efficiency of data transmission.
4th step, the data for transmitting the slave equipment found are from PCI-E memory copying to user's space.
When realizing, SSE (Streaming Single Instruction Multiple Data can be used
Extensions, abbreviation instruction set) assembly instruction realization data moving from kernel spacing to user's space.
Step 206 sends to process and reads feedback command.
It is moved from kernel spacing to after user's space by the data transmitted from equipment, main equipment is to carrying out transmission feedback
Instruction.Wherein, reading feedback command includes for the storage address of the user's space for the data distribution transmitted from equipment.Read feedback command
It is used to indicate process and obtains the data transmitted from equipment from the storage address of the user's space distributed for the data transmitted from equipment.
Existing PCI-E bus transmission system is the data moved the data transmitted from equipment from user's space to process
Buffer area, process obtain the data transmitted from equipment from data buffer zone.In the present embodiment, by the data transmitted from equipment with
The storage address in family space is sent to process, and process directly can obtain the data transmitted from equipment from user's space, thus not
Need the data transmitted from equipment moving data buffer zone to process from user's space, the process that saves obtain data when
Between, improve the efficiency of transmission of PCI-E bus transmission system.
When realizing, memory field can be mapped directly to user's space using similar iommap order by feedback command.Step
The entire read procedure of rapid 204- step 206 is realized using PCI-E bus function reading.
Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment can pass through hardware
It completes, relevant hardware can also be instructed to complete by program, the program can store in a kind of computer-readable
In storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of data transmission method of high-speed peripheral component interconnection bus system, which is characterized in that the described method includes:
Main equipment obtains the high-speed peripheral component interconnection PCI-E stored in the operating system after os starting
The physical parameter of the value of the physical parameter of bus, the PCI-E bus includes PCI-E transport layer maximum load size, PCI-E
Width is completed in transport layer maximum read request size and PCI-E read operation；
Configure the physical parameter of each PCI-E bus value be obtain corresponding PCI-E bus physical parameter value；
According to the physical parameter of each PCI-E bus postponed, by PCI-E bus to from equipment transmission data, with
And control it is described from equipment by the PCI-E bus to the master transmissions data.
2. the method according to claim 1, wherein
The value of the PCI-E transport layer maximum load size obtained is, the main equipment and described supports from equipment
The maximum maximum load size of PCI-E transport layer；
The value of the PCI-E transport layer maximum read request size obtained is that the PCI-E transport layer that the main equipment is supported is maximum
Maximum read request size, alternatively, the PCI-E bus transmission system provide practical business support maximum data packet it is long；
The value that width is completed in the PCI-E read operation obtained is that the PCI-E maximum read operation that the main equipment is supported is completed wide
Degree.
3. according to the method described in claim 2, it is characterized in that,
It is supported when the maximum data packet length that the practical business that the PCI-E bus transmission system provides is supported with the main equipment
When each PCI-E transport layer maximum read request is of different sizes, the PCI-E transport layer maximum read request size of acquisition
Value is the maximum maximum read request size of PCI-E transport layer that the main equipment is supported；
Belong to the main equipment support when the maximum data packet that the practical business that the PCI-E bus transmission system provides is supported is long
PCI-E transport layer maximum read request size when, the value of the PCI-E transport layer maximum read request size of acquisition is described
The maximum data packet that the practical business that PCI-E bus transmission system provides is supported is long.
4. the method according to claim 1, wherein described according to each PCI-E bus postponed
Physical parameter, by PCI-E bus to from equipment transmission data and control it is described from equipment by the PCI-E bus to
The master transmissions data, comprising:
The read request that receiving process is sent, under the instruction of the read request, according to each PCI-E bus postponed
Physical parameter, control it is described from equipment by the PCI-E bus to the master transmissions data；The process runs on institute
It states on main equipment；
The write request that the process is sent is received, under the instruction of the write request, according to total with each PCI-E postponed
The physical parameter of line, by the PCI-E bus to described from equipment transmission data.
5. according to the method described in claim 4, it is characterized in that, total by the PCI-E from equipment described in the control
Line to after the master transmissions data, the method also includes:
By the data storage transmitted from equipment to PCI-E memory, and the data transmitted from equipment are recorded described
The storage address of PCI-E memory；
It is determined as the storage address for the user's space that the data transmitted from equipment are distributed；
Based on described in record from equipment transmit data the PCI-E memory storage address, using direct addressing method
The data transmitted from equipment described in the PCI-E memory lookup；
The data transmitted described in finding from equipment are from the PCI-E memory copying to the user's space.
6. according to the method described in claim 5, it is characterized in that, the method also includes:
It is sent to the process and reads feedback command, the feedback command of reading includes the use distributed for the data transmitted from equipment
The storage address in family space, the feedback command of reading are used to indicate what the process was distributed from the data transmitted for described in from equipment
The storage address of user's space obtains the data transmitted from equipment.
7. a kind of data transmission device of high-speed peripheral component interconnection bus system, which is characterized in that described device includes:
Module is obtained, for after os starting, obtaining the high-speed peripheral component stored in the operating system interconnection mark
The physical parameter of the value of the physical parameter of quasi- PCI-E bus, the PCI-E bus includes that PCI-E transport layer maximum load is big
Width is completed in small, PCI-E transport layer maximum read request size and PCI-E read operation；
Configuration module, the value of the physical parameter for configuring each PCI-E bus are the physics ginseng of the corresponding PCI-E bus obtained
Several values；
Transmission module, for according to the physical parameter of each PCI-E bus postponed, by PCI-E bus to described
From equipment transmission data and control it is described from equipment by the PCI-E bus to the master transmissions data.
8. device according to claim 7, which is characterized in that
The value of the PCI-E transport layer maximum load size obtained is, the main equipment and described supports from equipment
The maximum maximum load size of PCI-E transport layer；
The value of the PCI-E transport layer maximum read request size obtained is that the PCI-E transport layer that the main equipment is supported is maximum
Maximum read request size, alternatively, the PCI-E bus transmission system provide practical business support maximum data packet it is long；
The value that width is completed in the PCI-E read operation obtained is that the PCI-E maximum read operation that the main equipment is supported is completed wide
Degree.
9. device according to claim 8, which is characterized in that
It is supported when the maximum data packet length that the practical business that the PCI-E bus transmission system provides is supported with the main equipment
When each PCI-E transport layer maximum read request is of different sizes, the PCI-E transport layer maximum read request size of acquisition
Value is the maximum maximum read request size of PCI-E transport layer that the main equipment is supported；
Belong to the main equipment support when the maximum data packet that the practical business that the PCI-E bus transmission system provides is supported is long
PCI-E transport layer maximum read request size when, the value of the PCI-E transport layer maximum read request size of acquisition is described
The maximum data packet that the practical business that PCI-E bus transmission system provides is supported is long.
10. a kind of high-speed peripheral component interconnection bus system, which is characterized in that the system comprises:
Main equipment,
The slave equipment being connect by PCI-E bus with the main equipment,
The main equipment is used for, and after os starting, obtains the high-speed peripheral component interconnection stored in the operating system
The physical parameter of the value of the physical parameter of standard PCI-E bus, the PCI-E bus includes that PCI-E transport layer maximum load is big
Width is completed in small, PCI-E transport layer maximum read request size and PCI-E read operation；Configure the physics of each PCI-E bus
The value of parameter is the value of the physical parameter of the corresponding PCI-E bus obtained；According to the object with each PCI-E bus postponed
Manage parameter, by PCI-E bus to from equipment transmission data and control it is described from equipment by the PCI-E bus to institute
State master transmissions data.
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