CN108897703A - A kind of high speed data transmission system and method based on PCIE - Google Patents
A kind of high speed data transmission system and method based on PCIE Download PDFInfo
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- CN108897703A CN108897703A CN201810571824.2A CN201810571824A CN108897703A CN 108897703 A CN108897703 A CN 108897703A CN 201810571824 A CN201810571824 A CN 201810571824A CN 108897703 A CN108897703 A CN 108897703A
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- pcie
- dma
- fpga module
- data transmission
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004891 communication Methods 0.000 claims abstract description 9
- 230000003993 interaction Effects 0.000 claims description 8
- 238000012790 confirmation Methods 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 claims description 2
- 238000012546 transfer Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000013475 authorization Methods 0.000 description 1
- 238000013480 data collection Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The invention discloses a kind of high speed data transmission system and method based on PCIE, the high speed data transmission system includes host, FPGA module and PCIE bus, the PCIE bus is used to connect the rapid communication between host and FPGA module, the host, FPGA module have the PCIE interface of grafting PCIE bus, the host is the main side of PCIE bus, FPGA module is PCIE bus from end, to the completion read-write operation to DMA.High speed data transmission system and method for the invention, master control DMA, address of cache, interruption etc. between host and FPGA module, it improves the speed of data transmission and ensure that the reliability of data transmission, it can be applicable to some equipment interacted with host progress high-speed data, such as data collecting card, FPGA accelerator card.
Description
Technical field
The present invention relates to data processing system and method, belong to field of computer technology, more particularly to a kind of based on PCIE
High speed data transmission system and method.
Background technique
With the continuous development of computer technology and information technology, the speed of existing some data transmission systems without
Method meets the requirement to data transmission bauds such as communication system and data collection system.
Data transmission bus of the PCIE bus as a new generation, carries out data biography by the way of end-to-end, differential serial
It is defeated, this transmission mode power consumption, rate, in terms of have preferable advantage.
Between host and various data modules, FPGA module, often need at a high speed and accurate data transmission, to meet data
Exchange and processing etc. require, and traditional data transmission system often cannot achieve this requirement in the prior art, therefore can be with
In conjunction with PCIE bussing technique, more demanding to data transmission bauds equipment room communication is effectively innovated and perfect.
As Chinese patent (Authorization Notice No. CN103984646B) discloses a kind of " storage system transmitted based on PCIE data
System design method ", content includes：The CPU PCIE2.0 interface of server master board is drawn and is used as data exchange channel, every 16
A PCIE channel is used as one group of corresponding physical address port；This 16 PCIE channel signals are subjected to four tunnels
Branch, and respectively correspond four virtual addresses and form Virtual PC IE address tunnel；Virtual PC IE address tunnel is connected to storage
The input terminal of FLASH controller, PCIE agreement is directly decoded by storage FLASH controller, and data are directly distributed and are deposited
It stores up in FLASH particle；When read operation, the data in FLASH are carried out PCIE coding by storage FLASH controller, and will be counted
According to being placed directly in Virtual PC IE address tunnel, high speed, the transmission of the data of low latency of entire PCIE link are realized.
Summary of the invention
The present invention provides a kind of high speed data transmission system and method based on PCIE, for solving in the prior art ask
Topic.
The present invention is achieved by the following technical programs：
A kind of high speed data transmission system based on PCIE, including host, FPGA module and PCIE bus, the PCIE
Bus is used to connect the rapid communication between host and FPGA module, and the host, FPGA module have grafting PCIE bus
PCIE interface, the host be PCIE bus main side, FPGA module be PCIE bus from end, to the completion to DMA
Read-write operation.
A kind of high speed data transmission system based on PCIE as described above, the FPGA module includes master control DMA mono-
Member, address and data/address bus, control and status register, interrupt control unit, dual-ported memory, master control DMA unit and both-end
Mouth register communication connection, address connect the PCIE interface of FPGA module with data/address bus one end, and the other end is separately connected master control
DMA unit, control and status register；It is described after there is mistake in the completion of master control DMA unit read-write operation or transmission process
Interrupt control unit generates MSI interrupt for controlling PCIE bus.
A kind of high speed data transmission system based on PCIE as described above, the FPGA module be data collecting card or
FPGA accelerator card.
The present invention provides a kind of high-speed data transmission method based on PCIE, the high speed number including such as claim 1-3
According to Transmission system, the high-speed data transmission method includes the following steps：
S1. before the master control DMA unit read-write operation operation, between host, FPGA module simultaneously by the connection of PCIE bus
Configuration, to establish correctly link access；
S2. host sends DMA and reads or writes order, and data packet corresponding with driver interaction generation is sent to FPGA mould
Block enters in control and mode control register；
S3. according to the content in control and status register, master control DMA unit is configured, host is to FPGA module
Returned data packet；
S3. after the completion of the read-write of master control DMA unit, generating interrupt notification host, this time data are transmitted.
A kind of high-speed data transmission method based on PCIE as described above, the DMA read procedure include：Host setting
Start command, address, size and the quantity order that DMA is read interact generation with driver and read TLP data packet；It is sent to
FPGA module, into control and mode control register；It is mono- to master control DMA according to the content in control and status register
Member is configured, and host returns to CPLD data packet to FPGA module；CPLD is parsed to take out effective data portion；Generate interruption
Host this time DMA read operation is notified to complete.
A kind of high-speed data transmission method based on PCIE as described above, the DMA write process include：Host setting
Start command, address, size and the quantity order of DMA write interact generation with driver and write TLP data packet；It is sent to
FPGA module, into control and mode control register；It is mono- to master control DMA according to the content in control and status register
Member is configured；Generating interrupt notification host, this time DMA write operation is completed.
A kind of high-speed data transmission method based on PCIE as described above, it is described before master control DMA unit read or write
It is configured between host, FPGA module, including obtains current PC IE bus transfer rate, confirmation EP local clock, confirmation biography
Whether the maximum load of transmission of data, the low power consumpting state of LTSSM state machine are opened, whether the channel VC opens and confirms BAR's
Address space.
Compared with prior art, it is an advantage of the invention that：
High speed data transmission system and method for the invention, between host and FPGA module master control DMA, address of cache,
Interrupt etc., it improves the speed of data transmission and ensure that the reliability of data transmission, can be applicable to some high with host progress
The equipment of fast data interaction, such as data collecting card, FPGA accelerator card.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described.
Fig. 1 is electrical schematic diagram of the invention；
Fig. 2 is FPGA internal electric schematic diagram described in Fig. 1；
Fig. 3 is flow chart of the invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.
Below to the present invention relates to technical term and writing a Chinese character in simplified form be illustrated：
FPGA full name in English Field-Programmable Gate Array, Chinese meaning are field programmable gate array；
DMA full name in English Direct Memory Access, Chinese meaning are direct memory access；
TLP full name in English Transaction Layer Packet, Chinese meaning are transport layer data packet；
CPLD full name in English Completion with data, Chinese meaning are the completion message with data；
BAR full name in English Base Address Register, full name in English base address register.
As shown in Figure 1, a kind of high speed data transmission system based on PCIE of the present embodiment, including host, FPGA module with
And PCIE bus, PCIE bus are used to connect the rapid communication between host and FPGA module, the equal band of the host, FPGA module
There is a PCIE interface of grafting PCIE bus, host is the main side of PCIE bus, and FPGA module is PCIE bus from end, to
Read-write operation is completed to DMA.
As shown in Fig. 2, the FPGA module of the present embodiment, including master control DMA unit, address and data/address bus, control and shape
State register, interrupt control unit, dual-ported memory, master control DMA unit and dual ported register communication connection, address and data
Bus one end connects the PCIE interface of FPGA module, and the other end is separately connected master control DMA unit, control and status register；It is main
It controls after there is mistake in the completion of DMA unit read-write operation or transmission process, interrupt control unit generates MSI for controlling PCIE bus
It interrupts.
Host uses PC machine, and is set as the main side of PCIE bus, and the EP core realized in FPGA module and DMA are PCIE
Bus from end, the high-speed traffic of PC machine and FPGA module is realized by PCIE interface, completes the read-write operation to DMA, is protected
Demonstrate,prove the speed and reliability of data transmission.What is stored in control and status register is content corresponding with DMA, such as opening for DMA
It opens and closes, the conveying length of DMA etc., the content root if what is received is to write TLP order, in control and status register
It is updated according to the address and data that receive；If what is received is to read TLP order, the content in control and status register
The end PC is returned to according to the address received；Occur mistake during the read or write to DMA is completed or is spread out of, interrupts control
Device processed generates interruptive command, and transmits the port PCIE and generate MSI interrupt.
As shown in figure 3, present embodiment discloses a kind of high-speed data transmission method based on PCIE, including it is as described above
High speed data transmission system, steps are as follows：
S1. before the master control DMA unit read-write operation operation, between host, FPGA module simultaneously by the connection of PCIE bus
Configuration, to establish correctly link access；
S2. host sends DMA and reads or writes order, and data packet corresponding with driver interaction generation is sent to FPGA mould
Block enters in control and mode control register；
S3. according to the content in control and status register, master control DMA unit is configured, host is to FPGA module
Returned data packet；
S3. after the completion of the read-write of master control DMA unit, generating interrupt notification host, this time data are transmitted.
DMA read procedure includes：Start command, address, size and the quantity order that DMA is read is arranged in host, with driving journey
Sequence interaction, which generates, reads TLP data packet；It is sent to FPGA module, into control and mode control register；According to control and shape
Content in state register configures master control DMA unit, and host returns to CPLD data packet to FPGA module；Parse CPLD
To take out effective data portion；This time DMA read operation of interrupt notification host is generated to complete.
It before carrying out DMA read-write operation, needs to complete to configure the end RP and EP of FPGA module, PC machine, to establish
Correctly link access；When doing the preparation before transmission data simultaneously, including obtaining Current bus transmission rate, the confirmation local EP
Clock, the confirmation transmission maximum load of data, LTSSM state machine low power consumpting state whether open, whether the channel VC opens and
Confirm the address space etc. of BAR.
The specific work process that DMA reads or writes is as follows：
DMA is read：These orders such as start command, address, size and the quantity that setting DMA is read at PC machine end；With driving
Program interaction generates corresponding reading TLP data packet, FPGA is sent to, into control/mode control register；According to control/
Content in status register, configures DMA；Host returns to CPLD data packet to FPGA；CPLD is parsed, is taken out effective
Data portion；Interrupt notification PC is generated, this time DMA read operation is completed.
DMA write：In these orders such as start command, address, size and the quantity of the end PC setting DMA write；With driving journey
Sequence interaction, which generates, writes TLP data packet accordingly, FPGA is sent to, into control/mode control register；According to control/shape
Content in state register, configures DMA；Interrupt notification PC is generated, this time DMA write operation is completed.
High speed data transmission system and method for the invention, between host and FPGA module master control DMA, address of cache,
Interrupt etc., it improves the speed of data transmission and ensure that the reliability of data transmission, can be applicable to some high with host progress
The equipment of fast data interaction, such as data collecting card, FPGA accelerator card.
The technology contents of the not detailed description of the present invention are well-known technique.
Claims (7)
1. a kind of high speed data transmission system based on PCIE, including host, FPGA module and PCIE bus, feature exist
In the PCIE bus is used to connect the rapid communication between host and FPGA module, and the host, FPGA module have slotting
The PCIE interface of PCIE bus is connect, the host is the main side of PCIE bus, and FPGA module is PCIE bus from end, to right
The completion read-write operation of DMA.
2. a kind of high speed data transmission system based on PCIE according to claim 1, which is characterized in that the FPGA mould
Block includes master control DMA unit, address and data/address bus, control and status register, interrupt control unit, dual-ported memory, master
DMA unit and dual ported register communication connection are controlled, address connects the PCIE interface of FPGA module with data/address bus one end, another
End is separately connected master control DMA unit, control and status register；Go out in the completion of master control DMA unit read-write operation or transmission process
After existing mistake, the interrupt control unit generates MSI interrupt for controlling PCIE bus.
3. a kind of high speed data transmission system based on PCIE according to claim 1, which is characterized in that the FPGA mould
Block is data collecting card or FPGA accelerator card.
4. a kind of high-speed data transmission method based on PCIE, including the high speed data transmission system as described in claim 1-3,
It is characterized in that, the high-speed data transmission method includes the following steps：
S1. it before the master control DMA unit read-write operation operation, connects and configures by PCIE bus between host, FPGA module,
To establish correctly link access；
S2. host sends DMA and reads or writes order, and the corresponding data packet of driver interaction generation, be sent to FPGA module into
Enter in control and mode control register；
S3. according to the content in control and status register, master control DMA unit is configured, host is returned to FPGA module
Data packet；
S3. after the completion of the read-write of master control DMA unit, generating interrupt notification host, this time data are transmitted.
5. a kind of high-speed data transmission method based on PCIE according to claim 4, which is characterized in that the DMA is read
Process includes：Start command, address, size and the quantity order that DMA is read is arranged in host, and generation is interacted with driver and is read
TLP data packet；It is sent to FPGA module, into control and mode control register；According in control and status register
Content configures master control DMA unit, and host returns to CPLD data packet to FPGA module；Parsing CPLD is effective to take out
Data portion；This time DMA read operation of interrupt notification host is generated to complete.
6. a kind of high-speed data transmission method based on PCIE according to claim 4, which is characterized in that the DMA write
Process includes：Start command, address, size and the quantity order of DMA write is arranged in host, and generation is interacted with driver and is write
TLP data packet；It is sent to FPGA module, into control and mode control register；According in control and status register
Content configures master control DMA unit；Generating interrupt notification host, this time DMA write operation is completed.
7. a kind of high-speed data transmission method based on PCIE according to claim 4, which is characterized in that master control DMA is mono-
It is configured between the host, FPGA module before first read or write, including obtains current PC IE bus transfer rate, confirmation
EP local clock, the confirmation transmission maximum load of data, LTSSM state machine low power consumpting state whether open, the channel VC whether
Open and confirm the address space of BAR.
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| CN201810571824.2A CN108897703A (en) | 2018-05-30 | 2018-05-30 | A kind of high speed data transmission system and method based on PCIE |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109800202A (en) * | 2019-01-17 | 2019-05-24 | 郑州云海信息技术有限公司 | A kind of data transmission system based on PCIE, method and device |
| CN109885508A (en) * | 2019-01-14 | 2019-06-14 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | High-speed peripheral component interconnection bus system and its data transmission method, device |
| CN110069443A (en) * | 2019-05-05 | 2019-07-30 | 山东浪潮人工智能研究院有限公司 | A kind of UFS memory array system and data transmission method based on FPGA control |
| CN110209358A (en) * | 2019-06-05 | 2019-09-06 | 哈尔滨工业大学 | A kind of NVMe equipment storage speed method for improving based on FPGA |
| CN110825674A (en) * | 2019-10-30 | 2020-02-21 | 北京计算机技术及应用研究所 | PCIE DMA (peripheral component interface express) interaction system and interaction method based on FPGA (field programmable Gate array) |
| CN111131873A (en) * | 2019-12-26 | 2020-05-08 | 曙光网络科技有限公司 | Server audio and video data processing method and processing device |
| CN111131738A (en) * | 2019-12-20 | 2020-05-08 | 合肥埃科光电科技有限公司 | Image acquisition system based on CoaXPress interface and acquisition method thereof |
| CN111679599A (en) * | 2020-05-22 | 2020-09-18 | 中国航空工业集团公司西安航空计算技术研究所 | High-reliability exchange method for CPU and DSP data |
| CN111858457A (en) * | 2020-07-15 | 2020-10-30 | 苏州浪潮智能科技有限公司 | Data processing method, device and system and FPGA |
| CN112699069A (en) * | 2020-12-28 | 2021-04-23 | 中孚信息股份有限公司 | High-speed data transmission method and system based on PCIe interface |
| CN114860158A (en) * | 2022-04-11 | 2022-08-05 | 中国电子科技集团公司第五十二研究所 | High-speed data acquisition and recording method |
| CN115328832A (en) * | 2022-10-11 | 2022-11-11 | 三未信安科技股份有限公司 | Data scheduling system and method based on PCIE DMA |
| WO2023226787A1 (en) * | 2022-05-24 | 2023-11-30 | 北京有竹居网络技术有限公司 | Communication method, system, and apparatus, and electronic device |
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2018
- 2018-05-30 CN CN201810571824.2A patent/CN108897703A/en not_active Withdrawn
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109885508A (en) * | 2019-01-14 | 2019-06-14 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | High-speed peripheral component interconnection bus system and its data transmission method, device |
| CN109800202B (en) * | 2019-01-17 | 2022-02-18 | 郑州云海信息技术有限公司 | PCIE (peripheral component interface express) -based data transmission system, method and device |
| CN109800202A (en) * | 2019-01-17 | 2019-05-24 | 郑州云海信息技术有限公司 | A kind of data transmission system based on PCIE, method and device |
| CN110069443A (en) * | 2019-05-05 | 2019-07-30 | 山东浪潮人工智能研究院有限公司 | A kind of UFS memory array system and data transmission method based on FPGA control |
| CN110209358A (en) * | 2019-06-05 | 2019-09-06 | 哈尔滨工业大学 | A kind of NVMe equipment storage speed method for improving based on FPGA |
| CN110209358B (en) * | 2019-06-05 | 2022-07-15 | 哈尔滨工业大学 | NVMe equipment storage speed improving method based on FPGA |
| CN110825674A (en) * | 2019-10-30 | 2020-02-21 | 北京计算机技术及应用研究所 | PCIE DMA (peripheral component interface express) interaction system and interaction method based on FPGA (field programmable Gate array) |
| CN110825674B (en) * | 2019-10-30 | 2021-02-12 | 北京计算机技术及应用研究所 | PCIE DMA (peripheral component interface express) interaction system and interaction method based on FPGA (field programmable Gate array) |
| CN111131738A (en) * | 2019-12-20 | 2020-05-08 | 合肥埃科光电科技有限公司 | Image acquisition system based on CoaXPress interface and acquisition method thereof |
| CN111131873A (en) * | 2019-12-26 | 2020-05-08 | 曙光网络科技有限公司 | Server audio and video data processing method and processing device |
| CN111679599A (en) * | 2020-05-22 | 2020-09-18 | 中国航空工业集团公司西安航空计算技术研究所 | High-reliability exchange method for CPU and DSP data |
| CN111679599B (en) * | 2020-05-22 | 2022-01-25 | 中国航空工业集团公司西安航空计算技术研究所 | High-reliability exchange method for CPU and DSP data |
| CN111858457A (en) * | 2020-07-15 | 2020-10-30 | 苏州浪潮智能科技有限公司 | Data processing method, device and system and FPGA |
| CN111858457B (en) * | 2020-07-15 | 2023-01-10 | 苏州浪潮智能科技有限公司 | Data processing method, device and system and FPGA |
| CN112699069A (en) * | 2020-12-28 | 2021-04-23 | 中孚信息股份有限公司 | High-speed data transmission method and system based on PCIe interface |
| CN114860158A (en) * | 2022-04-11 | 2022-08-05 | 中国电子科技集团公司第五十二研究所 | High-speed data acquisition and recording method |
| WO2023226787A1 (en) * | 2022-05-24 | 2023-11-30 | 北京有竹居网络技术有限公司 | Communication method, system, and apparatus, and electronic device |
| CN115328832A (en) * | 2022-10-11 | 2022-11-11 | 三未信安科技股份有限公司 | Data scheduling system and method based on PCIE DMA |
| CN115328832B (en) * | 2022-10-11 | 2023-01-17 | 三未信安科技股份有限公司 | Data scheduling system and method based on PCIE DMA |
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Application publication date: 20181127 |
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