CN109873399B - Power supply protection circuit and power supply protection device - Google Patents
Power supply protection circuit and power supply protection device Download PDFInfo
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- 239000003990 capacitor Substances 0.000 claims abstract description 66
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- 238000002955 isolation Methods 0.000 claims description 15
- 230000009471 action Effects 0.000 abstract description 21
- 230000002159 abnormal effect Effects 0.000 abstract description 4
- 230000007812 deficiency Effects 0.000 abstract 1
- 238000007726 management method Methods 0.000 description 63
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 238000001914 filtration Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 5
- 230000001960 triggered effect Effects 0.000 description 4
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- 238000005859 coupling reaction Methods 0.000 description 3
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- 238000009499 grossing Methods 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
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- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000015556 catabolic process Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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Abstract
The invention discloses a power supply protection circuit and a power supply protection device, which are provided with a detection circuit and a detection circuit, are used for calculating the difference value of a reference voltage value minus an analog OT voltage value detected by the detection circuit, and a first energy storage capacitor connected in parallel with a protection circuit output capacitor at a power output end of the power management chip PMIC, is used for providing more electric energy for heavy load when the load at the back end is changed violently, makes up the deficiency that the output capacitor of the original protection circuit has smaller capacity and can not provide enough electric energy, therefore, the error-reporting voltage detected by the detection circuit is stabilized in a normal working range, abnormal detection is prevented, the action of carrying out wrong over-temperature protection when the temperature of the line does not reach a limit value is effectively reduced, and unnecessary system downtime is avoided.
Description
Technical Field
The invention relates to the technical field of equipment power management, in particular to a power supply protection circuit and a power supply protection device.
Background
In the cloud computing era, mass data storage and transmission require a large-capacity storage carrier platform, and generally, in the operation process of a storage service system, a system power supply can be adjusted along with the change of the working state of a system storage unit of the large-capacity storage carrier, so that the stability and the safety of the system power supply are ensured. When the circuit is over-temperature, the power protection module of the equipment triggers over-temperature protection action (OTP) to stop the power supply of the equipment, so that the damage to the equipment and personnel is avoided.
However, in the actual working process of the power protection module, it often happens that the over-temperature protection is triggered when the line temperature does not reach the over-temperature protection limit value, and once the over-temperature protection is triggered, the system is down and stopped, and even the back-end equipment is affected.
How to prevent a power protection module of a device from performing wrong over-temperature protection actions when the line temperature does not reach a limit value, and avoiding unnecessary system downtime is a technical problem to be solved by technical personnel in the field.
Disclosure of Invention
Compared with the power protection module in the prior art, the power protection circuit and the power protection device provided by the invention have the advantages that the wrong over-temperature protection action is reduced when the line temperature does not reach the limit value, and unnecessary system downtime is avoided.
To solve the above technical problem, the present invention provides a power protection circuit, including:
the detection circuit is characterized in that the input end of the detection circuit is connected with the power output end of the power management chip PMIC, and the output end of the detection circuit is connected with the over-temperature protection detection signal input end of the power management chip PMIC;
the power management chip PMIC is used for calculating a difference value obtained by subtracting the analog OT voltage value detected by the detection circuit from a reference voltage value and sending an over-temperature protection signal to a system controller when the difference value is greater than a preset value;
and the first energy storage capacitor is connected with a protection circuit output capacitor of the power supply output end of the power supply management chip PMIC in parallel.
Optionally, the first energy storage capacitor is specifically an energy storage capacitor with a capacitance value between 220uf and 470 uf.
Optionally, the protection circuit further comprises a Snubber circuit connected in parallel with the protection circuit output capacitor.
Optionally, the Snubber circuit specifically includes a first resistor with a resistance value of 2.2 Ω -10 Ω and a capacitor with a capacitance value of 1000 pf;
the first end of the first resistor is connected with the power output end, the first end of the capacitor is connected with the second end of the first resistor, and the second end of the capacitor is grounded.
Optionally, the first energy storage capacitor and the Snubber circuit are both disposed between the power management chip PMIC and the protection line output capacitor.
Optionally, the power management system further includes an isolation circuit disposed at a power output end of the power management chip PMIC, and a controller connected to the detection circuit and configured to control the isolation circuit to block the detection circuit from receiving the analog OT voltage value when the detection circuit determines that the system is in a preset operating state according to an output signal of the power management chip PMIC.
Optionally, the isolation circuit specifically includes an MOS transistor having a gate connected to the control terminal of the controller, a drain connected to the power output terminal of the PMIC, and a source connected to the voltage detection enable terminal of the detection circuit;
the controller is specifically connected with a power management bus PMBus of the power management chip PMIC, and is used for judging the working state of the system according to an output signal of the power management bus PMBus, controlling the MOS tube to be switched on when the system works in a steady state, and controlling the MOS tube to be switched off when the system reaches the preset working state.
Optionally, the isolation circuit further includes a second resistor, a third resistor, and a second energy storage capacitor;
the second resistor is connected between a power output end of the power management chip PMIC and a drain electrode of the MOS tube;
the third resistor is connected between the control end of the controller and the grid electrode of the MOS tube;
the first end of the second energy storage capacitor is connected with the power output end of the power management chip PMIC, and the second end of the second energy storage capacitor is grounded.
Optionally, the resistance of the second resistor is specifically 10 Ω, and the resistance of the third resistor is specifically 100 Ω.
In order to solve the above technical problem, the present invention further provides a power protection device, including the power protection circuit described in any one of the above, and further including a PCB board for carrying the power protection circuit;
the ground terminal of the power input side of the power management chip PMIC and the ground terminal of the power output side of the power management chip PMIC are arranged on the same layer of PCB.
The power supply protection circuit provided by the invention comprises a detection circuit, a power supply management chip PMIC and a first energy storage capacitor, wherein the input end of the detection circuit is connected with the power supply output end of the power supply management chip PMIC, the output end of the detection circuit is connected with the over-temperature protection detection signal input end of the power supply management chip PMIC, the power supply management chip PMIC is used for calculating the difference value of the reference voltage value minus the analog OT voltage value detected by the detection circuit, and the over-temperature protection signal is sent to a system controller when the difference value is larger than the preset value, and the first energy storage capacitor is connected in parallel with the protection circuit output capacitor of the power supply output. In the prior art, only some capacitors with smaller capacitance values, which are used for providing electric energy when the system normally works, stabilizing voltage ripples and filtering noise of a path power supply, are connected to the power output end of the PMIC, however, when the power output end is switched to a larger load, the system can instantly extract internal charges from the output capacitor at the rear end of the protection circuit, and the output power supply provided by the capacitors is insufficient, so that the error-reporting voltage detected by the detection circuit changes suddenly, and the PMIC of the power management chip, which judges the line temperature according to the error-reporting voltage, triggers the over-temperature protection action by mistake, thereby causing the system to be down. The first energy storage capacitor connected with the output capacitor of the protection circuit in parallel is added at the power output end of the power management chip PMIC and used for providing more electric energy for the heavy load when the rear-end load is changed violently, so that the error-reporting voltage detected by the detection circuit is stabilized in a normal working range, abnormal detection is prevented, the error over-temperature protection action when the line temperature does not reach the limit value is effectively reduced, and unnecessary system downtime is avoided. The invention also provides a circuit protection device, which has the beneficial effects and is not described herein again.
Drawings
In order to more clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a power protection module in the prior art;
fig. 2 is a schematic diagram of a power protection module according to an embodiment of the present invention;
fig. 3 is a circuit diagram of a power protection circuit according to an embodiment of the invention;
fig. 4 is a circuit diagram of a power protection circuit according to a second embodiment of the present invention;
fig. 5 is a circuit diagram of a power protection circuit according to a third embodiment of the present invention.
Detailed Description
Compared with the power protection module in the prior art, the power protection circuit and the power protection device provided by the invention have the advantages that the wrong over-temperature protection action is reduced when the line temperature does not reach the limit value, and unnecessary system downtime is avoided.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
FIG. 1 is a schematic diagram of a power protection module in the prior art; fig. 2 is a schematic diagram of a power protection module according to an embodiment of the present invention; fig. 3 is a circuit diagram of a power protection circuit according to an embodiment of the invention.
As shown in fig. 1, a power protection module in the prior art includes a power management chip PMIC, an input terminal of the power management chip PMIC includes an energy storage module and a filtering module, an output terminal of the power management chip PMIC is provided with the filtering module and a small-capacity energy storage module (a capacitor with a small capacitance value), and then is connected to a load, and a system controller is connected to the power management chip PMIC and the load through an enable control terminal and an information interaction module. And the output end of the power management chip PMIC is also provided with a detection circuit for detecting the analog OT voltage of the power output end of the power management chip PMIC.
The power management chip PMIC has an analog OTP and a digital OTP, receives an analog OT voltage value of a power output terminal (i.e., a load terminal) detected by the detection circuit, and the digital OT signal is obtained by sampling the analog OT signal. The analog OTP is faster than the digital OTP, when the analog OT voltage value is higher than the reference voltage value, the over-temperature protection action can be triggered, when the power output end is switched to a larger load, because the small-capacity energy storage module at the power output end can not provide larger energy storage capacity, the analog OT signal will fluctuate greatly, and even if the line temperature is lower than the over-temperature protection limit value, the over-temperature protection signal can be sent to the system controller.
As shown in fig. 2, in the power protection module according to the embodiment of the present invention, on the basis of the power protection module in the prior art shown in fig. 1, a large-capacity energy storage module is disposed between a detection point of a detection circuit and a PMIC of a power management chip, so that a system is switched to a heavy-load mode to stably provide a load current, and stable operation of a back-end device is ensured.
As shown in fig. 3, based on the architecture provided in fig. 2, the power protection circuit provided in the embodiment of the present invention includes:
the input end of the detection circuit is connected with the power output end of the power management chip PMIC, and the output end of the detection circuit is connected with the over-temperature protection detection signal input end of the power management chip PMIC;
the power management chip PMIC is used for calculating a difference value of subtracting the analog OT voltage value detected by the detection circuit from the reference voltage value and sending an over-temperature protection signal to the system controller when the difference value is greater than a preset value;
and the first energy storage capacitor C20 is connected with the protection circuit output capacitors (C10-C13) of the power supply output end of the power supply management chip PMIC in parallel.
In an implementation, the PMIC may be an MP5023 chip, as shown in fig. 1, and the detection circuit is connected to three pins, i.e., ISET, IMON, and ADDR, of the MP5023 chip. The DAT, CLK and Alert pins of the MP5023 chip are connected with a system controller through a power management bus PMBus. In addition, the input end of the MP5023 chip is also connected with the energy storage module, the filtering module and the module for information interaction, which are not shown in fig. 1, and the detailed connection can refer to the prior art and is not described herein again.
A plurality of protection circuit output capacitors (C10-C13) are connected in parallel between the Vout end of the MP5023 chip and the ground, are all small-capacity capacitors and are used for providing electric energy, stabilizing voltage ripple and filtering noise of a path power supply when the system works normally.
In a specific implementation, the first energy storage capacitor C20 may employ an energy storage capacitor having a capacitance value between 220uf and 470 uf. When the wiring layout is performed on the PCB, a preferred embodiment is to dispose the first energy-storage capacitor C20 between the PMIC and the protection circuit output capacitor. In addition, the first energy storage capacitor C20 may include a plurality of capacitors (preferably no more than 3 capacitors) depending on the space utilization of the PCB.
The power protection circuit provided by the embodiment of the invention comprises a detection circuit, a power management chip PMIC and a first energy storage capacitor, wherein the input end of the detection circuit is connected with the power output end of the power management chip PMIC, the output end of the detection circuit is connected with the over-temperature protection detection signal input end of the power management chip PMIC, the detection circuit is used for calculating the difference value of the reference voltage value minus the analog OT voltage value detected by the detection circuit, and the first energy storage capacitor is connected in parallel with the protection circuit output capacitor of the power output end of the power management chip PMIC when the difference value is greater than the preset value and sends the over-temperature protection signal to a system controller. In the prior art, only some capacitors with smaller capacitance values, which are used for providing electric energy when the system normally works, stabilizing voltage ripples and filtering noise of a path power supply, are connected to the power output end of the PMIC, however, when the power output end is switched to a larger load, the system can instantly extract internal charges from the output capacitor at the rear end of the protection circuit, and the output power supply provided by the capacitors is insufficient, so that the error-reporting voltage detected by the detection circuit changes suddenly, and the PMIC of the power management chip, which judges the line temperature according to the error-reporting voltage, triggers the over-temperature protection action by mistake, thereby causing the system to be down. The first energy storage capacitor connected with the output capacitor of the protection circuit in parallel is added at the power output end of the power management chip PMIC and used for providing more electric energy for the heavy load when the rear-end load is changed violently, so that the error-reporting voltage detected by the detection circuit is stabilized in a normal working range, abnormal detection is prevented, the error over-temperature protection action when the line temperature does not reach the limit value is effectively reduced, and unnecessary system downtime is avoided.
Example two
Fig. 2 is a circuit diagram of a power protection circuit according to a second embodiment of the present invention. As shown in fig. 2, on the basis of the above embodiment, in another embodiment, the power protection circuit further includes a Snubber circuit 3 connected in parallel with the protection line output capacitance.
The Snubber circuit 3 is a buffer circuit and is used for filtering voltage spikes, inhibiting overshoot, smoothing a flowing voltage curve, and further preventing the error triggering of protection action due to the spike voltage.
In a specific implementation, the Snubber circuit 3 may specifically include a first resistor R1 having a resistance value between 2.2 Ω -10 Ω and a capacitor C30 having a capacitance value of 1000 pf;
the first end of the first resistor R1 is connected with the power output end, the first end of the capacitor C30 is connected with the second end of the first resistor R1, and the second end of the capacitor C30 is grounded.
When the wiring layout is performed on the PCB, a better implementation mode is to arrange the Snubber circuit 3 between the PMIC of the power management chip and the output capacitor of the protection circuit.
The power supply protection circuit provided by the embodiment of the invention further comprises a Snubber circuit connected with the output capacitor of the protection circuit in parallel on the basis of the embodiment, so that the effects of filtering voltage spikes, inhibiting overshoot and smoothing a flowing voltage curve are achieved, and the error triggering of protection action caused by spike voltage is further prevented.
EXAMPLE III
Fig. 3 is a circuit diagram of a power protection circuit according to a third embodiment of the present invention. As shown in fig. 3, in another embodiment based on the above embodiment, the power protection circuit further includes an isolation circuit 4 disposed at the power output terminal of the power management chip PMIC, and a controller 5 connected to the detection circuit and controlling the isolation circuit 4 to block the detection circuit from receiving the analog OT voltage value when the detection circuit determines that the system is in the preset operating state according to the output signal of the power management chip PMIC.
Because the voltage fluctuation which can cause the power management chip PMIC to trigger the over-temperature protection action by mistake is only the transient condition when the system switches a high load, the detection circuit can temporarily stop receiving the analog OT voltage value when the abnormal fluctuation of the voltage is detected, and the power management chip PMIC is prevented from triggering the over-temperature protection action by mistake due to the voltage peak. The operation of the controller 5 may be performed by a system controller.
In an embodiment, the isolation circuit 4 may specifically include a MOS transistor M1 having a gate connected to the control terminal of the controller 5, a drain connected to the power output terminal of the power management chip PMIC, and a source connected to the voltage detection enable terminal Vdet of the detection circuit;
the controller 5 is specifically connected to a power management bus PMBus of a PMIC (not shown in fig. 3, and the specific connection mode may refer to a connection mode between a system controller and the power management bus PMBus in the prior art), and is configured to determine a working state of the system according to an output signal of the power management bus PMBus, and control the MOS transistor M1 to be turned on when the system is in a steady state, and control the MOS transistor M1 to be turned off when the system reaches a preset working state.
The controller 5 reads the state information of the power management bus PMbus in real time through the power management bus PMbus, and controls the MOS transistor M1 to be turned on or off according to the change of the current working state. When the system works in a steady-state mode, the control signal output by the controller 5 is at a high level, the MOS transistor M1 is in a normally open state, and the voltage detection enable terminal Vdet of the power management chip PMIC is in an enable state; when the working state of the system changes dramatically, the control signal output by the controller 5 is low level, the MOS transistor M1 is in cut-off state, so that the voltage detection enable terminal Vdet of the detection circuit is in non-enable state, the protection action is prevented from being triggered by the peak voltage by mistake, after the logic of the system delays for 5ms, whether the working mode of the system is in steady state is judged, if yes, a high level control signal is output to enable the MOS transistor M1 to be connected, so that the voltage detection enable terminal Vdet of the detection circuit is in enable state.
The MOS transistor M1 adopts an N-channel power type MOS transistor.
Further, the isolation circuit 4 may further include a second resistor R2, a third resistor R3, and a second energy storage capacitor C40;
the second resistor R2 is connected between the power output end of the power management chip PMIC and the drain of the MOS transistor M1;
the third resistor R3 is connected between the control end of the controller 5 and the gate of the MOS transistor M1;
the first end of the second energy-storing capacitor C40 is connected to the power output end of the power management chip PMIC, and the second end of the second energy-storing capacitor C40 is grounded.
Optionally, the resistance of the second resistor R2 is specifically 10 Ω, and the resistance of the third resistor R3 is specifically 100 Ω.
The power protection circuit provided by the embodiment of the invention further comprises an isolation circuit and a controller on the basis of the embodiment, wherein the controller controls the isolation circuit to isolate the detection circuit from receiving the analog OT voltage value when judging that the system is in the preset working state through the output signal of the power management chip PMIC, so that the power management chip PMIC is further prevented from mistakenly triggering the over-temperature protection action due to the voltage spike.
On the basis of the above embodiments, the power protection circuit may include both the Snubber circuit 3 provided in the second embodiment of the present invention and the isolation circuit 4 provided in the third embodiment.
On the basis of the above detailed description of various embodiments corresponding to the power protection circuit, the invention also discloses a power protection device corresponding to the power protection circuit.
Example four
On the basis of the above embodiment, in another embodiment, the present invention further provides a power protection device that may include any one of the above power protection circuits, and further includes a PCB board for carrying the power protection circuit;
the ground terminal of the power input side of the power management chip PMIC and the ground terminal of the power output side of the power management chip PMIC are arranged on the same layer of PCB.
As shown in fig. 3, the detection circuit simulates that the OT voltage is related to VCC, and if VCC is unstable, the logic of the PMIC will be affected. In practical application, because the device integrated circuit is laid out in the multilayer PCB, the ground terminal of the power input side and the ground terminal of the power output side of the power management chip PMIC are often connected through the second power ground terminal instead of being directly connected, and the distance between the two ground terminals is long, so that parasitic inductance is generated in a ground path, and voltage fluctuation is also generated, which causes the power management chip PMIC to trigger an over-temperature protection action by mistake.
Therefore, the grounding end of the power input side of the power management chip PMIC and the grounding end of the power output side of the power management chip PMIC are welded on the same layer of PCB, so that the correct reasonability of circuit design and PCB layout is ensured, the system breakdown caused by the false triggering of over-temperature protection action is further avoided, and the product reliability is improved.
Since other embodiments of the power protection device portion correspond to the embodiments of the power protection circuit portion, please refer to the description of the embodiments of the power protection circuit portion, which is not repeated herein.
In the embodiments provided in the present application, it should be understood that the disclosed power protection circuit and power protection apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of modules is merely a division of logical functions, and an actual implementation may have another division, for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
The power protection circuit and the power protection device provided by the invention are described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (9)
1. A power protection circuit, comprising:
the detection circuit is characterized in that the input end of the detection circuit is connected with the power output end of the power management chip PMIC, and the output end of the detection circuit is connected with the over-temperature protection detection signal input end of the power management chip PMIC;
the power management chip PMIC is used for calculating a difference value obtained by subtracting the analog OT voltage value detected by the detection circuit from a reference voltage value and sending an over-temperature protection signal to a system controller when the difference value is greater than a preset value;
the first energy storage capacitor is connected with a protection circuit output capacitor of a power supply output end of the power supply management chip PMIC in parallel;
the isolation circuit is arranged at a power supply output end of the power management chip PMIC, and the controller is connected with the detection circuit and controls the isolation circuit to isolate the detection circuit from receiving the analog OT voltage value when the output signal of the power management chip PMIC judges that a system is in a preset working state;
the controller executes corresponding work through the controller, or the work corresponding to the controller is executed through the system controller.
2. The power protection circuit according to claim 1, wherein the first energy storage capacitor is an energy storage capacitor having a capacitance value of 220uf to 470 uf.
3. The power protection circuit of claim 1, further comprising a Snubber circuit in parallel with the protection line output capacitance.
4. A power protection circuit according to claim 3, wherein said Snubber circuit comprises in particular a first resistor having a value comprised between 2.2 Ω -10 Ω and a capacitor having a capacitance of 1000 pf;
the first end of the first resistor is connected with the power output end, the first end of the capacitor is connected with the second end of the first resistor, and the second end of the capacitor is grounded.
5. The power protection circuit of claim 3, wherein the first energy storage capacitor and the Snubber circuit are both disposed between the power management chip PMIC and the protection line output capacitor.
6. The power protection circuit of claim 1, wherein the isolation circuit comprises a MOS transistor having a gate connected to the control terminal of the controller, a drain connected to the power output terminal of the PMIC, and a source connected to the voltage detection enable terminal of the detection circuit;
the controller is specifically connected with a power management bus PMBus of the power management chip PMIC, and is used for judging the working state of the system according to an output signal of the power management bus PMBus, controlling the MOS tube to be switched on when the system works in a steady state, and controlling the MOS tube to be switched off when the system reaches the preset working state.
7. The power protection circuit of claim 6, wherein the isolation circuit further comprises a second resistor, a third resistor, and a second energy storage capacitor;
the second resistor is connected between a power output end of the power management chip PMIC and a drain electrode of the MOS tube;
the third resistor is connected between the control end of the controller and the grid electrode of the MOS tube;
the first end of the second energy storage capacitor is connected with the power output end of the power management chip PMIC, and the second end of the second energy storage capacitor is grounded.
8. The power protection circuit according to claim 7, wherein the second resistor has a resistance of 10 Ω, and the third resistor has a resistance of 100 Ω.
9. A power protection device comprising the power protection circuit of any one of claims 1 to 8, and further comprising a PCB board for carrying the power protection circuit;
the ground terminal of the power input side of the power management chip PMIC and the ground terminal of the power output side of the power management chip PMIC are arranged on the same layer of PCB.
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| CN201910299822.7A CN109873399B (en) | 2019-04-15 | 2019-04-15 | Power supply protection circuit and power supply protection device |
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| CN201910299822.7A CN109873399B (en) | 2019-04-15 | 2019-04-15 | Power supply protection circuit and power supply protection device |
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