CN103259422A - Power supply device - Google Patents
Power supply device Download PDFInfo
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- CN103259422A CN103259422A CN 201210038107 CN201210038107A CN103259422A CN 103259422 A CN103259422 A CN 103259422A CN 201210038107 CN201210038107 CN 201210038107 CN 201210038107 A CN201210038107 A CN 201210038107A CN 103259422 A CN103259422 A CN 103259422A
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- Prior art keywords
- circuit
- switch
- reduction voltage
- psu
- voltage circuit
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Abstract
The invention discloses a power supply device which comprises a voltage reduction circuit, a power supply unit (PSU), a buffer circuit and a logic circuit connected to the PSU and the buffer circuit. The PSU is used for supplying a direct current to the voltage reduction circuit. The voltage reduction circuit is used for converting voltage of the direct current into preset voltage and supplying the preset voltage to a receiving end. The buffer circuit is connected to the voltage reduction circuit and used for preventing the voltage reduction circuit from being damaged when the voltage reduction circuit works under a heavy-load power supply state. The buffer circuit is selectively connected to the voltage reduction circuit through the logic circuit. The PSU detects whether the voltage reduction circuit is under the heavy-load state or not and triggers the logic circuit to allow the buffer circuit to be connected to the voltage reduction circuit correspondingly when the voltage reduction circuit is under the heavy-load state. Correspondingly when the voltage reduction circuit is under a light-load state, the PSU triggers the logic circuit to allow the buffer circuit and the voltage reduction circuit to be disconnected so that power loss generated by the buffer circuit can be eliminated.
Description
Technical field
The present invention relates to a kind of supply unit, relate in particular to a kind of supply unit with buffer circuit.
Background technology
Supply units such as present notebook computer, server generally include power-supply unit (Power supply unit, PSU) and reduction voltage circuit, described PSU is converted to direct current in order to the alternating current that will insert from the external world, described reduction voltage circuit is low to moderate default magnitude of voltage in order to the galvanic voltage drop with the PSU conversion, is supplied to receiving ends such as server system.Existing reduction voltage circuit generally include controller such as pulse width modulation chip, successively be serially connected with first switch between PSU and the ground, second switch, be connected in parallel to outputting inductance and the storage capacitor of second switch opposite end after the serial connection mutually, receiving ends such as server system then are connected in parallel to the opposite end of storage capacitor, and control the conducting and become default voltage to be supplied to receiving end the voltage transitions of PSU output successively of described first switch and second switch by controller.Yet, when described supply unit exports the voltage of load to when higher (this reduction voltage circuit is in heavy condition), switch to the moment of off-state from conducting state at described second switch, voltage on this second switch may increase suddenly because of the effect of the voltage of PSU supply, thereby burns out described second switch.To this, existing operating type is the buffer circuit that serial connection is made up of resistance and electric capacity between second switch and outputting inductance, the too high phenomenon of transient voltage when disconnecting to suppress described second switch.As seen; though above-mentioned buffer circuit can prevent that effectively second switch from being burnt out when supply unit is in heavy duty (voltage of output is higher); but this buffer circuit is in when need not to protect second switch under the light condition at supply unit, then can leave unused and increases the power loss of this supply unit.
Summary of the invention
In view of above content, be necessary to provide in the higher power supply of a kind of power supplying efficiency and install.
A kind of supply unit, in order to receiving end is powered, this supply unit comprises reduction voltage circuit, power-supply unit (power supply unit, PSU), buffer circuit and one is connected to the logical circuit of PSU and buffer circuit, described PSU is in order to supply direct current to described reduction voltage circuit, this reduction voltage circuit becomes a default voltage to be supplied to receiving end described galvanic voltage transitions, described buffer circuit is connected to reduction voltage circuit, impaired in order to prevent that described reduction voltage circuit is in when working under the heavily loaded power supply state, described buffer circuit selects to be connected to reduction voltage circuit by logical circuit, described PSU detects reduction voltage circuit and whether is in heavy condition, and corresponding reduction voltage circuit triggers logical circuit when being in heavy condition buffer circuit is connected to reduction voltage circuit; When corresponding reduction voltage circuit was in light condition, this PSU triggering logical circuit disconnection buffer circuit was connected with reduction voltage circuit, to eliminate the loss that described buffer circuit produces.
Described supply unit is in heavy condition and may be impaired the time, control described buffer circuit and be connected to reduction voltage circuit, with this reduction voltage circuit of effective protection in described reduction voltage circuit; And can not damage and need not buffer circuit when protection is provided when reduction voltage circuit is in light condition; described supply unit disconnects being connected of described buffer circuit and reduction voltage circuit; to eliminate the power loss that this buffer circuit produces, make the power supplying efficiency of this supply unit higher.
Description of drawings
Fig. 1 is that supply unit of the present invention is to the circuit theory diagrams of receiving end power supply.
The main element symbol description
| Supply unit | 100 |
| Reduction voltage circuit | 10 |
| Controller | 11 |
| First switch | Q1 |
| Second switch | Q2 |
| Outputting inductance | L |
| Storage capacitor | C1 |
| PSU | 30 |
| Buffer circuit | 50 |
| Resistance | R |
| Buffer capacitor | C2 |
| Logical circuit | 70 |
| Logic module | 71 |
| Logic switch | 73 |
| Receiving end | 200 |
Following embodiment will further specify the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiments the present invention is described in further detail:
See also shown in Figure 1ly, supply unit 100 of the present invention is in order to receiving ends such as server system 200 power supply.This supply unit 100 comprises reduction voltage circuit 10, power-supply unit (power supply unit, PSU) 30, buffer circuit 50 and logical circuit 70, described PSU30 is connected to reduction voltage circuit 10 and logical circuit 70, described logical circuit 70 also is connected to buffer circuit 50, in order to control the electric connection between described buffer circuit 50 and the reduction voltage circuit 10.Described PSU30 is in order to providing DC power supply to reduction voltage circuit 10, and detects this PSU30 and export reduction voltage circuit 10 current values to.This PSU30 detects the current value of its output and judges that described reduction voltage circuit 10 is in heavy condition when higher, triggers logical circuit 70 then buffer circuit 50 is connected to reduction voltage circuit 10, to protect this reduction voltage circuit 10; The current value that detects its output as this PSU30 hour judges that described reduction voltage circuit 10 is in when need not to protect this reduction voltage circuit 10 under the light condition; trigger described logical circuit 70 and disconnect being connected of described buffer circuit 50 and reduction voltage circuit 10, eliminate the power loss of these buffer circuit 50 generations.
Described reduction voltage circuit 10 comprises controller 11, the first switch Q1, second switch Q2, outputting inductance L and storage capacitor C1.
Described controller 11 is connected to the first switch Q1 and second switch Q2, controls the described first switch Q1 and second switch Q2 conducting/disconnection successively in order to the magnitude of voltage that exports receiving end 200 according to this reduction voltage circuit 10 to.In embodiment of the present invention, described controller 11 is a pulse width modulation chip, and the duty of the pulse width modulating signal by being sent to the first switch Q1 and second switch Q2 is recently regulated the conducting duration of the described first switch Q1 and second switch Q2, the size of the magnitude of voltage of these reduction voltage circuit 10 outputs of corresponding adjusting.
The described first switch Q1 and second switch Q2 are serially connected with between PSU30 and the ground successively, after described outputting inductance L and storage capacitor C1 contact mutually, the other end of storage capacitor C1 is connected between the first switch Q1 and the second switch Q2, the other end ground connection of outputting inductance L.Described receiving end 200 is connected in parallel to the opposite end of storage capacitor C1.So, as the described controller 11 conductings first switch Q1, when disconnecting second switch Q2, the electric energy that the PSU30 termination is gone into will be supplied to receiving end 200 and storage capacitor C1 from the first switch Q1, outputting inductance L, to pass through storage capacitor C1 storage of electrical energy in to receiving end 200 power supplies the time; When described controller 11 disconnected the first switch Q1, conducting second switch Q2, then PSU30 stopped 10 power supplies of this reduction voltage circuit, and the energy that is discharged its storage by storage capacitor C1 is to receiving end 200 power supplies.In embodiment of the present invention, the described first switch Q1 and second switch Q2 are a field effect transistor, and the described first switch Q1 is connected to controller 11 by grid, are connected to PSU30 by drain electrode, and are connected to second switch Q2 by source electrode; Described second switch Q2 is connected to the source electrode of the first switch Q1 by drain electrode, is connected to controller by grid, and passes through source ground.
Described PSU30 is connected to the first switch Q1 and the logical circuit 70 of reduction voltage circuit 10,, detects described reduction voltage circuit 10 simultaneously and is in heavy condition or light condition to reduction voltage circuit 10 in order to supplying DC power source.When this PSU30 detects described reduction voltage circuit 10 and is in heavy condition, trigger logical circuit 70 buffer circuit 50 is connected in parallel to second switch Q2; When detecting described reduction voltage circuit 10 and be in light condition, trigger described logical circuit 70 and disconnect being connected of buffer circuits 50 and second switch Q2.In embodiment of the present invention, corresponding its current value that exports reduction voltage circuit 10 to of described PSU30 is set a reference current value, and detect the current value that this PSU30 exports reduction voltage circuit 10 to, if the current value of exporting exceeds default reference current value, judge that then described reduction voltage circuit 10 is in heavy condition; Be lower than default reference current value if PSU30 exports the current value of reduction voltage circuit 10 to, judge that then described reduction voltage circuit 10 is in light condition.In embodiment of the present invention, described PSU30 is by system's control bus (System Management Bus, Smbus) SDA in and SCL holding wire are set up and the communicating by letter of logical circuit 70, and control being connected of buffer circuits 50 and reduction voltage circuit 10 thereby trigger described logical circuit 70.
Described buffer circuit 50 comprises a resistance R and a buffer capacitor C2, and the end after described resistance R and buffer capacitor C2 are in series is connected between second switch Q2 and the outputting inductance L, and the other end is by logical circuit 70 ground connection.So, when described logical circuit 70 during with buffer circuit 50 ground connection, this buffer circuit 50 namely is connected in parallel to described second switch Q2, and when described logical circuit 70 disconnects being connected of buffer circuits 50 and ground, described buffer circuit 50 will disconnect and being electrically connected of reduction voltage circuit 10.
Described logical circuit 70 comprises logic module 71 and logic switch 73.Described logic module 71 is electrically connected to PSU30, and is connected to logic switch 73, and an end of described logic switch 73 also is connected to buffer capacitor C2, other end ground connection.Conducting or the disconnection of described logic module 71 control logic switch 73 under the triggering of PSU30, accordingly with an end ground connection of described buffer circuit 50 or disconnect and being connected of ground, the correspondence realization is with described buffer circuit 50 and be connected to second switch Q2 or disconnect the two connection.In embodiment of the present invention, described logic switch 73 also is a field effect transistor, and described logic module 71 sends a high level signal to logic switch 73 and this logic switch 73 of conducting under the control of PSU30.
Use in the process of 100 pairs of receiving ends of this supply unit, 200 power supplies, described PSU30 provides a direct current power supply to reduction voltage circuit 10, controller 11 outputs one pulse width modulating signal with certain duty ratio is controlled the conducting duration of the described first switch Q1 and second switch Q2 then, makes this supply unit 100 keep output one predetermined voltage to be supplied to receiving end 200.In this process, described PSU30 detects its electric current that exports reduction voltage circuit 10 to, and judges whether the current value of output exceeds default reference current.When the electric current that exports reduction voltage circuit 10 to as described PSU30 exceeds default reference current, judge that this reduction voltage circuit 10 is in heavy condition, trigger the described logic switch 73 of logic module 71 conductings then, so that an end ground connection of buffer circuit 50 is connected in parallel on the second switch Q2, prevent that voltage on the second switch Q2 from damaging this second switch Q2 greatly because the effect of the voltage of PSU30 supply becomes suddenly when disconnecting.When the electric current that exports reduction voltage circuit 10 to as PSU30 is lower than default reference current, judge that then described reduction voltage circuit 10 is in light condition, trigger described logic module 71 then and disconnect logic switch 73, disconnecting being connected of buffer circuit 50 and second switch Q2, thereby eliminate the power loss that this buffer circuit 50 brings.
When supply unit 100 of the present invention is in heavy condition in described reduction voltage circuit 10, control described buffer circuit 50 and be connected to second switch Q2 in the reduction voltage circuit 10, excessive and burnt out to prevent that second switch Q2 from switching to the transient voltage of off-state by conducting, effectively protect this reduction voltage circuit 10; When this reduction voltage circuit 10 is in light condition; second switch Q2 can be when just not disconnecting voltage excessive and impaired and when need not buffer circuit 50 protection being provided; the described buffer circuit 50 of described supply unit 100 disconnections is connected with reduction voltage circuit 10; eliminate the power loss that this buffer circuit 50 produces, make the power supplying efficiency of this supply unit 100 higher.
To those skilled in the art, can make other corresponding changes or adjustment in conjunction with the actual needs of producing according to invention scheme of the present invention and inventive concept, and these changes and adjustment all should belong to the protection range of claim of the present invention.
Claims (7)
1. supply unit, in order to receiving end is powered, this supply unit comprises reduction voltage circuit, power-supply unit (power supply unit, PSU) and buffer circuit, described PSU is in order to supply direct current to described reduction voltage circuit, this reduction voltage circuit becomes a default voltage to be supplied to receiving end described galvanic voltage transitions, described buffer circuit is connected to reduction voltage circuit, impaired in order to prevent that described reduction voltage circuit is in when working under the heavily loaded power supply state, it is characterized in that: this supply unit comprises that also one is connected to the logical circuit of PSU and buffer circuit, described buffer circuit optionally is connected to reduction voltage circuit by logical circuit, described PSU detects reduction voltage circuit and whether is in heavy condition, and corresponding reduction voltage circuit triggers logical circuit when being in heavy condition buffer circuit is connected to reduction voltage circuit; When corresponding reduction voltage circuit was in light condition, this PSU triggering logical circuit disconnection buffer circuit was connected with reduction voltage circuit.
2. supply unit as claimed in claim 1, it is characterized in that: described PSU correspondence exports the default reference current of galvanic electric current of reduction voltage circuit to, and detect the electric current that this PSU exports reduction voltage circuit to and whether exceed described default reference current, if the electric current of described output exceeds default reference current and judges that then described reduction voltage circuit is in heavy condition, if being lower than default reference current, the electric current of described output judges that then described reduction voltage circuit is in light condition.
3. supply unit as claimed in claim 1, it is characterized in that: described logical circuit comprises logic module and the logic switch that is serially connected with successively between PSU and the ground, described logical circuit is connected to buffer circuit by logic switch, described PSU is by conducting or the disconnection of logic module control logic switch, corresponding described buffer circuit is connected to reduction voltage circuit, perhaps disconnects being connected of described buffer circuit and reduction voltage circuit.
4. supply unit as claimed in claim 3, it is characterized in that: described logic switch is a field effect transistor.
5. supply unit as claimed in claim 3 is characterized in that: described PSU sets up and the communicating by letter of described logic module by the SDA in system's control bus and SCL holding wire.
6. supply unit as claimed in claim 3, it is characterized in that: described buffer circuit comprises a resistance and electric capacity, described buffer circuit is connected to logic switch by electric capacity, and is connected between first switch and the second switch by resistance.
7. supply unit as claimed in claim 1, it is characterized in that: described reduction voltage circuit comprises controller, first switch, second switch, outputting inductance and storage capacitor, described first switch and second switch are serially connected with between PSU and the ground mutually, end after described outputting inductance and the storage capacitor serial connection is connected between first switch and the second switch, other end ground connection, described receiving end is connected in parallel to the opposite end of storage capacitor, described controller is controlled the default duration of first switch and second switch conducting one respectively, convert described default voltage to the power source voltage that PSU is provided and be supplied to receiving end, one end of described buffer circuit is connected between first switch and the second switch, the other end is by logical circuit ground connection, be connected in parallel to second switch with ground connection under the control of logical circuit, perhaps under the control of logical circuit, disconnect and disconnect being connected of this buffer circuit and reduction voltage circuit with being connected of ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201210038107 CN103259422A (en) | 2012-02-20 | 2012-02-20 | Power supply device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201210038107 CN103259422A (en) | 2012-02-20 | 2012-02-20 | Power supply device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103259422A true CN103259422A (en) | 2013-08-21 |
Family
ID=48963172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201210038107 Pending CN103259422A (en) | 2012-02-20 | 2012-02-20 | Power supply device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103259422A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734503A (en) * | 2015-04-15 | 2015-06-24 | 上海斐讯数据通信技术有限公司 | Power conversion system and electronic equipment with same |
| CN106953511A (en) * | 2017-04-28 | 2017-07-14 | 昆山龙腾光电有限公司 | Switching power circuit and its adjusting method |
| CN109873399A (en) * | 2019-04-15 | 2019-06-11 | 苏州浪潮智能科技有限公司 | A kind of power protecting circuit and apparatus for protecting power supply |
| CN112532039A (en) * | 2020-10-30 | 2021-03-19 | 苏州浪潮智能科技有限公司 | Intelligent control method and circuit for reducing electromagnetic radiation of switching power supply |
-
2012
- 2012-02-20 CN CN 201210038107 patent/CN103259422A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734503A (en) * | 2015-04-15 | 2015-06-24 | 上海斐讯数据通信技术有限公司 | Power conversion system and electronic equipment with same |
| CN104734503B (en) * | 2015-04-15 | 2018-03-06 | 上海斐讯数据通信技术有限公司 | A kind of power conversion system and the electronic equipment with this kind of power conversion system |
| CN106953511A (en) * | 2017-04-28 | 2017-07-14 | 昆山龙腾光电有限公司 | Switching power circuit and its adjusting method |
| CN106953511B (en) * | 2017-04-28 | 2019-06-21 | 昆山龙腾光电有限公司 | Switching power circuit and its adjusting method |
| CN109873399A (en) * | 2019-04-15 | 2019-06-11 | 苏州浪潮智能科技有限公司 | A kind of power protecting circuit and apparatus for protecting power supply |
| CN112532039A (en) * | 2020-10-30 | 2021-03-19 | 苏州浪潮智能科技有限公司 | Intelligent control method and circuit for reducing electromagnetic radiation of switching power supply |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130821 |