CN103259422A - Power supply device - Google Patents

Abstract

The invention discloses a power supply device which comprises a voltage reduction circuit, a power supply unit (PSU), a buffer circuit and a logic circuit connected to the PSU and the buffer circuit. The PSU is used for supplying a direct current to the voltage reduction circuit. The voltage reduction circuit is used for converting voltage of the direct current into preset voltage and supplying the preset voltage to a receiving end. The buffer circuit is connected to the voltage reduction circuit and used for preventing the voltage reduction circuit from being damaged when the voltage reduction circuit works under a heavy-load power supply state. The buffer circuit is selectively connected to the voltage reduction circuit through the logic circuit. The PSU detects whether the voltage reduction circuit is under the heavy-load state or not and triggers the logic circuit to allow the buffer circuit to be connected to the voltage reduction circuit correspondingly when the voltage reduction circuit is under the heavy-load state. Correspondingly when the voltage reduction circuit is under a light-load state, the PSU triggers the logic circuit to allow the buffer circuit and the voltage reduction circuit to be disconnected so that power loss generated by the buffer circuit can be eliminated.

Description

power supply unit

technical field

The invention relates to a power supply device, in particular to a power supply device with a buffer circuit.

Background technique

Current power supply devices such as notebook computers and servers usually include a power supply unit (Power supply unit, PSU) and a step-down circuit. The PSU is used to convert AC power from the outside into DC power. Reduce the voltage of the DC power converted by the PSU to a preset voltage value, and supply it to the power receiving end such as the server system. The existing step-down circuit usually includes a controller such as a pulse width modulation chip, a first switch serially connected between the PSU and the ground, a second switch, an output inductor connected in series and parallel to the opposite ends of the second switch, and a storage The power receiving end of the energy storage capacitor, the server system, etc. is connected in parallel to the opposite ends of the energy storage capacitor, and the controller controls the first switch and the second switch to turn on in sequence to convert the voltage output by the PSU into a preset voltage supplied to the receiving end. However, when the voltage output from the power supply device to the load is relatively high (that is, the step-down circuit is in a heavy load state), at the moment when the second switch is switched from the on state to the off state, the second switch The voltage of the PSU may suddenly increase due to the voltage supplied by the PSU, thereby burning out the second switch. In this regard, the existing operation method is to connect a snubber circuit composed of a resistor and a capacitor in series between the second switch and the output inductor, so as to suppress the instantaneous overvoltage phenomenon when the second switch is turned off. It can be seen that although the above snubber circuit can effectively prevent the second switch from being burned out when the power supply device is under heavy load (the output voltage is relatively high), the snubber circuit does not need to protect the second switch when the power supply device is under a light load state. It will be idle and increase the power loss of the power supply device.

Contents of the invention

In view of the above, it is necessary to provide a power supply device with high power supply efficiency.

A power supply device, used to supply power to the power receiving end, the power supply device includes a step-down circuit, a power supply unit (power supply unit, PSU), a buffer circuit and a logic circuit connected to the PSU and the buffer circuit, and the PSU is used To supply direct current to the step-down circuit, the step-down circuit converts the voltage of the direct current into a preset voltage and supplies it to the power receiving terminal, and the buffer circuit is connected to the step-down circuit to prevent the step-down circuit from When it is damaged when working under the heavy-duty power supply state, the buffer circuit is selectively connected to the step-down circuit through the logic circuit, and the PSU detects whether the step-down circuit is in the heavy-load state, and triggers the logic when the step-down circuit is in the heavy-load state The circuit connects the buffer circuit to the step-down circuit; when the corresponding step-down circuit is in a light-load state, the PSU triggers the logic circuit to disconnect the connection between the buffer circuit and the step-down circuit, so as to eliminate the loss generated by the buffer circuit.

When the step-down circuit is under heavy load and may be damaged, the power supply device controls the buffer circuit to be connected to the step-down circuit to effectively protect the step-down circuit; and when the step-down circuit is under light load, it will not When the buffer circuit is damaged for protection, the power supply device disconnects the buffer circuit from the step-down circuit, so as to eliminate the power loss generated by the buffer circuit, so that the power supply device has higher power supply efficiency.

Description of drawings

Fig. 1 is a schematic circuit diagram of a power supply device of the present invention supplying power to a power receiving terminal.

Description of main component symbols

power supply unit 100 Buck circuit 10 controller 11 first switch Q1 second switch Q2 output inductance L Energy storage capacitor C1 PSUs 30 snubber circuit 50 resistance R Snubber capacitance C2 logic circuit 70 logic module 71 logic switch 73 Receiver 200

The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

Detailed ways

Below in conjunction with accompanying drawing and preferred embodiment the present invention is described in further detail:

Please refer to FIG. 1 , the power supply device 100 of the present invention is used to supply power to a power receiving terminal 200 such as a server system. The power supply device 100 includes a step-down circuit 10, a power supply unit (power supply unit, PSU) 30, a buffer circuit 50 and a logic circuit 70, the PSU30 is connected to the step-down circuit 10 and the logic circuit 70, and the logic circuit 70 also Connected to the buffer circuit 50 for controlling the electrical connection between the buffer circuit 50 and the step-down circuit 10 . The PSU 30 is used to provide DC power to the step-down circuit 10 and detect the current value output from the PSU 30 to the step-down circuit 10 . When the PSU30 detects that the output current value is relatively high, it judges that the step-down circuit 10 is in a heavy load state, and then triggers the logic circuit 70 to connect the buffer circuit 50 to the step-down circuit 10 to protect the step-down circuit 10; When the PSU 30 detects that the output current value is small and judges that the step-down circuit 10 is in a light-load state and there is no need to protect the step-down circuit 10, it triggers the logic circuit 70 to disconnect the buffer circuit 50 from the step-down circuit. The connection of the circuit 10 eliminates the power loss generated by the snubber circuit 50.

The buck circuit 10 includes a controller 11 , a first switch Q1 , a second switch Q2 , an output inductor L and an energy storage capacitor C1 .

The controller 11 is connected to the first switch Q1 and the second switch Q2, and is used to sequentially control the first switch Q1 and the second switch Q2 to turn on/off according to the voltage value output from the step-down circuit 10 to the power receiving terminal 200 disconnect. In the embodiment of the present invention, the controller 11 is a pulse width modulation chip, and adjusts the first switch Q1 and the second switch Q2 through the duty cycle of the pulse width modulation signal sent to the first switch Q1 and the second switch Q2. The conduction time of the second switch Q2 is adjusted correspondingly to the magnitude of the voltage output by the step-down circuit 10 .

The first switch Q1 and the second switch Q2 are sequentially connected in series between the PSU30 and the ground. After the output inductor L and the energy storage capacitor C1 are connected in series, the other end of the energy storage capacitor C1 is connected to the first switch Q1 and the ground. Between the second switches Q2, the other end of the output inductor L is grounded. The power receiving end 200 is connected in parallel to two opposite ends of the energy storage capacitor C1. In this way, when the controller 11 turns on the first switch Q1 and turns off the second switch Q2, the power connected to the PSU30 terminal will be supplied from the first switch Q1 and the output inductor L to the power receiving terminal 200 and the energy storage capacitor C1 , so as to store power through the energy storage capacitor C1 while supplying power to the power receiving terminal 200; when the controller 11 turns off the first switch Q1 and turns on the second switch Q2, the PSU30 stops supplying power to the step-down circuit 10 , and the stored energy is released by the energy storage capacitor C1 to supply power to the receiving terminal 200 . In the embodiment of the present invention, both the first switch Q1 and the second switch Q2 are field effect transistors, and the first switch Q1 is connected to the controller 11 through the gate, connected to the PSU30 through the drain, and connected to the PSU30 through the drain. The source is connected to the second switch Q2; the second switch Q2 is connected to the source of the first switch Q1 through the drain, connected to the controller through the gate, and grounded through the source.

The PSU 30 is connected to the first switch Q1 of the step-down circuit 10 and the logic circuit 70 for supplying DC power to the step-down circuit 10 and detecting whether the step-down circuit 10 is in a heavy load state or a light load state. When the PSU30 detects that the step-down circuit 10 is in a heavy-load state, the trigger logic circuit 70 connects the buffer circuit 50 to the second switch Q2 in parallel; when it detects that the step-down circuit 10 is in a light-load state, triggers the The logic circuit 70 disconnects the buffer circuit 50 from the second switch Q2. In the embodiment of the present invention, the PSU30 sets a reference current value corresponding to the current value output to the step-down circuit 10, and detects the current value output by the PSU30 to the step-down circuit 10, if the output current value exceeds the predetermined If the reference current value is set, it is determined that the step-down circuit 10 is in a heavy load state; if the current value output by the PSU30 to the step-down circuit 10 is lower than the preset reference current value, it is determined that the step-down circuit 10 is in a light load state. In the embodiment of the present invention, the PSU 30 establishes communication with the logic circuit 70 through the SDA and SCL signal lines in the System Management Bus (Smbus), thereby triggering the logic circuit 70 to control the buffer circuit 50 and the step-down Circuit 10 connections.

The buffer circuit 50 includes a resistor R and a buffer capacitor C2 , one end of the series connection of the resistor R and the buffer capacitor C2 is connected between the second switch Q2 and the output inductor L, and the other end is grounded through the logic circuit 70 . In this way, when the logic circuit 70 connects the buffer circuit 50 to the ground, the buffer circuit 50 is connected in parallel to the second switch Q2, and when the logic circuit 70 disconnects the buffer circuit 50 from the ground, the buffer circuit 50 will disconnect the electrical connection with the step-down circuit 10 .

The logic circuit 70 includes a logic module 71 and a logic switch 73 . The logic module 71 is electrically connected to the PSU 30 and connected to a logic switch 73 , one end of the logic switch 73 is also connected to the buffer capacitor C2 , and the other end is grounded. The logic module 71 controls the conduction or disconnection of the logic switch 73 under the trigger of the PSU30, and correspondingly connects one end of the buffer circuit 50 to the ground or disconnects the connection with the ground, and correspondingly realizes connecting the buffer circuit 50 to the ground. to the second switch Q2 or disconnect both. In the embodiment of the present invention, the logic switch 73 is also a field effect transistor, and the logic module 71 sends a high level signal to the logic switch 73 under the control of the PSU 30 to turn on the logic switch 73 .

In the process of using the power supply device 100 to supply power to the power receiving terminal 200, the PSU 30 provides a DC power supply to the step-down circuit 10, and then the controller 11 outputs a pulse width modulation signal with a certain duty cycle to control the first switch The conduction duration of Q1 and the second switch Q2 enables the power supply device 100 to keep outputting a predetermined voltage to the power receiving terminal 200 . During this process, the PSU 30 detects the current output to the step-down circuit 10 , and determines whether the output current exceeds a preset reference current. When the current output by the PSU30 to the step-down circuit 10 exceeds the preset reference current, it is determined that the step-down circuit 10 is in a heavy load state, and then the logic module 71 is triggered to turn on the logic switch 73, so that the buffer circuit 50 One end is grounded and connected in parallel to the second switch Q2 to prevent the second switch Q2 from being damaged due to the sudden increase of the voltage supplied by the PSU 30 when the voltage on the second switch Q2 is turned off. When the current output by the PSU30 to the step-down circuit 10 is lower than the preset reference current, it is determined that the step-down circuit 10 is in a light-load state, and then the logic module 71 is triggered to disconnect the logic switch 73 to disconnect the buffer circuit 50 is connected to the second switch Q2, thereby eliminating the power loss caused by the snubber circuit 50.

The power supply device 100 of the present invention controls the buffer circuit 50 to be connected to the second switch Q2 in the step-down circuit 10 when the step-down circuit 10 is in a heavy load state, so as to prevent the second switch Q2 from switching from on to off. The momentary voltage in the open state is too large and burns out, effectively protecting the step-down circuit 10; when the step-down circuit 10 is in a light-load state, the second switch Q2 will not be damaged due to the excessive voltage when it is just turned off. When the buffer circuit 50 is not needed to provide protection, the power supply device 100 disconnects the buffer circuit 50 from the step-down circuit 10 to eliminate the power loss generated by the buffer circuit 50 and make the power supply device 100 more efficient in power supply.

For those skilled in the art, other corresponding changes or adjustments can be made according to the inventive solution and inventive concept of the present invention combined with the actual needs of production, and these changes and adjustments should all belong to the protection scope of the claims of the present invention.

Claims (7)

1. supply unit, in order to receiving end is powered, this supply unit comprises reduction voltage circuit, power-supply unit (power supply unit, PSU) and buffer circuit, described PSU is in order to supply direct current to described reduction voltage circuit, this reduction voltage circuit becomes a default voltage to be supplied to receiving end described galvanic voltage transitions, described buffer circuit is connected to reduction voltage circuit, impaired in order to prevent that described reduction voltage circuit is in when working under the heavily loaded power supply state, it is characterized in that: this supply unit comprises that also one is connected to the logical circuit of PSU and buffer circuit, described buffer circuit optionally is connected to reduction voltage circuit by logical circuit, described PSU detects reduction voltage circuit and whether is in heavy condition, and corresponding reduction voltage circuit triggers logical circuit when being in heavy condition buffer circuit is connected to reduction voltage circuit; When corresponding reduction voltage circuit was in light condition, this PSU triggering logical circuit disconnection buffer circuit was connected with reduction voltage circuit.

2. supply unit as claimed in claim 1, it is characterized in that: described PSU correspondence exports the default reference current of galvanic electric current of reduction voltage circuit to, and detect the electric current that this PSU exports reduction voltage circuit to and whether exceed described default reference current, if the electric current of described output exceeds default reference current and judges that then described reduction voltage circuit is in heavy condition, if being lower than default reference current, the electric current of described output judges that then described reduction voltage circuit is in light condition.

3. supply unit as claimed in claim 1, it is characterized in that: described logical circuit comprises logic module and the logic switch that is serially connected with successively between PSU and the ground, described logical circuit is connected to buffer circuit by logic switch, described PSU is by conducting or the disconnection of logic module control logic switch, corresponding described buffer circuit is connected to reduction voltage circuit, perhaps disconnects being connected of described buffer circuit and reduction voltage circuit.

4. supply unit as claimed in claim 3, it is characterized in that: described logic switch is a field effect transistor.

5. supply unit as claimed in claim 3 is characterized in that: described PSU sets up and the communicating by letter of described logic module by the SDA in system's control bus and SCL holding wire.

6. supply unit as claimed in claim 3, it is characterized in that: described buffer circuit comprises a resistance and electric capacity, described buffer circuit is connected to logic switch by electric capacity, and is connected between first switch and the second switch by resistance.

7. supply unit as claimed in claim 1, it is characterized in that: described reduction voltage circuit comprises controller, first switch, second switch, outputting inductance and storage capacitor, described first switch and second switch are serially connected with between PSU and the ground mutually, end after described outputting inductance and the storage capacitor serial connection is connected between first switch and the second switch, other end ground connection, described receiving end is connected in parallel to the opposite end of storage capacitor, described controller is controlled the default duration of first switch and second switch conducting one respectively, convert described default voltage to the power source voltage that PSU is provided and be supplied to receiving end, one end of described buffer circuit is connected between first switch and the second switch, the other end is by logical circuit ground connection, be connected in parallel to second switch with ground connection under the control of logical circuit, perhaps under the control of logical circuit, disconnect and disconnect being connected of this buffer circuit and reduction voltage circuit with being connected of ground.