CN109857243B - System-on-chip, universal serial bus master device, system and awakening method - Google Patents

System-on-chip, universal serial bus master device, system and awakening method Download PDF

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Publication number
CN109857243B
CN109857243B CN201711212992.4A CN201711212992A CN109857243B CN 109857243 B CN109857243 B CN 109857243B CN 201711212992 A CN201711212992 A CN 201711212992A CN 109857243 B CN109857243 B CN 109857243B
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usb
soc
bus
power consumption
low power
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CN109857243A (en
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钱进
任博
刘宇
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN201711212992.4A priority Critical patent/CN109857243B/en
Priority to PCT/CN2018/086309 priority patent/WO2019104947A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The embodiment of the invention provides a system-level chip, universal serial bus master equipment, a system and a wake-up method. The system-on-chip SOC comprises a system awakening control module, a processor CPU, a USB controller and a universal serial bus physical layer module USB PHY. After the SOC receives an instruction for indicating to enter a low power consumption state, the CPU, the USB controller and the USB PHY are powered off through the system awakening control module; and after the SOC receives an instruction for indicating to exit the low power consumption state, powering on the CPU, the USB controller and the USB PHY. And when the USB controller and the USB PHY are in a power-off state in the low power consumption state, the power consumption of the USB main equipment can be reduced. When an instruction for indicating to exit from the low-power-consumption state is received, the CPU, the USB controller and the USB PHY are powered on, so that the normal operation of data communication is ensured while the power consumption is reduced, and the user experience is improved.

Description

System-on-chip, universal serial bus master device, system and awakening method
Technical Field
The invention relates to the field of electronic communication, in particular to a system-level chip, universal serial bus master equipment, a system and a wake-up method.
Background
The Universal Serial Bus (USB) 2.0 protocol specifies that the USB 2.0 Bus contains two data lines, D +, D-and enters a low power consumption state when idle. After entering the low power consumption state, either the USB master device or the USB slave device may initiate a recovery. When the system enters a low power consumption state, the system can monitor the change of the Bus level through a Universal Serial Bus Physical Layer (USB PHY) module and a USB controller, and once a wake-up signal appears, the system immediately enters a flow of recovering data communication. In the process of low power consumption, the USB controller and the USB PHY part circuit are always powered on, and thus may consume power continuously, resulting in large power consumption of the USB host device.
Disclosure of Invention
The embodiment of the invention provides a system-level chip, universal serial bus master equipment, a system and a wake-up method, which can power down a USB PHY and a USB controller when a bus enters a low-power-consumption state, and save power consumption.
In a first aspect, an embodiment of the present invention provides a system-on-chip SOC, including: the system comprises a system awakening control module, a processor CPU, a USB controller and a universal serial bus physical layer module USB PHY; wherein:
the system wake-up control module is used for powering down the CPU, the USB controller and the USB PHY after the SOC receives an instruction for indicating to enter a low power consumption state;
the system wake-up control module is further configured to power on the CPU, the USB controller, and the USB PHY after the SOC receives an instruction to instruct to exit the low power consumption state.
According to the embodiment of the invention, after the SOC receives the state of entering the low power consumption state, the CPU, the USB controller and the USB PHY are powered off, so that the power consumption is saved.
With reference to the first aspect, in a first implementation manner of the first aspect, the SOC is further configured to maintain, by a bus hold circuit, a level of a target bus after the SOC receives an instruction to instruct entry into a low power consumption state; the bus holding circuit comprises a system wake-up controller or a pull-down resistor, and the target bus is a bus between the SOC and the USB slave device.
According to the embodiment of the invention, the bus level is kept unchanged after the bus enters the low power consumption state through the bus holding circuit, so that the USB controller and the USB PHY can be powered off.
With reference to the first implementation manner of the first aspect, in a second implementation manner of the first aspect, the receiving, by the SOC, an instruction to enter a low power consumption state includes: the SOC detects that the level of the target bus does not change within a preset time period.
The embodiment of the invention provides a judgment condition for entering a low power consumption state, and the low power consumption state is entered in time when the condition for entering the low power consumption state is met, so that the power consumption is saved.
With reference to the first implementation manner of the first aspect, in a third implementation manner of the first aspect, the receiving, by the SOC, an instruction to enter a low power consumption state includes: the SOC receives a data packet sent by the USB slave equipment; the data packet is a response data packet of a link Layer Power Management (LPM) data packet sent by the SOC to the USB slave device, or the data packet is an LPM data packet sent by the USB slave device to the SOC.
The embodiment of the invention provides another judgment condition for entering the low-power-consumption state, and the low-power-consumption state is entered in time when the condition for entering the low-power-consumption state is met, so that the power consumption is saved.
With reference to the second or third implementation manner of the first aspect, in a fourth implementation manner of the first aspect, the receiving, by the SOC, the instruction to exit the low power consumption state includes: and the SOC detects that the target bus level changes through the system awakening control module.
The embodiment of the invention provides a judgment condition for exiting from the low power consumption state, and when data needs to be transmitted, the low power consumption state is exited in time without influencing the use of a user.
With reference to the second or third implementation manner of the first aspect, in a fifth implementation manner of the first aspect, the SOC is further configured to turn off the bus holding circuit after the system wake-up control module wakes up the CPU, the USB controller, and the USB PHY.
The embodiment of the invention cancels the bus holding circuit in time after recovering the data communication, ensures the normal operation of the data communication and does not influence the use of users.
In a second aspect, an embodiment of the present invention provides a USB host device, including: a system-on-chip SOC and bus hold circuit; the SOC is provided in the first aspect of the embodiments of the present invention or any implementation manner of the first aspect.
In a third aspect, an embodiment of the present invention provides a universal serial bus USB system, including: a USB master device and a USB slave device; wherein the USB master device comprises a System On Chip (SOC) and a bus holding circuit;
the SOC is provided in the first aspect of the embodiments of the present invention or any implementation manner of the first aspect.
In a fourth aspect, an embodiment of the present invention provides a USB wakeup method, including:
if the SOC receives an instruction for indicating to enter a low power consumption state, the SOC powers down a CPU (central processing unit), a USB (universal serial bus) controller and a USB PHY (universal serial bus) of a USB physical layer module;
and if the SOC receives an instruction for indicating to exit the low power consumption state, the SOC powers on the CPU, the USB controller and the USB PHY.
With reference to the fourth aspect, in a first implementation manner of the fourth aspect, after the system on chip SOC receives the instruction for instructing to enter the low power consumption state, the method further includes:
the SOC maintains the level of a target bus through the bus maintaining circuit, wherein the target bus is a bus between the SOC and a USB slave device;
if the SOC receives an instruction for instructing to exit the low power consumption state, the SOC powers up the CPU, the USB controller, and the USB PHY, including:
and if the target bus level changes, powering on the CPU, the USB controller and the USB PHY.
With reference to the first implementation manner of the fourth aspect, in a second implementation manner of the fourth aspect, the powering on the CPU, the USB controller, and the USB PHY if the target bus level changes includes:
detecting the level of the target bus through a system wake-up control module;
and if the target bus level changes, the CPU, the USB controller and the USB PHY are electrified through the system awakening control module.
With reference to the fourth aspect or any one implementation manner of the first to the second aspects, in a third implementation manner of the fourth aspect, if the receiving, by the system on chip SOC, the instruction for instructing to enter the low power consumption state includes: and if the SOC detects that the level of the target bus is not changed within a preset time period.
With reference to the fourth aspect or any one implementation manner of the first to the second aspects of the fourth aspect, in a fourth implementation manner of the fourth aspect, if the receiving, by the system on chip SOC, the instruction for instructing to enter the low power consumption state includes: if the system-level chip receives a data packet sent by the USB slave equipment; the data packet is a response data packet of a link Layer Power Management (LPM) data packet sent by the SOC to the USB slave device, or the data packet is an LPM data packet sent by the USB slave device to the SOC.
With reference to the third or fourth implementation manner of the fourth aspect, in a fifth implementation manner of the fourth aspect, after the SOC powers on the CPU, the USB controller, and the USB PHY, the method further includes:
the SOC turns off the bus hold circuit.
With reference to the first implementation manner of the fourth aspect, in a sixth implementation manner of the fourth aspect, the bus holding circuit includes a bus holder or a pull-down resistor.
It can be seen that, in the embodiment of the present invention, after the SOC receives the instruction for instructing to enter the low power consumption state, the system wake-up control module controls the CPU, the USB controller, and the USB PHY to be powered off; and after the SOC receives an instruction for indicating to exit the low power consumption state, powering on the CPU, the USB controller and the USB PHY. And when the USB controller and the USB PHY are in a power-off state in the low power consumption state, the power consumption of the USB main equipment can be reduced. When an instruction for indicating to quit the low-power-consumption state is received, the CPU, the USB controller and the USB PHY are powered on in time, normal operation of data communication is guaranteed while power consumption is reduced, and user experience is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
FIG. 1 is a diagram of a USB system according to the prior art;
FIG. 2 is a schematic diagram of a prior art SOC architecture;
fig. 3 is a schematic diagram of an SOC structure according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a USB host device according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a USB system according to an embodiment of the present invention;
fig. 6 is a flowchart illustrating a USB wake-up method according to an embodiment of the present invention.
Detailed Description
The technical solutions in the prior art or the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.
First, a USB system structure and an SOC structure in the prior art are described with reference to fig. 1-2, where fig. 1 is a schematic diagram of a USB system structure in the prior art, and fig. 2 is a schematic diagram of an SOC structure in the prior art.
Please refer to fig. 1. As shown in fig. 1, the USB system in the prior art includes a USB master device 10, a USB slave device 20, and a USB connection line 30, wherein the USB master device 10 and the USB slave device 20 can be connected via the USB connection line 30 for data transmission. For example, the USB host 10 is a computer host, the USB slave 20 is a mobile phone, the USB connection line 30 is a data line, and the computer host and the mobile phone can perform data transmission through the data line. Alternatively, in a USB system of the prior art, the USB slave device 20 may include a USB connection line 30. For example, the USB host 10 is a computer host, the USB slave 20 is a wired mouse, and the computer host and the wired mouse can directly perform data transmission. Alternatively, a USB system in the prior art may only include the USB master device 10 and the USB slave device 20, and the USB slave device 20 may be directly connected to the USB master device 10 for data transmission. For example, the USB host device 10 is a computer host, the USB slave device 20 is a USB flash disk, and the USB flash disk can be directly plugged into the computer host for data transmission.
The USB master device 10 may be a USB host capable of connecting with the USB slave device 20, and when the USB host is connected with the USB slave device 20, data transmission may be performed with the USB slave device 20. The USB host device 10 may also be a USB On-The-go (OTG) device, and according to different application scenarios, The host and slave identities of The OTG device may be converted, that is, The OTG device may be used as both The USB host device 10 and The USB slave device 20. For example, the OTG device may be a digital camera. When the digital camera is connected to a computer host and uploads photos to the computer, the digital camera plays the role of the identity of the USB slave device. If the digital camera is directly connected with the printer, the photos in the digital camera are printed out, and the digital camera plays the role of the identity of the USB host device. The USB OTG device in the embodiment of the present invention is used to implement the function of a USB host, and may be connected to other USB slave devices 20 to perform data transmission with the USB slave devices 20.
As can be seen from fig. 1, the USB host device 10 may include at least: a System On Chip (SOC) 110, a data bus (D +, D-)120, and a USB interface 130. The data bus 120 is used to connect the SOC110 and the USB interface 130. The USB interface 130 is used to provide a connection interface for the USB master device 10 and the USB slave device 20. After the USB slave device 20 and the USB master device 10 are connected through the USB connection line 30, the SOC110 performs data transmission with the USB slave device 20 through the data bus 120.
Specifically, the SOC110 structure is shown in fig. 2. As shown in fig. 2, the SOC110 may include at least a system wake-up control module 1110, a Central Processing Unit (CPU) 1120, a USB controller 1130, and a USB PHY 1140.
The CPU1120 is configured to generate a corresponding control signal according to the received instruction, and control the corresponding component to perform an action according to a specified requirement.
The USB controller 1130 is used to provide USB control functions, which together with the USB PHY1140 perform data transfer functions.
USB PHY1140 is used for data transfer with USB slave device 20 via data bus 120. USB PHY1140 may also be used to maintain the level of data bus 120 in a low power state to prevent the system from exiting the low power state due to a bus level change caused by a false trigger signal.
It is understood that the low power consumption state is a state in which the USB host device is operating with lower power consumption than when data communication is in progress, and the low power consumption state in the prior art may be that the USB host device is in a suspend state, i.e. the USB host device is in a low power consumption state due to the absence of data bus activity for a period of time, which is specified in the prior USB protocol to be 3 ms. The low Power consumption state in the prior art may also be that the USB master device is in a dormant state, that is, the USB master device or the USB slave device transmits a Link Power Management (LPM) packet to the other side, so that the USB master device is in a state with low Power consumption.
The USB controller 1130 and USB PHY1140 may also be used to detect bus level changes during low power states to ensure that a wake-up signal is detected. It is understood that the bus level change may be triggered by USB slave device 20, and when USB slave device 20 needs to perform data transmission, the bus level change may be caused. In this case, since the amplitude of the bus level change triggered by the USB slave device 20 is much larger than the amplitude of the bus level change triggered by the false trigger signal, the USB PHY1140 cannot maintain the bus level and the CPU is woken up. Therefore, the USB PHY1140 may prevent the bus level from varying due to false trigger signals by maintaining the bus level in a low power state.
The system wake control module 1110 is used to manage the operating mode of the SOC 110. Specifically, when receiving an instruction for instructing to exit the low power consumption state, the system wake-up control module 1110 may send a wake-up signal to wake up the CPU1110, and further wake up the USB controller 1130 and the USB PHY1140 through the CPU1110, that is, power up the CPU1110, the USB controller 1130, and the USB PHY1140, so that the USB system resumes data communication.
In a specific implementation, the system wake-up control module 1110 may be a processor or a logic control circuit, and is configured to implement the above-mentioned functions. It can be known that the system wake-up control module 1110 may also have other existing forms, and no matter what state the system is in, the system wake-up control module 1110 is always in the power-on state, and the system wake-up function may be implemented, which is not limited herein.
Further, it can be seen from fig. 2 that the SOC110 can be divided into a power-down region and a power-off region. The CPU1120 is located in a power-down region, and the system wake-up control module 1110, the USB controller 1130, and the USB PHY1140 are located in a non-power-down region. For the division of the power-down region and the power-off-free region, it is only necessary to configure the working logic of each region after dividing the SOC110 when designing it. And after the system enters a low power consumption state, the power supply of the power-off area is turned off so as to save the power consumption of the system. A non-powered down region is a region that remains powered up in any state of the system. That is, in the prior art, after the system enters the low power consumption state, the CPU1120 turns off the power supply to save the power consumption of the system, and the system wake-up control module 1110, the USB controller 1130, and the USB PHY1140 remain powered on.
In the present invention, the CPU1120, the USB controller 1130, and the USB PHY1140 are located in a power-down region, and the system wake-up control module 1110 is located in a non-power-down region. After the system enters the low power consumption state, the CPU1120, the USB controller 1130, and the USB PHY1140 may all be powered down, and only the system control module 1110 located in the non-powered down region remains powered up, which reduces the power consumption of the system in the low power consumption state compared to the prior art.
The SOC, the USB host device and the USB system provided in the embodiments of the present invention are described below with reference to fig. 3 to 5. Fig. 3 is a schematic structural diagram of an SOC according to an embodiment of the present invention, fig. 4 is a schematic structural diagram of a USB host according to an embodiment of the present invention, and fig. 5 is a schematic structural diagram of a USB system according to an embodiment of the present invention.
Please refer to fig. 3. As shown in fig. 3, SOC110 may include at least: system wake-up control module 1110, CPU1120, USB controller 1130, and USB PHY 1140. As can be seen from the figure, the SOC110 is divided into a power-down region and a power-off region. The CPU1120, the USB controller 1130, and the USB PHY1140 are in a power-down region, and the system wake-up control module 1110 is in a power-off region.
The CPU1120 is configured to generate a corresponding control signal according to the received instruction, and control the corresponding component to perform an action according to a specified requirement.
The USB controller 1130 is used to provide USB control functions, which together with the USB PHY1140 perform data transfer functions.
USB PHY1140 is used for data transfer with USB slave device 20.
The system wake control module 1110 is used to manage the operating mode of the SOC 110. Specifically, after the SOC110 receives an instruction for instructing entry into the low power consumption state, the CPU1120, the USB controller 1130, and the USB PHY1140 are powered down; the system wake control module 1110 is further configured to power up the CPU1120, the USB controller 1130, and the USB PHY1140 after the SOC110 receives an instruction indicating to exit the low power consumption state.
After the system enters the low power consumption state, since the USB controller 1130 and the USB PHY1140 are powered down and cannot detect the change of the bus level, and the USB PHY1140 cannot maintain the bus level to prevent the bus level from changing due to a false trigger signal, so that the system exits the low power consumption state, in this embodiment of the present invention, the SOC110 is further configured to maintain the level of the target bus through the bus maintenance circuit 140 after the SOC110 receives the instruction for instructing to enter the low power consumption state; the bus holding circuit 140 includes a bus holder or a pull-down resistor, and the target bus is the data bus (D +, D-)120 between the SOC and the USB slave device. It should be appreciated that the bus holding circuit 140 is not limited to the above-listed components, and other components for holding the target bus level may be used in practice, and is not limited herein.
Specifically, the bus hold circuit 140 is arranged in the following manner:
in one possible implementation, the bus hold circuit 140 is located between the SOC110 and the USB interface 130, and is connected to a pin b on the unpowered region in the SOC110, and the pin b may be controlled by the CPU 1120. When the SOC110 receives an instruction for instructing entry to the low power consumption state, the CPU1120 may control the bus holding circuit 140 to operate, maintain the target bus level, and power down the power down region. When the SOC110 receives an instruction for instructing to exit the low power consumption state, the system wake-up control module 1110 wakes up the CPU1120, the USB controller 1130, and the USB PHY1140, so that the CPU1120 controls the bus hold circuit 140 to stop operating after powering on. And restoring the USB system to normal data communication.
In another possible implementation manner, the bus holding circuit 140 may also be directly disposed in a non-power-down region of the SOC110, and the CPU1120 controls the bus holding circuit to operate and shut down.
Specifically, the ways in which the SOC110 receives the instruction to enter the low power consumption state include, but are not limited to, the following:
optionally, the receiving, by the SOC110, the instruction for instructing to enter the low power consumption state includes: the SOC110 detects that the level of the target bus 120 has not changed within a preset time period. Wherein a change in bus level may be detected by USB PHY 1140. The preset time period may be, for example, 3ms, 5ms, 10ms, or the like. The change in bus level may be a reversal in the level of the two data buses D +, D-. For example, when entering the low power consumption state, the level of D + is high, and the level of D-is low, then when exiting the low power consumption state, the level of D + should be inverted to low, and the level of D-should be inverted to high.
Optionally, the receiving, by the SOC110, the instruction for instructing to enter the low power consumption state includes: the SOC110 receives a data packet transmitted from the USB slave device 20; the data packet is a response data packet fed back by the USB slave device 20 after the SOC110 sends the LPM data packet to the USB slave device 20, or the data packet is an LPM data packet sent by the USB slave device 20 to the SOC 110.
Receiving the instruction by SOC110 to exit the low power consumption state includes: the SOC110 detects a change in the level of the target bus 120 through the system wake-up control module 1110. Wherein the level change comprises a level flip.
Specifically, the wake-up control module 1110 is connected to at least one of the target buses 120(D +, D-) through the pin a, and it is detected that the level value thereof is inverted, that is, an instruction for instructing to exit the low power consumption state is received. Specifically, the system wake-up control module 1110 is connected to at least one of the target buses 120(D +, D-) through at least one wire led out from the pin a to detect the level change of the target bus 120. For example, a lead may be led out through pin a to connect with D +, a lead may also be led out through pin a to connect with D-, or two leads may also be led out through pin a to connect with D + and D-, respectively. Since the system wake-up control module 1110 is in the non-power-down region, the system control module 1110 can still detect the level change of the target bus 120 even after the system enters the low power consumption state. The flipping of the target bus 120 level value may be triggered by USB slave device 20, and USB slave device 20 may cause the target bus 120 level to change when USB slave device 20 needs to send data to SOC 110. In this case, the bus hold circuit 140 cannot hold the target bus 120 level unchanged. The amplitude of the level change of the target bus 120 triggered by the USB slave device 20 is much larger than the amplitude of the level change of the target bus 120 triggered by the false trigger signal. Therefore, the bus hold circuit 140 holds the target bus 120 level in the low power consumption state to avoid the change of the target bus 120 level caused by the false trigger signal.
According to the embodiment of the invention, after the system enters the low power consumption state, the bus level is detected through the system awakening control module, the bus level is maintained through the bus holding circuit, and the work of the USB controller and the USB PHY in the low power consumption state is replaced, so that when the system enters the low power consumption state, the USB controller and the USB PHY can be powered down, and the electric energy consumption of the system in the low power consumption state is saved.
The embodiment of the invention provides USB master equipment. As shown in fig. 4, the USB host device 10 may include at least an SOC110, a target bus 120, a USB interface 130, and a bus hold circuit 140. Among them, the SOC110 may include at least: system wake-up control module 1110, CPU1120, USB controller 1130, and USB PHY 1140. As can be seen from the figure, the SOC110 is divided into a power-down region and a power-off region. The CPU1120, the USB controller 1130, and the USB PHY1140 are in a power-down region, and the system wake-up control module 1110 is in a power-off region. The target bus 120 is connected to the USB PHY1140 in the SOC110 for completing data communication with USB slave devices. The USB interface 130 is used to provide a connection interface for the USB master device 10 and the USB slave device 20. The bus holding circuit 140 is connected to the non-power-down region in the SOC110, and is configured to keep the level of the target bus 120 unchanged after the system enters the low power consumption state, and at this time, the CPU1120, the USB controller 1130, and the USB PHY1140 may be powered down completely, so as to save power consumption of the system.
Specifically, the structure and the operation principle of the SOC110 in the embodiment of the present invention may refer to the SOC described in the embodiment of fig. 3.
The embodiment of the invention provides a USB system. As shown in fig. 5, the USB system may include a USB master device 10, a USB slave device 20, and a USB connection line 30, wherein the USB master device 10 and the USB slave device 20 may be connected via the USB connection line 30 for data transmission. For example, the USB host 10 is a computer host, the USB slave 20 is a mobile phone, the USB connection line 30 is a data line, and the computer host and the mobile phone can perform data transmission through the data line. Alternatively, the USB slave device 20 in the USB system provided by the embodiment of the present invention may include the USB connection line 30. For example, the USB host 10 is a computer host, the USB slave 20 is a wired mouse, and the computer host and the wired mouse can directly perform data transmission. Or, the USB system provided in the embodiment of the present invention may include only the USB master device 10 and the USB slave device 20, and the USB slave device 20 may be directly connected to the USB master device 10 for data transmission. For example, the USB host device 10 is a computer host, the USB slave device 20 is a USB flash disk, and the USB flash disk can be directly plugged into the computer host for data transmission.
The USB master device 10 may be a USB host capable of connecting with the USB slave device 20, and when the USB host is connected with the USB slave device 20, data transmission may be performed with the USB slave device 20. The USB master device 10 may also be a USB OTG device that may act as both a USB host and a USB slave device 20. The USB OTG device in the embodiment of the present invention is used to implement the function of a USB host, and may be connected to other USB slave devices 20 to perform data transmission with the USB slave devices 20.
Specifically, USB host 10 may include at least SOC110, data bus (D +, D-)120, USB interface 130, and bus hold circuit 140. The data bus 120 is used to connect the SOC110 and the USB interface 130. The USB interface 130 is used to provide a connection interface for the USB master device 10 and the USB slave device 20. After the USB slave device 20 and the USB master device 10 are connected through the USB connection line 30, the SOC110 performs data transmission with the USB slave device 20 through the data bus 120. When the system enters a low power consumption state, the SOC110 maintains the level of the data bus 120 through the bus hold circuit 140, while the SOC110 detects a change in the level of the data bus 120 through the system wake-up control module 1110. The structure and operation principle of the SOC110 in the embodiment of the present invention can refer to the SOC described in the embodiment of fig. 3.
The embodiment of the invention also correspondingly provides a USB awakening method. As shown in fig. 6, the USB wakeup method may include at least the following steps:
s401: if the SOC receives an instruction for instructing entry into a low power state, the SOC powers down the CPU, the USB controller, and the USB PHY.
Specifically, the ways in which the SOC110 receives the instruction to enter the low power consumption state include, but are not limited to, the following:
optionally, the receiving, by the SOC110, the instruction for instructing to enter the low power consumption state includes: the SOC detects that the level of the target bus (i.e., the data bus 120) has not changed for a preset period of time. Wherein a change in the target bus level may be detected by USB PHY 1140. The preset time period may be, for example, but not limited to, 3ms, 5ms, 10ms, etc. The change in the level of the target bus 120 may be a reversal in the level of the two data buses D +, D-. For example, when entering the low power consumption state, the level of D + is high, and the level of D-is low, then when exiting the low power consumption state, the level of D + should be inverted to low, and the level of D-should be inverted to high.
Optionally, the receiving, by the SOC110, the instruction for instructing to enter the low power consumption state includes: the SOC110 receives a data packet transmitted from the USB slave device 20; the data packet is a response data packet sent by SOC110 to USB slave device 20, or the data packet is an LPM data packet sent by USB slave device 20 to SOC 110.
Specifically, after the SOC110 receives the instruction for instructing to enter the low power consumption state, the method further includes:
s402: the SOC holds the level of the target bus line by a bus holding circuit.
The bus hold circuit 140 includes a bus keeper or a pull-down resistor, among other things.
Specifically, the bus holding circuit is arranged in the following ways:
in one possible implementation, the bus hold circuit 140 is located between the SOC110 and the USB interface 130, connected to the non-power-down region in the SOC110, and may be controlled by the CPU 1120. When the SOC110 receives an instruction for instructing entry to the low power consumption state, the CPU1120 may control the bus holding circuit 140 to operate, maintain the level of the target bus 120, and power down the power down region.
In another possible implementation manner, the bus holding circuit 140 may also be directly disposed in a non-power-down region in the SOC110, and the CPU1120 controls the bus holding circuit 140 to operate and shut down.
S403: if the SOC receives an instruction for instructing to exit the low power consumption state, the SOC powers on the CPU, the USB controller and the USB PHY.
Specifically, the SOC110 receiving the instruction to instruct exit from the low power consumption state includes: the SOC110 detects a change in the level of the target bus 120 through the system wake-up control module 1110. Wherein the level change comprises a level flip.
When the SOC110 receives an instruction indicating to exit the low power consumption state, the system wake-up control module 1110 wakes up the CPU1120, the USB controller 1130, and the USB PHY1140, so that the CPU1120 controls the bus holding circuit 140 to stop working, that is, turns off the bus holding circuit 140, and the USB system resumes normal data communication.
Specifically, the wake-up control module 1110 is connected to at least one of the target buses 120, and detecting that the level value thereof is inverted is to receive an instruction for instructing to exit the low power consumption state. The flipping of the target bus 120 level value may be triggered by USB slave device 20, and USB slave device 20 may cause the target bus 120 level to change when USB slave device 20 needs to send data to SOC 110. In this case, the bus hold circuit 140 cannot hold the target bus 120 level unchanged. The amplitude of the level change of the target bus 120 triggered by the USB slave device 20 is much larger than the amplitude of the level change of the target bus 120 triggered by the false trigger signal. Therefore, the bus hold circuit 140 holds the target bus 120 level in the low power consumption state to avoid the change of the target bus 120 level caused by the false trigger signal.
According to the embodiment of the invention, after the system enters the low power consumption state, the bus level is detected through the system awakening control module, the bus level is maintained through the bus holding circuit, and the work of the USB controller and the USB PHY in the low power consumption state is replaced, so that when the system enters the low power consumption state, the USB controller and the USB PHY can be powered down, and the electric energy consumption of the system in the low power consumption state is saved.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs.
The modules in the device provided by the embodiment of the invention can be combined, divided and deleted according to actual needs.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (13)

1. A system-on-chip SOC, comprising: the system comprises a system awakening control module, a processor CPU, a USB controller and a universal serial bus physical layer module USB PHY; wherein:
the system wake-up control module is used for powering down the CPU, the USB controller and the USB PHY after the SOC receives an instruction for indicating to enter a low power consumption state;
the system wake-up control module is further used for powering on the CPU, the USB controller and the USB PHY after the SOC receives an instruction for indicating to exit the low power consumption state;
the SOC is further used for keeping the level of a target bus through a bus keeping circuit after the SOC receives an instruction for indicating to enter a low power consumption state; the bus holding circuit comprises a system wake-up controller or a pull-down resistor, and the target bus is a bus between the SOC and the USB slave device;
and the system wake-up control module is specifically configured to power on the CPU, the USB controller, and the USB PHY if the target bus level changes.
2. The SOC of claim 1, wherein the SOC receiving the instruction to indicate entry into a low power consumption state comprises: the SOC detects that the level of the target bus does not change within a preset time period.
3. The SOC of claim 1, wherein the SOC receiving the instruction to indicate entry into a low power consumption state comprises: the SOC receives a data packet sent by the USB slave equipment; the data packet is a response data packet of a link Layer Power Management (LPM) data packet sent by the SOC to the USB slave device, or the data packet is an LPM data packet sent by the USB slave device to the SOC.
4. The SOC of claim 2 or 3, wherein the SOC receiving the instruction to indicate exiting the low power consumption state comprises: and the SOC detects that the target bus level changes through the system awakening control module.
5. The SOC of claim 2 or 3, wherein the SOC is further configured to turn off the bus hold circuit after the system wake control module wakes up the CPU, USB controller, and USB PHY.
6. A Universal Serial Bus (USB) master device, comprising: a system-on-chip SOC and bus hold circuit; wherein the SOC is the SOC of any one of claims 1-5.
7. A Universal Serial Bus (USB) system, comprising: a USB master device and a USB slave device; wherein the USB master device comprises a System On Chip (SOC) and a bus holding circuit;
wherein the SOC is the SOC of any one of claims 1-5.
8. A USB wake-up method, comprising:
if the SOC receives an instruction for indicating to enter a low power consumption state, the SOC powers down a CPU (central processing unit), a USB (universal serial bus) controller and a USB PHY (universal serial bus) of a USB physical layer module;
if the SOC receives an instruction for indicating to exit the low power consumption state, the SOC powers on the CPU, the USB controller and the USB PHY;
if the system on chip SOC receives the instruction for indicating to enter the low power consumption state, the method further comprises:
the SOC keeps the level of a target bus through a bus holding circuit, the bus holding circuit comprises a system awakening controller or a pull-down resistor, and the target bus is a bus between the SOC and the USB slave device;
if the SOC receives an instruction for instructing to exit the low power consumption state, the SOC powers up the CPU, the USB controller, and the USB PHY, including:
and if the target bus level changes, powering on the CPU, the USB controller and the USB PHY.
9. The method of claim 8, wherein powering up the CPU, USB controller, and USB PHY if the target bus level changes comprises:
detecting the level of the target bus through a system wake-up control module;
and if the target bus level changes, the CPU, the USB controller and the USB PHY are electrified through the system awakening control module.
10. The method of claim 8, wherein the receiving the instruction to enter the low power consumption state by the system on chip SOC comprises: and if the SOC detects that the level of the target bus is not changed within a preset time period.
11. The method of claim 8, wherein the receiving the instruction to enter the low power consumption state by the system on chip SOC comprises: if the system-level chip receives a data packet sent by the USB slave equipment; the data packet is a response data packet of a link Layer Power Management (LPM) data packet sent by the SOC to the USB slave device, or the data packet is an LPM data packet sent by the USB slave device to the SOC.
12. The method of claim 10 or 11, wherein after the SOC powers up the CPU, USB controller, and USB PHY, the method further comprises:
the SOC turns off the bus hold circuit.
13. The method of claim 8, wherein the bus hold circuit comprises a bus keeper or a pull-down resistor.
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