CN116414212B

CN116414212B - Core particle and control method for core particle

Info

Publication number: CN116414212B
Application number: CN202310397447.6A
Authority: CN
Inventors: 陈佰儒; 刘勋
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2023-04-13
Filing date: 2023-04-13
Publication date: 2024-02-13
Anticipated expiration: 2043-04-13
Also published as: CN116414212A

Abstract

The present disclosure relates to a core particle and a control method of the core particle. The core particle comprises a physical layer functional module and a first physical layer interface module, wherein the physical layer functional module comprises a sending state machine sub-module, a data message sending sub-module and a control message sending sub-module. The data message sending submodule is configured to provide a first data message, the control message sending submodule is configured to provide a first state entering message, the sending state machine submodule is configured to control the physical layer functional module to switch from providing the first data message to the first physical layer interface module to providing the first state entering message to the first physical layer interface module, so that the first physical layer interface module is switched from providing the first data message to the other core particle through the physical link to providing the first state entering message to the other core particle through the physical link, and the first physical layer interface module is controlled to enter the low-power consumption state from the working state. The chip does not need to use an extra pin to control the first physical layer interface module to enter a low power consumption state.

Description

Core particle and control method for core particle

Technical Field

Embodiments of the present disclosure relate to a core particle and a control method of the core particle.

Background

Chiplet is also known as a "core" or "Chiplet". The core grain technology is to split a chip silicon wafer (die) with abundant functions and large area into a plurality of core grains. These pre-manufactured cores, which perform specific functions, are combined together and packaged together in advanced form (e.g., 3D package) to form a system-on-chip.

The high-speed interconnection between the core grains is a key technology for the falling of the core grain technology. When the chip design company designs interconnection interfaces among the core grains, the improvement of data throughput, the reduction of delay and code rate and the reduction of the overall power consumption of chip interconnection are required.

Disclosure of Invention

At least one embodiment of the present disclosure provides a core particle, including a physical layer functional module and a first physical layer interface module, where the first physical layer interface module is configured to be electrically connected to a second physical layer interface module of another core particle through a physical link, the physical layer functional module includes a sending state machine sub-module, a data packet sending sub-module, and a control packet sending sub-module, where the data packet sending sub-module is configured to provide a first data packet to the first physical layer interface module, and the control packet sending sub-module is configured to provide a first state entry packet to the first physical layer interface module, and where the sending state machine sub-module is configured to: receiving a first control signal; in response to the first control signal switching from a second mode to a first mode, controlling the physical layer functional module to switch from providing the first data message to the first physical layer interface module to providing a first state entry message to the first physical layer interface module, so that the first physical layer interface module switches from providing the first data message to the other core particle through the physical link to providing the first state entry message to the other core particle through the physical link; and after the first physical layer interface module provides the first state entry message for the other core particle, controlling the first physical layer interface module to enter a low power consumption state from a working state, wherein the first state entry message is used for notifying the other core particle to enter the low power consumption state, and the power consumption of the first physical layer interface module in the low power consumption state is smaller than that in the working state.

For example, in the core granule provided in an embodiment of the present disclosure, the first physical layer interface module includes a transmitting sub-module, and the transmitting sub-module is electrically connected to the transmitting state machine sub-module, and the transmitting state machine sub-module is configured to control the transmitting sub-module to enter the low power consumption state from the operating state in response to the first mode of the first control signal.

For example, in the core granule provided in an embodiment of the present disclosure, the control packet sending submodule is further configured to provide a wake-up packet and an exit packet to the sending submodule, and the sending state machine submodule is further configured to: responding to the first control signal to switch from the first mode to the second mode, and controlling the sending sub-module to exit the low-power consumption state and enter the working state; controlling the control message sending sub-module to provide the wake-up message for the sending sub-module, so that the sending sub-module provides the wake-up message for the other core particle to inform the second physical layer interface module to enter a working state; and controlling the control message sending sub-module to provide a state exit message for the sending sub-module, so that the sending sub-module provides the state exit message for another core particle to inform the other core particle of recovering the receiving of the first data message in the next clock cycle.

For example, in the core provided by an embodiment of the present disclosure, the transmit state machine submodule is further configured to: providing a third control signal to the sending sub-module, so that the sending sub-module enters the low power consumption state from the working state, the sending sub-module is in the working state in response to the third control signal being in a first control mode, and the sending sub-module is in the low power consumption state in response to the third control signal being in a second control mode.

For example, in the core particle provided in an embodiment of the present disclosure, the second control mode causes at least part of the circuit structures in the transmitting sub-module to be turned off, so that the transmitting sub-module is in the low power consumption state, and the first control mode causes at least part of the circuit structures to be turned on, so that the transmitting sub-module is in the working state.

For example, in a core granule provided in an embodiment of the present disclosure, the transmitting sub-module includes a plurality of data transmitting channels for transmitting the data packets, each of the plurality of data transmitting channels includes a data driving buffer and a parallel-to-serial conversion unit connected to the data driving buffer, the parallel-to-serial conversion unit configured to convert parallel data into serial data to provide the serial data to the data driving buffer, and each of the data driving buffers is connected to the physical link. The phase-locked loop is connected to the clock phase control unit, the clock switching unit is connected to the clock phase control unit and to the parallel-to-serial conversion unit, the phase-locked loop is configured to generate a clock signal, the clock phase control unit is configured to control a phase of the clock signal, and after the phase control of the clock signal, the clock signal is provided to the clock switching unit, the clock switching unit is configured to provide the clock signal to the parallel-to-serial conversion unit, the at least part of the circuit structure includes: a data driving buffer in at least one of the plurality of data transmission channels and the clock switching unit.

For example, in the core granule provided in an embodiment of the present disclosure, the sending submodule is in an on state in a data-driven buffer in a target sending channel in the plurality of data sending channels in the low power consumption state, and the sending state machine submodule is configured to provide the wake-up message to the other core granule through the data-driven buffer in the target sending channel; or the transmit sub-module further comprises a sideband signal path, the transmit state machine sub-module being configured to provide the wake-up message to the further core via the sideband signal path.

For example, in the core granule provided in an embodiment of the present disclosure, the physical layer functional module further includes a selector, where the selector includes a first input terminal, a second input terminal, a third input terminal, and an output terminal, the data packet sending sub-module is connected to the first input terminal, the control packet sending sub-module is connected to the second input terminal, the output terminal is connected to the physical layer interface module, and the sending state machine sub-module is further configured to provide a second control signal to the third input terminal, and the selector is configured to: and selecting the data message provided by the data message sending sub-module or the control message provided by the control message sending sub-module from the output end to the first physical layer interface module according to the second control signal.

For example, in the core provided by an embodiment of the present disclosure, the transmit state machine submodule is further configured to:

responding to a first mode of the first control signal, and providing a message stop receiving signal for the data message sending sub-module; the data message sending submodule is configured to: and responding to the message stop receiving signal, and stopping receiving the first data message.

For example, in the core particle provided in an embodiment of the present disclosure, further comprising: and the data bus module is configured to provide the first data message and the first control signal for the physical layer functional module.

For example, in the core granule provided by an embodiment of the present disclosure, the data bus module is further configured to: counting the number of invalid data; and triggering the first control signal to switch to the first mode in response to the number of invalid data being greater than a first preset threshold.

For example, in the core granule provided in an embodiment of the present disclosure, the data bus module includes a data buffer for storing the first data packet provided to the physical layer function module, and the data bus module is further configured to: counting the number of effective data in the data buffer; and responding to the number of the effective data reaching a second preset threshold value, triggering the first control signal to switch to the second mode so as to provide the first data message for the physical layer interface module.

For example, in the core granule provided in an embodiment of the present disclosure, the physical layer functional module further includes a receiving state machine sub-module, a data packet receiving sub-module, and a control packet receiving sub-module, and the first physical layer interface module is further configured to: receiving a communication message provided from the other core particle, and providing the communication message to the data message receiving sub-module and the control message receiving sub-module, wherein the data message receiving sub-module is configured to: the communication message is received, and the control message receiving sub-module is configured to: receiving the communication message, and in response to the communication message being a second state entry message, providing the second state entry message to the receiving state machine sub-module, the receiving state machine module configured to: and responding to the second state entering message, controlling the data message receiving sub-module to stop receiving the second data message, and controlling the first physical layer interface module to be switched from the working state to the low power consumption state.

For example, in the core particle provided in an embodiment of the present disclosure, further comprising: and responding to the communication message as the second data message, and providing the second data message for the data bus module by the data message receiving sub-module.

For example, in a core particle provided in an embodiment of the present disclosure, the first physical layer interface module includes a receiving sub-module, the receiving sub-module being connected to the receiving state machine sub-module, the receiving state machine sub-module being configured to: and controlling the receiving sub-module to be switched from the working state to the low-power consumption state.

For example, in the core provided by an embodiment of the present disclosure, the receive state machine submodule is further configured to: and providing a fourth control signal for the receiving sub-module so that the receiving sub-module enters the low power consumption state from the working state, responding to the fourth control signal as a first control mode, the receiving sub-module is in the working state, responding to the fourth control signal as a second control mode, and the receiving sub-module is in the low power consumption state.

For example, in the core particle provided in an embodiment of the present disclosure, the second control mode causes at least part of the circuit structures in the receiving sub-module to be turned off, so that the receiving sub-module is in the low power consumption state, and the first control mode causes at least part of the circuit structures to be turned on, so that the receiving sub-module is in the working state.

For example, in a core provided in an embodiment of the present disclosure, a receiving sub-module includes a plurality of data receiving channels for transmitting the data packets, each of the plurality of data receiving channels including a data receiving buffer and a serial-to-parallel conversion unit, each of the data receiving buffers being connected to the physical link, the serial-to-parallel conversion unit being configured to receive serial data provided by the data receiving buffer and to convert the serial data into parallel data, a clock phase control unit being connected to the clock phase control unit and to the serial-to-parallel conversion unit, the clock phase control unit being configured to receive a clock signal, control a phase of the clock signal, and, after phase control of the clock signal, to provide the clock signal to the clock switching unit, the clock switching unit being configured to provide the clock signal to the serial-to-parallel conversion unit, the at least part of the circuit structure including: a data reception buffer in at least one of the plurality of data reception channels and the clock switching unit.

For example, in the core granule provided in an embodiment of the present disclosure, the control message receiving submodule is further configured to: responding to the communication message as the awakening message, sending the awakening message to the receiving state machine sub-module, wherein the receiving state machine sub-module is configured to: responding to the received awakening message, and switching the fourth control signal into the first control mode so as to control the receiving sub-module to enter the working state; the control message receiving sub-module is further configured to: in response to the communication message being the state exit message, providing the exit message to the receiving state machine sub-module, the receiving state machine sub-module further configured to: and responding to the state exit message, and controlling the data message receiving sub-module to start receiving the second data message.

At least one embodiment of the present disclosure provides a control method of a core particle including a physical layer function module and a first physical layer interface module for electrically connecting with a second physical layer interface module of another core particle through a physical link, the method including: and after the first physical layer interface module provides the first state entry message for the other core particle, controlling the first physical layer interface module to enter a low power consumption state from an operating state, wherein the first state entry message is used for notifying the other core particle to enter the low power consumption state, and the power consumption of the first physical layer interface module in the low power consumption state is smaller than that in the operating state.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1A shows a schematic diagram of a circuit configuration of a gated clock;

FIG. 1B shows a timing diagram of a gating clock;

FIG. 1C illustrates a flow chart for entering and exiting the L1 state;

FIG. 2 illustrates an architecture diagram of a fast entry of a core into a low power state provided in at least one embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a portion of an internal circuit structure of a physical layer interface module provided in at least one embodiment of the present disclosure;

FIG. 4A shows a schematic circuit diagram of a data bus module generating a txFastPM_Entry signal provided in at least one embodiment of the present disclosure;

FIG. 4B shows a schematic circuit diagram of a data bus module generating a txFastPM_Exit signal provided in at least one embodiment of the present disclosure;

FIG. 4C illustrates a schematic diagram of independent control of a core in both receive and transmit directions of transmission provided by at least one embodiment of the present disclosure;

FIG. 5 illustrates a block diagram of a physical layer coding module PCS or adaptation layer provided by at least one embodiment of the present disclosure;

FIG. 6A illustrates a schematic diagram of a state machine of a transmit submodule provided by at least one embodiment of the present disclosure;

FIG. 6B illustrates a schematic diagram of a state machine of a receiving sub-module provided in at least one embodiment of the present disclosure

FIG. 7A is a flowchart of a method for a transmitting end and a receiving end to quickly enter a low power consumption state according to at least one embodiment of the present disclosure;

fig. 7B illustrates a timing diagram of a sender entering a low power consumption state quickly according to at least one embodiment of the present disclosure;

fig. 7C illustrates a timing diagram of a receiving end quickly entering a low power consumption state according to at least one embodiment of the present disclosure;

FIG. 8A is a flowchart of a method for a sender and a receiver to quickly exit a low power state according to at least one embodiment of the present disclosure;

fig. 8B illustrates a timing diagram of a sender exiting a low power state quickly provided by at least one embodiment of the present disclosure;

fig. 8C illustrates a timing diagram of a receiving end rapidly exiting a low power consumption state according to at least one embodiment of the present disclosure;

FIG. 9A illustrates a flow diagram of a state jump of a transmit state machine provided by at least one embodiment of the present disclosure; and

fig. 9B illustrates a flow diagram of a state jump of a receive state machine provided by at least one embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

The uci standard defines an interconnection specification between packaged kernels or chiplets to create an open kernel ecosystem. The Physical layer of the uicie standard specifies two different Physical layer interface modules (PHYs), 64 lanes (lane) for advanced encapsulation and 16 lanes (lane) for normal encapsulation, respectively. The number of parallel channels of the PHY of uicie is large and the power consumption is large if it is always in the operation mode. When the system needs less data to be transmitted, the PHY can be enabled to enter a low power consumption mode, so that the system power consumption is reduced.

3 power consumption management methods are defined in uci, namely gating clock management, L1 power consumption management, and L2 power consumption management, respectively.

Fig. 1A shows a schematic diagram of a circuit configuration of a gating clock. Fig. 1B shows a timing diagram of a gating clock. Gating clock management is described below in conjunction with fig. 1A and 1B.

As shown in fig. 1A, the left side is the transmitting end, and the right side is the receiving end.

The gated clock scheme uses a Valid (Valid) signal to indicate whether data is Valid or invalid.

When the transmitting end does not have effective data to transmit, the effective signal is set to 0, the transmitting end can close the clock of the transmitting end according to the effective signal, and simultaneously the clock transmitted to the receiving end is also closed, so that the power consumption of the transmitting end is saved.

The receiving end receives the valid signal and uses the valid signal to turn on or off the receiving clock. When the effective signal is 0, the clock of the receiving end is closed, so that the power consumption of the receiving end is saved.

The data at the transmitting end comes from a physical layer coding sub-layer module (Physical coding sublayer, PCS), the data provided to the PHY by the PCS first passes through a buffer 101, then passes through a parallel-to-serial converter 102, the parallel-to-serial converter 102 converts the parallel data into serial data, and then passes through a data driving buffer (buffer) 103 to transmit the data to the physical link.

The Clock at the transmitting end is generated by a phase-locked loop (Phase Locked Loop, PLL) 104, and the Clock output by the PLL 104 controls a Clock switch control circuit (Clock gate) 105 by an effective signal. The clock is output from the switching control circuit 105 when the valid signal is 1. When the valid signal is 0, the switching control circuit 105 outputs 0. The clock passing through the clock switch control circuit 105 controls the phase of the transmission clock through the clock phase controller 106. The clock of the phase control output is used for the buffer 101 and the parallel to serial converter 102. While the clock output by the clock phase controller 106 is sent to the physical link via the clock drive buffer 107.

The valid signal at the transmitting end comes from the PCS, and a valid signal of 1 indicates that the data sent to the PHY is valid. A valid signal of=0 indicates that the data sent to the PHY is invalid, at which point the PHY may turn off the clock at the transmitting end.

At the receiving end, judging whether the effective data is received according to the received effective signal. When the valid signal is 1, the output clock of the clock switch control circuit 116 is turned on, and the clock switch control circuit 116 supplies the output clock to a register (DFF) in the receiving-side Digital circuit. So that data can be normally received. When the valid signal is 0, the clock switch control circuit 116 outputs 0, and valid data is not received.

As shown in fig. 1B, both the rising and falling edges of the clock transmit and receive data. For one byte (byte) of data, a valid signal is defined to be high for 2 clock cycles and low for 2 clock cycles, indicating valid data transmission. The valid signal continues low for 8 clock cycles, indicating that no valid data is being sent and the clock can be turned off.

After the valid signal is pulled high, the data and clock recovery are indicated, and normal data reception is required.

And the gating clock is used for managing, and when effective data transmission is not carried out in the transmission process, the gating clock can rapidly close the clock of the PHY so as to save power consumption. Gating clock management achieves power saving by turning the PHY clock off, with an entry/exit time of about 0.5 nanoseconds, but with the worst power saving effect and requiring an additional Valid pin (Valid PAD).

Gating clock management requires an additional Pin (PAD) to tell the opposite if the data is valid. PAD of high performance chips is often limited, and increasing PAD may result in an increase in the area of the chip. While adding additional PADs itself increases power consumption. Gating clock management may achieve the effect of reducing power consumption by turning off part of the logic's clock. But merely turning off the clock reduces the power consumption value to a limited extent. The gating clock needs to keep the data channel, the clock channel and Valid channel are always on. The analog circuit is always on and the power consumption is still large in PHY.

The L1 power consumption management is that the link can enter the L1 state when no valid data is transmitted in both the receiving and transmitting directions for a long time, and the L1 power consumption management is that the link can enter the L2 state when no valid data is transmitted in both the receiving and transmitting directions for a long time. The L1 state and the L2 state are two low power states of uci, both of which are states in which the PHY is controlled to enter a low power state by a Physical Coding Sublayer (PCS) or an adaptation Layer (adaptation) defined in uci. The difference is that the PHY sleep level is shallow in the L1 state, and the PHY enters a retraining state after exiting the L1 state. The PHY sleep level is deeper in the L2 state, and the PHY enters a reset state after exiting L2.

The entry and exit flows of L1 power management and L2 power management are similar, with L1 power management being illustrated in this disclosure as entering and exiting the L1 state. Since L2 power consumption management is similar to L1 power consumption management, the disclosure will not be repeated.

FIG. 1C shows a flow chart for entering and exiting the L1 state.

As shown in fig. 1C, the method of entering the state includes steps S201 to S206.

Step S201: the adaptation layer of the transmitting end DIE0 transmits lp_state_req=l1 to the physical layer. Lp_state_req is that the adaptation layer initiates a state change request to the physical layer, and L1 represents that the adaptation layer controls the physical layer to enter an L1 state.

Step S202: the physical layer of the transmitting end DIE0 transmits a request message l1.req to the receiving end DIE1 through a sideband signal (sb_msg) into an L1 state.

Step S203: the adaptation layer of the receiving end DIE1 responds to the request message l1.req of the transmitting end DIE0, and controls the physical layer lp_state_req=l1 of the receiving end DIE1.

Step S204: the physical layer of the receiving end DIE1 returns a feedback signal l1.Rsp to the transmitting end DIE0, and simultaneously the physical layer of the receiving end DIE1 also transmits a request message l1.Req to the transmitting end DIE 0.

Step S205: after receiving the feedback signal l1.rsp of the receiving end DIE1, the physical layer of the transmitting end DIE0 makes the pl_state_sts=pm to enter the PM state, and simultaneously transmits the feedback signal l1.rsp to the receiving end DIE1. The PM state refers to the L1 state or the L2 state, and if pl_state_req=l1, the PM state refers to the L1 state; if pl_state_req=l2, the PM state refers to the L2 state. For example, the physical layer of the transmitting end DIE0 transmits a status indication signal pl_state_sts=pm to the adaptation layer, so that the transmitting end DIE0 enters the PM state.

Step S206: the physical layer of the receiving end DIE1 receives the feedback signal l1.Rsp of the transmitting end DIE0 and then enters the PM state.

As shown in fig. 1C, the method for exiting the low power consumption state includes steps S301 to S306.

Step S301: the adaptation layer of the sending end DIE0 controls the physical layer lp_state_req=active, and Active indicates that the physical layer is controlled to enter a working state so as to control the physical layer to exit the L1 state.

Step S302: the physical layer of the sending end DIE0 sends a request message active. Req entering the working state to the receiving end DIE1 through a sideband signal.

Step S303: after receiving the active. Req, the physical layer of the receiving end DIE1 sends an active. Rsp message to the sending end DIE0, and notifies the adaptation layer to re-perform link training. For example, the physical layer of the transmitting end DIE0 transmits the status indication signal pl_state_sts=retrain to the adaptation layer, so that the adaptation layer retrains the link.

Step S304: the adaptation layer of the receiving end DIE1 controls the physical layer lp_state_req=active, and controls to exit from the L1 state. The receiving end DIE1 physical layer sends an active. Req message to the sending end DIE 0.

Step S305: the physical layer of the sending end DIE0 returns to active.Rsp after receiving the active.req. And (5) entering a working state after waiting for training.

Step S306: after receiving the active rsp, the physical layer of the receiving end DIE1 waits for training to be received and then enters a working state.

L1 power consumption management may turn off the phase locked loop of the PHY, saving more power. PHY requires retraining when the L1 state exits, so the time to exit is long on the order of subtle or milliseconds. The L2 power management may turn off the entire PHY to be the most power efficient state, but the L2 state needs to be re-entered into the reset state when exiting, and the time required to restore to the active state is also the longest.

The whole link is disconnected no matter L1 power consumption management or L2 power consumption management, and the PHY needs to be retrained when being reconnected, so that the exiting time is long. Upon entering the L1 state or the L2 state, the PHY transmission and reception will be completely stopped. The analog circuitry of the PLL, etc. are turned off. If the data transmission is to be resumed, the PHY will need to be retrained. Also, the L1 power consumption management and the L2 power consumption management use sideband signals to transmit additional control signals, require additional PADs, and consume additional power consumption. The Sideband signal requires two signals, SB_Clock and SB_Message, and additional transmit and receive circuitry, requiring additional power consumption.

The present disclosure proposes a core that does not require the use of additional pins to enable the core to quickly enter and exit from a low power mode (e.g., the entry and exit time is only a few clock cycles). Some embodiments of the present disclosure are also capable of shutting down the output clock of the PHY and the analog transceiver circuitry, effectively reducing the digital transceiver logic power consumption and the PHY power consumption.

At least one embodiment of the present disclosure provides a core particle. The core particle comprises a physical layer functional module and a first physical layer interface module, wherein the first physical layer interface module is used for being electrically connected with a second physical layer interface module of another core particle through a physical link, the physical layer functional module comprises a sending state machine sub-module, a data message sending sub-module and a control message sending sub-module, the data message sending sub-module is configured to provide a first data message for the first physical layer interface module, the control message sending sub-module is configured to provide a first state entering message for the first physical layer interface module, and the sending state machine sub-module is configured to: receiving a first control signal; and after the first physical layer interface module provides the first state entry message for the other core particle, controlling the first physical layer interface module to enter a low power consumption state from the working state, wherein the first state entry message is used for notifying the other core particle to enter the low power consumption state, and the power consumption of the first physical layer interface module in the low power consumption state is smaller than that in the working state. The core particle controls the physical link transmission state to enter the message through the sending state machine submodule, so that the physical link can transmit not only the data message but also the state to enter the message, and the core particle can enter and exit the low-power consumption mode rapidly without adding an extra pin.

Fig. 2 illustrates an architecture diagram of a fast entry of a core into a low power state provided in at least one embodiment of the present disclosure. An example of a core particle provided in accordance with at least one embodiment of the present disclosure is described below in conjunction with fig. 2.

As shown in fig. 2, a core particle DIE0 is included in the architecture. The core particle DIE0 includes a physical layer function module PCA0 and a physical layer interface module PHY0. The physical layer interface module PHY0 is configured to be electrically connected to the physical layer interface module PHY1 of another core DIE1 through a physical link. The physical layer interface module PHY0 is an example of a first physical layer interface module, and the physical layer interface module PHY1 is an example of a second physical layer interface module.

For example, the physical layer function module PCA0 may be a physical layer coding submodule or an adaptation layer. The adaptation layer is used to select and arbitrate between multiple protocols. The physical layer coding submodule is used for controlling the physical layer interface module to transmit and receive data. The physical layer interface module is responsible for signal transmission techniques related to the electrical characteristics. The physical link may be a wired link or a wireless link (e.g., optical fiber, etc.), and embodiments of the present disclosure do not specifically limit the form of the physical link.

The physical layer function module PCA0 includes a transmit state machine sub-module 210, a data message transmit sub-module 220, and a control message transmit sub-module 230.

The data message sending sub-module 220 is configured to provide the data message txData to the physical layer interface module PHY 0. The data message txData is an example of a first data message. The control message sending sub-module 230 is configured to provide a first state entry message to the physical layer interface module PHY 0. The first state entry message is used for notifying another core particle DIE1 to enter a low power consumption state. The first state entry message is, for example, the fpmetric message in fig. 2.

The transmit state machine sub-module 210 is configured to: receiving a control signal txLowPower (the control signal txLowPower is an example of a first control signal); in response to the control signal txLowPower being switched from the second mode to the first mode, the physical layer function module PCA0 is controlled to switch from providing the first data packet to the physical layer interface module PHY0 to providing the first state entry packet (e.g., fpmetric packet) to the physical layer interface module PHY0 such that the physical layer interface module PHY0 is switched from providing the data packet txData to the other core DIE1 over the physical link to providing the first state entry packet to the other core DIE1 over the physical link, and after the physical layer interface module PHY0 provides the first state entry packet to the other core DIE1, the physical layer interface module PHY0 is controlled to enter the low power state from the operating state, the power consumption of the physical layer interface module PHY0 in the low power state being less than the power consumption in the operating state.

For example, the control signal txLowPower may include one or more level signals. For example, the control signal txLowPower includes 1 level signal, and if the level signal is at a first level (e.g., high level), the control signal txLowPower is in a first mode, and if the level signal is at a second level (e.g., low level), the control signal txLowPower is in a second mode. For another example, the control signal txLowPower includes a plurality of level signals, and different combinations of the level signals respectively represent different modes. For example, the 2 level signals are all high, which indicates that the control signal txLowPower is in the first mode, the 2 level signals are all low, which indicates that the control signal txLowPower is in the second mode, and the 2 level signals are all high and one low, which indicates that the control signal txLowPower is in the third mode. The present disclosure does not limit the first control signal and the mode of the first control signal.

Hereinafter, the control signal txLowPower is set to a high level as a first mode, and the control signal txLowPower is set to a low level as a second mode.

For example, in response to the control signal txLowPower switching from low to high, the transmit state machine sub-module 210 controls the physical layer function module PCA0 to switch from providing the first data packet to the physical layer interface module PHY0 to providing the first state entry packet to the physical layer interface module PHY 0. That is, if the control signal txLowPower is at a low level, the transmit state machine sub-module 210 controls the physical layer function module PCA0 to provide the first data packet to the physical layer interface module PHY 0; if the control signal txLowPower is at a high level, the transmit state machine sub-module 210 controls the physical layer function module PCA0 to provide a first state entry message to the physical layer interface module PHY 0.

The physical interface module PHY0 provides the messages received from the physical layer function module PCA0 to another core DIE1 via a physical link. For example, if the physical layer function module PCA0 provides the data packet txData to the physical interface module PHY0, the physical interface module PHY0 provides the data packet txData to another core DIE1 through a physical link; if the physical layer function module PCA0 provides the first state entry message to the physical interface module PHY0, the physical interface module PHY0 provides the first state entry message to another core DIE1 through a physical link.

The physical layer function module PCA0 switches from providing the data message txData to the physical layer interface module PHY0 to providing the first state entry message to the physical layer interface module PHY0, so that the physical layer interface module PHY0 switches from providing the data message txData to the other core particle DIE1 through the physical link to providing the first state entry message to the other core particle DIE1 through the physical link.

After the physical layer interface module PHY0 provides the first state entry message to another core DIE1, the physical layer interface module PHY0 is controlled to enter a low power consumption state from the working state. The physical layer interface module PHY0 consumes less power in the low power state than in the active state.

For example, the physical layer interface module PHY0 includes a transmit sub-module TX0. The transmitting sub-module TX0 is configured to transmit a data packet. The transmitting sub-module TX0 is electrically connected to the transmitting state machine sub-module 210, and the transmitting state machine sub-module 210 is configured to control the transmitting sub-module TX0 to enter a low power consumption state from an operating state in response to a first mode of the first control signal. That is, the physical layer interface module PHY0 entering the low power consumption state includes the transmitting sub-module TX0 entering the low power consumption state.

In the embodiment of the disclosure, the core particle responds to the control signal through the sending state machine submodule and controls the physical layer functional module to transmit the data message by using the physical link and transmit the first state entering message by using the physical link, so that the core particle can quickly enter and exit the low-power consumption mode without adding an extra pin.

As shown in fig. 2, in some embodiments of the present disclosure, the physical layer function module PCA0 may further include a selector including a first input (e.g., input D0), a second input (e.g., input D1), a third input (e.g., input S), and an output (e.g., input P).

The data message sending sub-module 220 is connected to the input D0, the control message sending sub-module 230 is connected to the input D1, the output P is connected to the physical layer interface module PHY0,

The transmit state machine sub-module 210 is further configured to provide a second control signal, such as the control signal txfastpm_sel shown in fig. 2, to the input S.

The selector 240 is configured to select the message provided by the data messaging sub-module 220 or the control message provided by the control messaging sub-module 230 to the physical layer interface module PHY0 at the output P according to the control signal txfastpm_sel.

The control message provided by the control message sending sub-module 230 may not only include the first state entry message described above, but also include a state exit message, a wake-up message, and the like. For the exit message or wake-up message, refer to the description below.

For example, if the control signal txLowPower is at a low level, the control signal txfastpm_sel output by the transmit state machine submodule 210 is at a low level, the input terminal S of the selector 240 receives the low level signal, and the signal output of the input terminal D0 is selected, that is, the data packet txData is provided to the physical layer interface module PHY0 via the output terminal P; if the control signal txLowPower is at a high level, the control signal txfastpm_sel output by the transmit state machine submodule 210 is at a high level, the input terminal S of the selector 240 receives the high level signal, and the signal output of the input terminal D1 is selected, that is, the first state entry message is provided to the physical layer interface module PHY0 via the output terminal P.

The physical layer function module PCA0 is controlled by the selector to provide data messages or control messages for the physical layer interface module PHY0, so that the logic of the physical layer function module PCA0 is simple and easy to realize. However, the method for controlling the physical layer function module PCA0 by providing the data message or the control message to the physical layer interface module PHY0 is not limited in this disclosure, and those skilled in the art may use other methods to control the physical layer function module PCA0 by providing the data message or the control message to the physical layer interface module PHY0

In some embodiments of the present disclosure, the control message sending sub-module 230 is further configured to provide a wake-up message and a status exit message to the sending sub-module TX 0.

The transmit state machine sub-module 210 is further configured to switch from the first mode to the second mode in response to a first control signal (e.g., control signal txLowPower), control the transmit sub-module TX0 to exit the low power consumption state and enter the operational state; the control message sending sub-module 230 provides a wake-up message to the sending sub-module TX0, so that the sending sub-module provides a wake-up message to another core particle DIE1 to inform the physical layer interface module PHY1 to enter a working state; the control packet transmitting sub-module 230 provides a status exit packet to the transmitting sub-module TX0, so that the transmitting sub-module TX0 provides a status exit packet to the other core DIE1 to notify the other core DIE1 that the next clock cycle resumes the reception of the first data packet.

For example, as shown in fig. 2, the wake-up message is an FPMWake message, and the exit message is an FPMExit message. The FPMWake and FPMExit messages are provided, for example, by the transmit state machine sub-module 210 to the control message transmit sub-module 230, whereby the control message transmit sub-module 230 provides a wake-up message and a state exit message to the transmit sub-module TX 0.

And providing a wake-up message and a state exit message for the other core particle through a physical link, so that the other core particle is controlled to recover the working state under the condition that pins are not added.

In some embodiments of the present disclosure, the transmit state machine sub-module 210 is further configured to provide a message stop receive signal tx_stop to the data message transmit sub-module 220 in response to the first mode of the first control signal; the data packet transmission sub-module 220 is configured to stop receiving the first data packet in response to the packet stop reception signal tx_stop.

In some embodiments of the present disclosure, the transmit state machine sub-module 210 is further configured to provide a third control signal to the transmit sub-module TX0 to cause the transmit sub-module TX0 to enter a low power consumption state from an operating state. In response to the third control signal being in the first control mode, the transmitting sub-module TX0 is in an operating state, and in response to the third control signal being in the second control mode, the transmitting sub-module TX0 is in a low power consumption state.

As shown in fig. 2, the third control signal is, for example, a control signal tx_lp. For example, the control signal tx_lp is low in the first control mode, and the control signal tx_lp is high in the second control mode. Similar to the first control signal, the present disclosure also does not limit the first control mode and the second control mode of the third control signal.

For example, after the physical layer interface module PHY0 provides the fpmetric message to another core DIE1, the transmit state machine sub-module 210 provides the control signal tx_lp of the high level to the physical layer interface module PHY0, so that the transmit sub-module TX0 of the physical layer interface module PHY0 enters the low power consumption state.

In some embodiments of the present disclosure, the second control mode of the control signal tx_lp causes at least part of the circuit structures in the transmitting sub-module TX to be turned off, such that the transmitting sub-module TX0 is in a low power consumption state, and the first control mode causes at least part of the circuit structures to be turned on, such that the transmitting sub-module TX0 is in an operating state.

For example, at least some of the circuit structures include clock circuits, data paths, phase locked loops, and the like. Those skilled in the art may set the circuit structure to be turned off in the low power state by themselves, and the present disclosure is not limited thereto.

In some embodiments of the present disclosure, the physical layer interface module of the core may include a transmitting sub-module and a receiving sub-module, where the receiving sub-module is used for receiving the data packet. For example, the physical layer interface module PHY0 includes a transmitting sub-module TX0 and a receiving sub-module RX0; the physical layer interface module PHY1 comprises a transmit sub-module TX1 and a receive sub-module RX1.

Fig. 3 is a schematic diagram illustrating a part of an internal circuit structure of a physical layer interface module according to at least one embodiment of the present disclosure.

For example, a part of the internal circuit structure of the transmission sub-module TX0 of the physical layer interface module PHY0 is shown on the left side of fig. 3; a part of the internal circuit structure of the receiving sub-module RX1 of the physical layer interface module PHY1 is shown on the right side of fig. 3. Only the connection relation of the transmitting sub-module TX0 of the physical layer interface module PHY0 and the receiving sub-module RX1 of the physical layer interface module PHY1 is shown. The receiving sub-module RX0 of the physical layer interface module PHY0 is similar to the receiving sub-module RX1 of the physical layer interface module PHY1 in structure, and will not be described again. The transmission sub-module TX1 of the physical layer interface module PHY1 is similar to the transmission sub-module TX0 of the physical layer interface module PHY1, and will not be described again.

In some embodiments of the present disclosure, each physical layer interface module has a plurality of data channels (Lane). The plurality of data channels includes a plurality of data transmission channels and a plurality of data reception channels. The transmitting submodule in the physical layer interface module comprises a plurality of data transmitting channels, and the receiving submodule comprises a plurality of data receiving channels, so that data can be independently transmitted and received through the data transmitting channels and the data receiving channels. The transmitting sub-module includes a clock channel for providing a transmitting clock of the transmitting end to the receiving end (e.g., the receiving sub-module RX 1) in addition to a plurality of data transmitting channels.

For example, the transmitting sub-module TX0 comprises a plurality of data transmission channels for transmitting data messages. Each data transmission channel includes a data driving buffer and a parallel-to-serial conversion unit. The parallel-to-serial conversion unit is connected with the data driving buffers and is configured to convert parallel data into serial data to provide the serial data to the data driving buffers, each driving buffer being connected with a physical link. For example, the data channel 0 includes at least a buffer 0, a parallel-to-serial conversion unit 0, and a data driving buffer DD0. The other data channels are similar to data channel 0 and include at least a buffer, a parallel to serial conversion unit and a data driving buffer.

As shown in fig. 3, the transmission data (e.g., transmission data 0, transmission data 1, … …, transmission data n) of each data channel is buffered and then converted into serial data through one parallel-to-serial conversion. Serial data is sent over a data driven buffer onto a physical channel (i.e., physical link). The receiving terminal RX1 receives a signal from the physical channel, passes through a data receiving buffer, and provides the signal to the serial-parallel conversion unit, converts the serial data into parallel data, and then sends the parallel data to the buffer.

As shown in fig. 3, the transmitting sub-module TX further comprises a phase locked loop PLL, a clock phase control unit 310 and a clock switching unit 320.

The phase-locked loop PLL is connected to the clock phase control unit 310, and the clock switching unit 320 is connected to the clock phase control unit 310 and to each of the plurality of parallel-to-serial conversion units. The phase-locked loop PLL is configured to generate a clock signal, the clock phase control unit 310 is configured to control the phase of the clock signal, and after the phase control of the clock signal, the clock signal is supplied to the clock switching unit 320, and the clock switching unit 320 is configured to supply the clock signal to the parallel-to-serial conversion unit.

At least part of the circuit structure includes at least one data driving buffer and clock switching unit 320 of the plurality of data paths.

In some embodiments of the present disclosure, as shown in fig. 3, for example, the transmitting sub-module TX0 receives a control signal tx_lp provided by a physical layer functional module (e.g., PCA0 in fig. 2), and the physical layer functional module controls the transmitting sub-module TX0 to quickly enter a low power consumption state. Since the physical layer interface module PHY0 does not have valid data to transmit after entering the low Power state, the control signal tx_lp controls the clock Switch module to turn off the clock, and at the same time, the control signal tx_lp may control the Power Switch (Power Switch) of the data driving buffer to be turned off. For example, the power supply switch 330 of the data driving buffer DD0 is turned off, thereby powering off the analog Input Output (IO), thereby saving power consumption of the transmitting sub-module TX 0.

In embodiments of the present disclosure, when PHY0 quickly goes into low power consumption, powering off the analog circuitry of PHY0, e.g., turning off the data drive buffer, does not require retraining PHY 0. And thus can quickly enter and exit the low power mode.

In some embodiments of the present disclosure, the transmitting sub-module TX0 is in an on state in the data driving buffer in the target data lane of the plurality of data lanes in the low power consumption state. The transmit state machine sub-module 210 is configured to: and providing a wake-up message to another core particle through a data driving buffer in the target data channel.

The data driving buffer in the target data channel keeps on state and can wake up the receiving terminal RX1 of another core particle DIE1 in time. The target data channel may be one data channel or a plurality of data channels. For example, in order to wake up the receiving end RX1 of another core particle DIE1 in time, for example, one data channel in the transmitting sub-module TX0 is kept in an open state, and the data channel kept in the open state is the target data channel. As shown in fig. 3, the power supply switch 330 of the data driving buffer DD0 is in an on state. For example, the power supply switch 330 includes a transistor, the transistor is turned on at a low level, and the gate input signal 0 of the transistor of the data driving buffer DD0 indicates a low level, so that the power supply switch 301 is in an open state. The data channel 0 where the data driving buffer DD0 is located is the target data channel.

For example, at least part of the circuit structures in the transmitting sub-module TX0 of the physical layer interface module PHY0, which may include the data driving buffers DD1, … …, the data driving buffer DDn and the clock switching unit 320, for example, are turned off when the control signal tx_lp is at a low level. The data driving buffer DD0 and the clock driving buffer remain in an open state to be able to wake up the receiving terminal RX1 of the other core DIE1 in time.

In other embodiments of the present disclosure, the transmit submodule TX0 further comprises a sideband signal path, and the transmit state machine submodule 210 is configured to: a wake-up message is provided to the other core through the sideband signal path. This embodiment may not require that at least one data channel and clock channel be left in an on state, but may require an additional sideband signal path.

In some embodiments of the present disclosure, the core may also include a DataFabric (DF) 250.

The data bus module 250 is configured to provide a first data packet (e.g., data packet txData) and a first control signal (e.g., control signal txLowPower) to the physical layer function module PCA 0.

The data bus module 250 controls data communication of the various modules in the chip, such as data communication of the processor and the memory module. Data for data bus module 250 in the Chiplet structure needs to be transferred across the DIE. For example, when the data bus module 250 of DIE0 needs to send data to DIE1, the data packet is sent to the physical layer coding submodule PCS of DIE0, and the data packet sending submodule 220 in the PCS processes the data and sends the processed data to the physical layer interface module PHY0. The physical layer interface module PHY0 processes the data packet and sends the data packet to the physical link. The did 1 receives the data packet from the PHY1 and then sends the received data packet to the PCS of the did 1, and the data packet receiving module in the PCS of the PHY is configured to process the data and then send the data packet to its own data bus module.

In some embodiments of the present disclosure, the data bus module 250 is further configured to: counting the number of invalid data; and triggering the first control signal to switch to the first mode in response to the number of invalid data being greater than a first preset threshold.

A number of invalid data greater than the first preset threshold indicates that the data bus module 250 has no valid data to send. When the data bus module 250 has no valid data to be transmitted, the first control signal is controlled to switch to the first mode, the first control signal of the first mode is provided to the physical layer coding submodule PCS of DIE0, and the physical layer coding submodule PCS of DIE0 and the physical layer interface module PHY0 are controlled to enter a low power consumption state of the transmitting submodule. For example, the first mode of the first control signal is a low level signal of the control signal txLowPower, which is hereinafter referred to as "txfastpm_entry signal". The method of generating the txfastpm_entry signal may be obtained by counting the number of invalid data transmitted. When no valid data is transmitted, a counter is used for counting the number of invalid data, and when the number of continuously transmitted invalid data exceeds a first preset threshold value, a txFastPM_entry signal is triggered.

FIG. 4A shows a schematic circuit diagram of a data bus module generating a txFastPM_Entry signal provided in at least one embodiment of the present disclosure.

As shown in fig. 4A, the data bus module 250 includes at least a counter 401, a comparator 402, and a plurality of selectors.

A counter 401 and a plurality of selectors are used to count invalid data. For example, if the valid_packet signal is 1, it indicates that the data bus module 250 outputs Valid data; if the valid_packet signal is 0, it indicates that the data bus module 250 outputs invalid data. The data bus module 250 generates a signal by itself according to whether Valid data is required to be transmitted when the valid_packet signal is generated. The comparator 402 is configured to compare the number of invalid data with a first predetermined threshold. If the number of invalid data is greater than the first preset threshold, the comparator 402 generates a txFastPM_Entry signal. For the txfastpm_exit signal in fig. 4A, please refer to the description of fig. 4B.

In some embodiments of the present disclosure, the data bus module 250 includes a data buffer for storing the first data packet provided to the physical layer function module, and the data bus module 250 is further configured to count the number of valid data in the data buffer; and triggering the first control signal to switch to a second mode in response to the number of the effective data reaching a second preset threshold so as to provide a first data message for the physical layer interface module.

The number of valid data in the data buffer being greater than the second predetermined threshold indicates that valid data is present in the data bus module 250 to be transmitted. When there is valid data to be transmitted in the data bus module 250, the first control signal is controlled to switch to the second mode, the first control signal in the second mode is provided to the physical layer coding submodule PCS of the core particle DIE0, and the physical layer coding submodule PCS of the DIE0 and the physical layer interface module PHY0 are controlled to enter the working state of the transmitting submodule. For example, the second mode of the first control signal is a high level signal of the control signal txLowPower, which will be hereinafter referred to as "txfastpm_exit signal". the txFastPM_Exit signal is sent to the PCS to control the PCS and PHY to Exit from the low power state and to resume the normal operating state (Active). The method of generating the txfastpm_exit signal may be obtained by counting the number of valid data in the data buffer of the data bus module 250. When the number of valid data exceeds a second preset threshold, txfastpm_exit is triggered.

Fig. 4B shows a schematic circuit diagram of a data bus module generating a txfastpm_exit signal provided in at least one embodiment of the present disclosure.

As shown in fig. 4B, the data bus module 250 includes at least a buffer 410, a comparator 420, a counter 430, and a plurality of selectors.

The counter 430 and the plurality of selectors are used to count valid data in the buffer. The comparator 420 is configured to compare the number of invalid data with a second predetermined threshold. If the number of valid data is greater than the second threshold value, the comparator 402 generates a txFastPM_Exit signal.

Write_data represents a Data packet written to the buffer 410.

The circuit diagrams shown in fig. 4A and 4B are only an example, and those skilled in the art can design the circuit structures of the trigger txfastpm_entry signal and the txfastpm_exit signal by themselves, and the present disclosure is not limited to the circuit structures of the data bus module.

In some embodiments of the present disclosure, as shown in fig. 2, the physical layer function module PCA0 further includes a receive state machine sub-module 260, a data message receiving sub-module 270, and a control message receiving module 280. The physical layer interface module PHY0 is further configured to: receives a communication message provided from another core particle DIE1 and provides the communication message to the data message receiving sub-module 270 and the control message receiving sub-module 280. The data message receiving sub-module 270 is configured to receive a communication message. The control message receiving sub-module 280 is configured to receive the communication message and provide a second state entry message to the receiving state machine sub-module in response to the communication message being the second state entry message. The receive state machine submodule 260 is configured to: in response to the second state entry message, the control data message receiving sub-module 270 stops receiving the second data message, and controls the first physical layer interface module PHY0 to switch from the operating state to the low power consumption state.

In this embodiment, core DIE0 is used as the receiving end, DIE1 is used as the transmitting end, and DIE0 receives the communication message from core DIE1 via physical interface module PHY 0. The communication message may be a data message or a control message. As described above, the control message may be any one of a state entry message, a wake-up message, and a state exit message.

For example, the receiving sub-module RX0 of the core DIE0 receives the communication message provided by the transmitting sub-module TX1 of the core DIE 1.

The second state entering message refers to a control message provided by another core particle DIE1 to a core particle DIE0, the first state entering message refers to a control message provided by a core particle DIE0 to another core particle DIE1, and the format of the second state entering message may be the same as that of the first state entering message, or the second state entering message is the same as that of the first state entering message.

The second data message refers to the data message provided from the other core particle DIE1 to the core particle DIE0, and the first data message refers to the data message provided from the core particle DIE0 to the other core particle DIE 1. The first data message and the second data message are different, but the formats of the first data message and the second data message may be the same.

In some embodiments of the present disclosure, the control message receiving sub-module 280 may determine whether the communication message is a data message or a control message according to a message format of the communication message. In response to the communication message being a second data message, the data message receiving sub-module 270 provides the second data message to the data bus module 250. The second data packet is, for example, the data packet rxData in fig. 2. In response to the communication packet being the second state entry packet, the second state entry packet is provided to the receiving state machine sub-module 260, so that the receiving state machine sub-module 260 controls the data packet receiving sub-module 270 to stop receiving the second data packet, and controls the first physical layer interface module PHY0 to switch from the working state to the low power consumption state. The second state entry message is, for example, the fpmetric' message shown in fig. 2.

For example, the receive state machine submodule 260 provides a message stop receive signal rx_stop to the data message receive submodule 270 in response to the communication message being a second state enter message. The data message receiving sub-module 270 is configured to stop receiving the second data message in response to the message stop receive signal rx_stop.

In some embodiments of the present disclosure, the physical layer interface module PHY0 includes a receive sub-module RX0, where the receive sub-module RX0 is connected to the receive state machine sub-module 260. The receive state machine sub-module 260 is configured to control the receive sub-module RX0 to switch from the operating state to the low power consumption state. For example, in response to the fpmetric' message, the receive state machine sub-module 260 controls the receive sub-module RX0 to switch from the operating state to the low power consumption state.

According to the embodiment, the receiving sub-module and the sending sub-module can be independently controlled to enter a low-power-consumption state in the receiving and sending directions, and the power consumption of a chip can be saved when no effective data is transmitted in any direction. When no effective data is transmitted in one direction, the transmitting sub-module of the transmitting end and the receiving sub-module of the receiving end are controlled to enter a low power consumption state so as to save power consumption, and the data channel in the other direction is kept in a working state (the transmitting sub-module of the transmitting end and the transmitting sub-module of the receiving end are still in a normal working state).

Fig. 4C illustrates a schematic diagram of independent control of a core in both receive and transmit directions of transmission provided by at least one embodiment of the present disclosure.

Fig. 4C shows the structures of the core particle DIE0 and the core particle DIE1 and the functions of the respective structures are the same as those of fig. 2, and are not repeated.

As shown in fig. 4C, DIE0 is used as a transmitting end, and DIE1 is used as a receiving end. The transmit direction 4000 and the receive direction 4100 are independent of each other. That is, some embodiments of the present disclosure can individually control the transmitting sub-module TX0 of DIE0 and the receiving sub-module RX1 of DIE1, and can individually control the receiving sub-module RX0 of DIE0 and the transmitting sub-module TX1 of DIE1, thereby realizing independent control of the transmission direction of DIE0 as a transmitting end and DIE1 as a receiving end and the transmission direction of DIE0 as a receiving end and DIE1 as a transmitting end.

In some embodiments of the present disclosure, the receiving state machine sub-module 260 is further configured to provide a fourth control signal to the receiving sub-module RX to cause the receiving sub-module RX to enter the low power consumption state from the operating state. The fourth control signal is, for example, the control signal rx_lp in fig. 2. The control signal rx_lp comprises, for example, a plurality of operating modes. For example, the control signal rx_lp is in a first control mode in which the low level is the control signal rx_lp, and the control signal rx_lp is in a second control mode in which the high level is the control signal rx_lp.

In response to the fourth control signal being in the first control mode, the receiving sub-module RX0 is in a working state, and in response to the fourth control signal being in the second control mode, the receiving sub-module RX0 is in a low power consumption state. For example, the receiving sub-module RX0 enters an operating state in response to the control signal rx_lp being low; the reception sub-module RX0 enters a low power consumption state in response to the control signal rx_lp being low.

In some embodiments of the present disclosure, the second control mode of the fourth control signal causes at least part of the circuit structures in the receiving submodule to be turned off, such that the receiving submodule is in a low power consumption state, and the first control mode causes at least part of the circuit structures to be turned on, such that the receiving submodule is in an operational state.

For example, at least some of the circuit structures include clock circuits, data lanes, phase-locked loops, and the like. Those skilled in the art may set the circuit structure to be turned off in the low power state by themselves, and the present disclosure is not limited thereto.

The circuit structure of the receiving sub-module RX0 of the physical layer interface module PHY0 may be similar to the circuit structure of the receiving sub-module RX1 of the physical layer interface module PHY1, and the circuit structure of the receiving sub-module RX0 will be described below with reference to fig. 3 by taking the receiving sub-module RX1 of the physical layer interface module PHY1 as an example.

For example, the receiving sub-module RX1 comprises a plurality of data receiving channels for transmitting data messages. The plurality of data reception channels each include a data reception buffer and a serial-parallel conversion unit. The serial-to-parallel conversion unit is connected with the data receiving buffer and is configured to receive serial data provided by the data receiving buffer and convert the serial data into parallel data. Each data receiving buffer is connected to a physical link. For example, the data reception channel 0 includes at least a buffer 3, a serial-parallel conversion unit 0, and a data reception buffer DR0. The other data receiving channels are similar to the data receiving channel 0 and include at least a buffer, a serial-parallel conversion unit and a data receiving buffer.

As shown in fig. 3, the data packet of each data receiving channel is converted into parallel data by the serial-parallel conversion unit, and then is provided to the physical layer coding module PCS after being buffered.

As shown in fig. 3, the receiving sub-module RX1 further includes a plurality of clock phase control units and a plurality of clock switching units. For example, each data receiving channel corresponds to one clock phase control unit and one clock switching unit. For example, the data reception channel 0 corresponds to the clock phase control unit 340 and the clock switching unit 350.

The clock switching unit 350 is connected to the clock phase control unit 340 and to the serial-parallel conversion unit 0 and the cache 3. The clock phase control unit 340 is configured to control the phase of the clock signal, and after the phase control of the clock signal, the clock signal is supplied to the clock switching unit 350, and the clock switching unit 320 is configured to supply the clock signal to the serial-parallel conversion unit.

For example, the circuit structure of the receiving sub-module RX0 is the same as the circuit structure of the receiving sub-module RX1 in fig. 3, and the second control mode causes the data receiving buffer and the clock switching unit in at least one of the plurality of data receiving channels in the receiving sub-module RX0 to be turned off.

In some embodiments of the present disclosure, a control signal rx_lp is received, e.g., at the receiving sub-module RX0, e.g., the control signal rx_lp is provided by a physical layer functional module (e.g., PCS), such that the receiving sub-module RX0 quickly enters a low power consumption state in response to the control signal rx_lp. Since no valid data is transmitted after the physical layer interface module PHY0 enters the low power state, the control signal rx_lp may control the power switch of the data receiving driving buffer to be turned off. For example, the power supply switch 360 of the data reception buffer DR0 of the data reception channel 0 is turned off, thereby saving power consumption of the reception sub-module RX.

In some embodiments of the present disclosure, the receiving sub-module RX0 in the core DIE0 is in an on state in a data reception buffer in a target data reception channel of the plurality of data reception channels in a low power consumption state. The data receiving buffer in the target data receiving channel keeps an on state, and can timely receive the wake-up message provided by the other core particle DIE 1. The target data receiving channel may be one data receiving channel or a plurality of data receiving channels. For example, in order to wake up the receiving end RX0 of the core particle DIE0 in time, the receiving end RX0 of the core particle DIE0 reserves one data receiving channel in an open state, and the data channel in the open state is the target data receiving channel.

In other embodiments of the present disclosure, the receive sub-module RX0 may further comprise a sideband signal path, the receive state machine sub-module 260 being configured to: and receiving a wake-up message provided by another core particle through a sideband signal path. This embodiment may not require that at least one data channel and clock channel be left in an on state, but may require an additional sideband signal path.

In other embodiments of the present disclosure, the control message receiving sub-module 280 is further configured to send a wake-up message to the receive state machine sub-module 260 in response to the communication message being a wake-up message. The wake-up message is, for example, the FPMWake' message shown in fig. 2. The receiving state machine sub-module 260 is configured to switch a fourth control signal (e.g., the control signal rx_lp) to the first control mode in response to receiving the wake-up message, so as to control the receiving sub-module RX to enter the working state. The control message receiving sub-module 280 is further configured to provide a status exit message to the receiving state machine sub-module 260 in response to the communication message being a status exit message. The state exit message is, for example, the FPMExit' message shown in fig. 2. The receive state machine sub-module 260 is further configured to control the data message receive sub-module 270 to begin receiving the second data message in response to the state exit message.

For example, the receive state machine sub-module 260 sends a message receipt indication signal to the data message receipt sub-module in response to the state exit message to inform the data message receipt sub-module 270 that it is ready to receive the second data message.

Fig. 5 shows a block diagram of a physical layer coding module PCS or adaptation layer provided by at least one embodiment of the present disclosure.

The physical layer coding module PCS or the adaptation layer Adapter shown in fig. 5 is applied, for example, in the core grain DIE0 or the core grain DIE1 in fig. 2. The physical layer coding module PCS or the adaptation layer Adapter comprises a data message receiving and transmitting path and a control message receiving and transmitting path.

The data message receiving and transmitting path is used for providing data messages from the data bus module of the data message receiving and transmitting path to other core grains in a normal working state, receiving the data messages from the other core grains from the physical layer interface module PHY and providing the data messages to the data bus module of the data message receiving and transmitting path.

In connection with fig. 5 and 2, a physical layer coding module provided in at least one embodiment of the present disclosure is illustrated by taking the physical layer coding module PCS or the physical layer coding module of which the adaptation layer is the core DIE0 of fig. 2 as an example.

As shown in fig. 5, in the transmission path in the data messaging path, the PCS receives the data message txData provided by the data bus module, and sends the data message txData to a selector after processing (for example, performing processing such as checking and encoding) by the data message transmission sub-module 220. The selector selects the port D0 input when transmitting a data message, txData, which is provided to the txData signal line via which it is provided to the transmit sub-module TX0 of the physical layer interface module PHY 0.

As shown in fig. 2, after the receiving channel of another core DIE1 receives the data packet rxData from PHY0 (i.e., the data packet txData provided by DIE 0), the data packet rxData signal line is sent to the data packet receiving sub-module 2100 and the control packet receiving sub-module 2200, respectively.

Since a normal data message is received, the control message receiving sub-module 2200 outputs 0. The data packet receiving sub-module 2100 outputs the processed data packet rxData to the data bus module 2300.

As shown in fig. 5, for the receiving channel of the data packet transceiver channel of the core DIE0, after receiving the data packet rxData from the PHY1 (i.e., the data packet txData provided by DIE 1), the data packet rxData signal line is sent to the data packet receiving sub-module 270 and the control packet receiving sub-module 280, respectively.

Since a normal data message is received, the control message receiving sub-module 280 outputs 0. The data packet receiving sub-module 270 outputs the processed data packet rxData to the data bus module 250.

The control message receiving and transmitting path is used for exchanging control messages among PCS to quickly control entering and exiting the low-power consumption state.

As shown in fig. 5, in the transmit path in the control messaging path, the PCS receives the txfastpm_entry signal, i.e., txlowpower=1, from the data bus module to control the PCS to enter the low power mode quickly. The transmit state machine sub-module 210 in the PCS generates a tx_stop signal to control the data packet transmit sub-module 220 to Stop normal data transmission. The transmit state machine sub-module 210 controls the control message transmit sub-module 230 to transmit the fpmetric control message. The transmit state machine sub-module 210 outputs the txFastPM _ sel signal to the selector for controlling the selector to select the D1 path to provide the fpmetric control message. The fpmedium control message indicates that the transmitting sub-module TX is to enter a low power consumption state. The fpmedium control message is ultimately sent to another DIE dee 1 via the TXDATA signal line and physical link.

The transmit state machine sub-module 210 generates a tx_lp signal to control the transmit sub-module TX0 of the physical layer interface module PHY0 to quickly enter a low power state. PHY0 only reserves one data transmit lane (e.g., data transmit lane 0) and clock signal lane in transmit sub-module TX0 for wakeup, closes the other data transmit lanes in transmit sub-module TX0 and gates the transmit clock.

The communication message received by the other core DIE1 is sent to the data message receiving sub-module 2100 and the control message receiving sub-module 2200 of the core DIE 1. Since the fpmessage control message is received at this time, the control message receiving sub-module 2200 determines that the fpmessage is received, and the message is sent to the receiving state machine sub-module 2400 of the core DIE1, and the receiving state machine sub-module of the core DIE1 generates the rx_stop signal to control the data message receiving sub-module 2100 to stop receiving the data message. The receive state machine sub-module 2400 of the core DIE1 generates an rx_lp signal to control the circuit of the receive sub-module RX1 of the physical layer interface module PHY1 of the core DIE1 to enter the low power consumption state. The physical layer interface module PHY1 of the core DIE1 only reserves a data reception channel (e.g., data reception channel 0) and a clock signal channel of one reception sub-module for waking up, and closes other data reception channels of the reception sub-module.

If the transmit path receives the txfastpm_exit signal, i.e., txlowpower=0, from the data bus module, the PCS is controlled to quickly Exit the low power mode. The transmit state machine sub-module 210 pulls down the tx_lp signal, which controls the TX0 module of the PHY to quickly exit the low power mode. The transmit state machine sub-module 210 in the PCS will control the control message transmit sub-module 230 to transmit the FPMWake control message and the FPMExit control message. The FPMWake is used to wake up the counterpart receive state machine sub-module. The FPMExit control message is used to tell another core to resume data reception for the next clock cycle.

The transmit state machine sub-module 210 will pull down the tx_stop signal to control the data message transmit module to begin normal data transmission.

The other core particle DIE1 has only one data receiving channel and clock signal channel in an open state for receiving the FPMWake control message before receiving the FPMWake control message. After receiving the FPMWake control message, the control message receiving sub-module 2200 pulls down the rx_lp signal, and controls PHY1 to exit the low power state, and PHY1 opens all data receiving channels.

After receiving the FPMExit control message, the receive state machine sub-module 2400 pulls down the rx_stop signal to control the data message receiving module 2100 to start receiving the data message normally.

As shown in fig. 5, for the receiving channel of the control message transceiving path of the core particle DIE0, only one data receiving channel and clock signal channel are in an open state for receiving the FPMWake message before receiving the FPMWake control message. After receiving the FPMWake control message, the control message receiving sub-module 280 pulls down the rx_lp signal, and controls the PHY0 to exit the low power state, and PHY0 opens all data receiving channels.

After receiving the FPMExit control message, the receiving state machine sub-module 260 pulls down the rx_stop signal, and controls the data message receiving module 270 to start receiving the data message normally.

Fig. 6A illustrates a schematic diagram of a state machine of a transmit sub-module provided in at least one embodiment of the present disclosure. Fig. 6B illustrates a schematic diagram of a state machine of a receiving sub-module provided in at least one embodiment of the present disclosure.

As shown in fig. 6A, when the signal tx_lp=1, the transmitting submodule of the physical layer interface module quickly enters a low-power consumption state, and the IO power supply of the data channel of the transmitting submodule is turned off. When the signal tx_lp=0, the low power consumption state is quickly exited, and the IO power supply of the data channel of the transmitting sub-module is turned on.

As shown in fig. 6B, when the signal rx_lp=1, the receiving submodule of the physical layer interface module quickly enters a low-power consumption state, and the IO power supply of the data channel of the receiving submodule is turned off. When the signal tx_lp=0, the low power consumption state is quickly exited, and the IO power supply of the data channel of the receiving sub-module is turned on.

The core particle provided by at least some embodiments of the present disclosure controls the PHY to enter and exit the low power mode by the interaction of the transmitting and receiving parties to control messages, without requiring an additional chip pin. According to the embodiment of the disclosure, the logic of the sending state machine sub-module and the logic of the data bus module are used for realizing the interaction control message between the two parties, and no additional chip pins are needed. The extra chip pins not only increase the cost, but also bring inconvenience to the design of the chip. According to the embodiments of the present disclosure, through determining the time point when the PHY safely enters and exits the low power consumption mode after the negotiation of the transmitting and receiving sides, the IO power supply of the PHY can be safely turned off, so that more power consumption is saved than in the gated clock scheme. When the PHY enters fast low power consumption, turning off the analog drive buffer does not require retraining the PHY. And thus can quickly enter and exit the low power mode.

It should be noted that, in some embodiments, the clock signal channel remains open when the fast low power mode is entered, but the clock signal is turned off when the fast low power mode is entered and turned on when the fast low power mode is exited. In other embodiments of the present disclosure, transitions of the clock signal may be used to control the wake-up of the receiving sub-module at the receiving end.

Another embodiment of the present disclosure provides a method of controlling a pellet. The core particle comprises a physical layer functional module and a first physical layer interface module, wherein the first physical layer interface module is used for being electrically connected with a second physical layer interface module of another core particle through a physical link. The method comprises the following steps: and after the first physical layer interface module provides the first state entry message for the other core particle, controlling the first physical layer interface module to enter a low power consumption state from the working state, wherein the first state entry message is used for notifying the other core particle to enter the low power consumption state, and the power consumption of the first physical layer interface module in the low power consumption state is smaller than that in the working state.

According to the control method, the transmission state entering message of the physical link is controlled by the sending state machine submodule, so that the physical link can transmit not only the data message but also the state entering message, and therefore, the core particle can enter and exit the low-power consumption mode quickly without adding an extra pin.

For example, the physical layer function module may be a physical layer coding submodule or an adaptation layer. The adaptation layer is used to select and arbitrate between multiple protocols. The physical layer coding submodule is used for controlling the physical layer interface module to transmit and receive data. The physical layer interface module is responsible for signal transmission techniques related to the electrical characteristics. The physical link may be a wired link or a wireless link (e.g., optical fiber, etc.), and embodiments of the present disclosure do not specifically limit the form of the physical link.

For example, as shown in fig. 2, the physical layer function module PCA0 of the core DIE0 includes a transmit state machine sub-module 210, a data packet transmit sub-module 220, and a control packet transmit sub-module 230.

For the wake-up message and the state exit message, refer to the above description, and will not be repeated.

The control method is applied, for example, to the pellets provided in any of the foregoing embodiments. The control method corresponds to each part of the above-mentioned core particle, please refer to the description of the above-mentioned core particle.

FIG. 7A is a flowchart of a method for a transmitting end and a receiving end to quickly enter a low power consumption state according to at least one embodiment of the present disclosure; fig. 7B illustrates a timing diagram of a sender entering a low power consumption state quickly according to at least one embodiment of the present disclosure; fig. 7C illustrates a timing diagram of a receiving end quickly entering a low power consumption state according to at least one embodiment of the present disclosure.

The low power consumption state is hereinafter referred to as the "FastPM state". The FastPM state is initiated by the PCS of the sender (e.g., core particle DIE0 in FIG. 7A). The receiving end is, for example, the core particle DIE1 in fig. 7A.

As shown in fig. 7A, the method of entering the FastPM state includes steps S701 to S705.

Step S701: the data bus module of the transmitting end pulls up the txLowerPower signal, controls the PCS of the transmitting end to enter the txFastPM state, and stops receiving data from the data bus module. the txFastPM state indicates that the transmitting sub-module is to enter a low power state. At the beginning, the transmitting sub-module TX of the transmitting end is in a normal operating state. "TX" in fig. 7A represents a transmitting sub-module, and "RX" represents a receiving sub-module.

After the data bus module of DIE0 sends the TxLowPower signal after being pulled up, no data is sent. Therefore, the transmission direction of the data bus module is in an idle state at this time.

Step S702: the PCS of the transmitting end transmits the FPMEntry control message.

Step S703: after the PCS of the transmitting end transmits the FPMEntry control message, the PCS of the transmitting end pulls up the TX_LP signal to control the PHY of the transmitting end to enter a txFastPM state, namely, a transmitting sub-module of the transmitting end is idle, and the PHY performs clock gating.

Step S704: after receiving the FPMEntry control message, the PCS of the receiving end controls the PCS of the receiving end to enter an rxFastPM state, and the PCS of the receiving end stops receiving data from the PHY of the receiving end to the data bus module of the receiving end. The rxFastPM state indicates that the receiving sub-module is entering a low power consumption state.

Step S705: the PCS of the receiving end pulls up the RX_LP control signal to control the PHY of the receiving end to enter into an rxFastPM state, namely a receiving submodule RX of the receiving end is idle.

The data bus module of DIE1 receives rxvalid=0, and no valid data is received, so the receiving direction of the data bus module of DIE1 is also in an idle state.

As shown in fig. 7B, first, for example, on the rising edge of the ith Clock cycle of the Clock signal Clock (i is an integer greater than or equal to 1), the txLowPower signal is pulled up by the data bus module of the transmitting end, so as to control the transmitting state machine of the PCS of the transmitting end to enter the low power consumption state from the normal operation state, and stop transmitting the data packet. Thereafter, for example, the i+1th clock cycle, the fpmetric message is sent by the PCS of the transmitting side through the TXDATA signal line. In the i+2 clock period, the PCS of the transmitting end pulls TX_LP high. In the (i+3) clock period, the PHY of the transmitting end enters a low power consumption state from a normal working state.

As shown in fig. 7C, for example, first, in j clock cycles, the fpmetric message is received through the RXDATA signal line in the PCS of the receiving end. In response to detecting the FPMEntry message, an rxFastPM state is entered and receipt of the data message is stopped. Thereafter, the PCS at the receiving end pulls the RX_LP signal high. Finally, the PHY of the receiving end enters the rxFastPM state. j is an integer greater than i+1.

FIG. 8A is a flow chart illustrating a method for a sender and a receiver to exit a fast low power state according to at least one embodiment of the present disclosure; fig. 8B illustrates a timing diagram of a sender exiting a low power state quickly provided by at least one embodiment of the present disclosure; fig. 8C illustrates a timing diagram for a receiving end to quickly exit a low power consumption state according to at least one embodiment of the present disclosure.

As shown in FIG. 8A, the method of exiting the FastPM state includes steps S801-S807.

Step S801: the data bus module of the transmitting end pulls down the txLowerPower signal to control the PCS of the transmitting end to exit the txFastPM state.

Step S802: the PCS of the transmitting end pulls down the TX_LP control signal to control the PHY of the transmitting end to exit the txFastPM state.

Step S803: the PCS of the transmitting end transmits the FPMWake control message.

Step S804: and after the PCS of the receiving end receives the FPMWake control message, controlling the PCS of the receiving end to exit the rxFastPM state.

Step S805: the PCS of the receiving end pulls down the RX_LP control signal to control the PHY of the receiving end to exit the rxFastPM state.

Step S806: the PCS of the transmitting end transmits the FPMExit control message and starts transmitting the data message.

Step S807: after receiving the FPMExit control message, the PCS of the receiving end starts to receive the data message.

As shown in fig. 8B, first, for example, on the rising edge of the m (m is an integer greater than or equal to 1) Clock period of the Clock signal Clock, the txLowPower signal is pulled down by the data bus module of the transmitting end, so as to control the receiving state machine in the PCS of the transmitting end to exit the low power consumption state and enter the awake state. Then, for example, in the (m+1) th clock period, the PCS of the transmitting end pulls down the TX_LP control signal to control the PHY of the transmitting end to exit from the low power consumption state and enter into the normal working state. For example, in the i+2 clock cycle, the transmitting end PHY exits the low power consumption state in response to the low level signal of tx_lp. And after the PHY of the transmitting end exits the low-power-consumption state and enters the working state, the effective data message starts to be transmitted.

As shown in fig. 8C, for example, first, in n clock cycles, the PCS at the receiving end receives the FPMWake message through the RXDATA signal line, exits the low power consumption working state, and enters the awake state. Afterwards, the PCS of the receiving end pulls down the rx_lp signal to control the PHY of the receiving end to exit the low power consumption state. After the PCS of the receiving end pulls down the RX_LP signal, the PHY of the receiving end exits the low power consumption state. Finally, the PCS of the receiving end sends an FPMExit control message, enters a working state and starts to normally receive data. n is an integer greater than m+1.

Fig. 9A illustrates a flow diagram of a state jump of a transmit state machine provided by at least one embodiment of the present disclosure. For example, the transmit state machine sub-module performs control operations in accordance with the transmit state machine shown in fig. 9A.

As shown in fig. 9A, the state jump of the transmission state machine includes steps S901 to S907.

Step S901: the transmit state machine is in the txfpm_idle state. The txfpm_idle state indicates that the transmitting end is in an initial state, that is, is in a state of transmitting a data packet when the control signal txLowPower entering the low power consumption of the bus module is not received.

Step S902: when the control signal txLowPower sent to the PCS by the data bus sending module of the sending end is at a high level (i.e., txlowpower= 1), the PCS sends the fpmetric control message. The PCS at the receiving end is notified to enter the FastPM state.

Step S903: and after the FPMEntry control message is sent, entering a TXFPM_ENTRY_WAIT state. The TXFPM_ENTRY_WAIT state represents a WAIT state before entering the FastPM state. At this time, waiting for a preset time, if txLowPower is switched to a low level (i.e., txlowpower= 0) for the preset time, then jumping to the txfpm_exit_wake state. Or in the waiting preset time, if the cyclic redundancy check (Cyclic redundancy check, CRC) error of the receiving end occurs, the receiving end also EXITs to the TXFPM_EXIT_WAKE state, and the receiving state machine submodule of the receiving end is informed to stop the flow of entering the rxFastPM state. The internal circuitry of the transmit sub-module in the txfpm_exit_wake state PHY is turned on.

Step S904: after waiting for a preset time in the txfpm_entry_wait state, the method jumps to the txfpm_entry_done state, i.e., enters the txFastPM state. The receiving sub-module of the PHY of the transmitting end is turned off. The preset time may be set by one skilled in the art himself.

Step S905: when txLowPower switches low, it is indicated that the data bus control module is controlling the PCS to exit the txFastPM state. The transmit state machine jumps to the txfpm_exit_wake state. And in the TXFPM_EXIT_WAKE state, turning on TX of the PHY and sending an FPMWake control message.

Step S906: the FPMWake control message enters the TXFPM_EXIT_SENT state after transmission. In the TXFPM_EXIT_SENT state, the sender starts to send an FPMExit control message.

Step S907: after the FPMExit control message is sent, the TXFPM_EXIT_DONE state is entered to completely EXIT the txFastPM state.

The final transmit state machine reverts to the txfpm_idle state.

Fig. 9B illustrates a flow diagram of a state jump of a receive state machine provided by at least one embodiment of the present disclosure. For example, the receive state machine sub-module performs control operations in accordance with the receive state machine shown in fig. 9B.

As shown in fig. 9B, the state jump of the receiving state machine includes steps S910 to S950.

Step S910: the receive state machine is initially in rxfpm_idle state (i.e., initial state).

Step S920: after receiving the FPMEntry control message, the receiving state machine enters the RXFPM_ENTRY_WAIT state. If the FPMWake control message is received in the rxfpm_entry_wait state, the process proceeds to step S940. If the preset time is waited in the rxfpm_entry_wait state, the process goes to step S930. The preset time may be set by one skilled in the art himself.

Step S930: the receive state machine enters the rxfpm_entry_done state. In the rxfpm_entry_done state, the receive submodule of the PHY of the receiving end is turned off.

Step S940: the receive state machine enters the rxfpm_entry_wake state (i.e., awake state), exits the rxFastPM state, and turns on the internal circuitry of the receive sub-module of the receive end PHY.

Step S950: and after receiving the FPMExit control message, entering the RXFPM_EXIT_DONE state and completely exiting the rxFastPM state.

The final receive state machine reverts to rxfpm_idle state.

The following points need to be described:

(1) The drawings of the embodiments of the present disclosure relate only to the structures to which the embodiments of the present disclosure relate, and reference may be made to the general design for other structures.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. A core particle comprising a physical layer functional module and a first physical layer interface module, wherein the first physical layer interface module is used for being electrically connected with a second physical layer interface module of another core particle through a physical link,

the physical layer function module comprises a sending state machine sub-module, a data message sending sub-module and a control message sending sub-module, wherein the data message sending sub-module is configured to provide a first data message for the first physical layer interface module, the control message sending sub-module is configured to provide a first state entering message for the first physical layer interface module,

the transmit state machine submodule is configured to:

Receiving a first control signal;

in response to the first control signal switching from a second mode to a first mode, controlling the physical layer functional module to switch from providing the first data message to the first physical layer interface module to providing a first state entry message to the first physical layer interface module, so that the first physical layer interface module switches from providing the first data message to the other core particle through the physical link to providing the first state entry message to the other core particle through the physical link; and

after the first physical layer interface module provides the first state entry message for the other core particle, the first physical layer interface module is controlled to enter a low power consumption state from a working state, wherein the first state entry message is used for notifying the other core particle to enter the low power consumption state, the power consumption of the first physical layer interface module in the low power consumption state is smaller than that in the working state,

in the low power state of the first physical layer interface module, the first physical layer interface module includes a target data channel that is kept in an open state or includes a sideband signal path to wake up the second physical layer interface module through the target data channel or the sideband signal path.

2. The core particle of claim 1, wherein the first physical layer interface module comprises a transmit sub-module electrically coupled to the transmit state machine sub-module,

the transmit state machine submodule is configured to control the transmit submodule to enter the low-power-consumption state from the operational state in response to a first mode of the first control signal.

3. The core particle of claim 2, wherein the control message transmitting sub-module is further configured to provide a wake-up message and a state exit message to the transmitting sub-module,

the transmit state machine sub-module is further configured to:

responding to the first control signal to switch from the first mode to the second mode, and controlling the sending sub-module to exit the low-power consumption state and enter the working state;

controlling the control message sending sub-module to provide the wake-up message for the sending sub-module, so that the sending sub-module provides the wake-up message for the other core particle to inform the second physical layer interface module to enter a working state;

and controlling the control message sending sub-module to provide the state exit message for the sending sub-module, so that the sending sub-module provides the state exit message for another core particle to inform the other core particle of recovering the receiving of the first data message in the next clock cycle.

4. The core particle of claim 3, wherein the transmit state machine submodule is further configured to: providing a third control signal to the transmitting sub-module to enable the transmitting sub-module to enter the low power consumption state from the working state,

the transmitting sub-module is in the working state in response to the third control signal being in the first control mode, and is in the low power consumption state in response to the third control signal being in the second control mode.

5. The core particle of claim 4, wherein said second control mode causes at least a portion of the circuit structure in said transmit sub-module to be off, causing said transmit sub-module to be in said low power state, said first control mode causes said at least a portion of the circuit structure to be on, causing said transmit sub-module to be in said operational state,

the second control mode causes at least part of circuit structures in the sending sub-module to be closed, and the method comprises the following steps:

the second control mode enables circuit structures in data transmission channels except the target data channel in the plurality of data transmission channels in the transmission sub-module to be closed; or alternatively

The transmit sub-module further includes the sideband signal path, and the second control mode causes each circuit structure in the plurality of data transmit channels in the transmit sub-module to be closed.

6. The core particle of claim 5, wherein the transmit sub-module further comprises a phase locked loop, a clock phase control unit, and a clock switching unit, the plurality of data transmit channels each comprising a data drive buffer and a parallel to serial conversion unit coupled to the data drive buffer, the parallel to serial conversion unit configured to convert parallel data to serial data to provide the serial data to the data drive buffer, each data drive buffer coupled to the physical link,

the phase-locked loop is connected with the clock phase control unit, the clock switch unit is connected with the clock phase control unit and the parallel-serial conversion unit,

the phase locked loop is configured to generate a clock signal, the clock phase control unit is configured to control a phase of the clock signal, and after the phase control of the clock signal, the clock signal is provided to the clock switching unit, the clock switching unit is configured to provide the clock signal to the parallel-to-serial conversion unit,

The at least part of the circuit structure comprises: a data driving buffer in at least one of the plurality of data transmission channels and the clock switching unit.

7. The core particle of claim 6, wherein the transmit sub-module is in an on state for a data-driven buffer in a target data lane of the plurality of data transmit lanes in the low power state,

the sending state machine submodule is configured to provide the wake-up message to the other core particle through a data drive buffer in the target data channel; or alternatively

The transmit state machine sub-module is configured to provide the wake-up message to the other core via the sideband signal path.

8. The core particle of claim 1, wherein the physical layer function further comprises a selector comprising a first input, a second input, a third input, and an output,

the data message sending sub-module is connected with the first input end, the control message sending sub-module is connected with the second input end, the output end is connected with the physical layer interface module,

the transmit state machine sub-module is further configured to provide a second control signal to the third input,

The selector is configured to:

and selecting the data message provided by the data message sending sub-module or the control message provided by the control message sending sub-module from the output end to the first physical layer interface module according to the second control signal.

9. The core particle of claim 1, wherein the transmit state machine submodule is further configured to:

responding to a first mode of the first control signal, and providing a message stop receiving signal for the data message sending sub-module;

the data message sending submodule is configured to: and responding to the message stop receiving signal, and stopping receiving the first data message.

10. The core particle of claim 3, further comprising:

and the data bus module is configured to provide the first data message and the first control signal for the physical layer functional module.

11. The core particle of claim 10, wherein the data bus module is further configured to:

counting the number of invalid data; and

and triggering the first control signal to switch to the first mode in response to the number of invalid data being greater than a first preset threshold.

12. The core particle of claim 11, wherein the data bus module comprises a data buffer for storing the first data packet provided to the physical layer function module, the data bus module further configured to:

Counting the number of effective data in the data buffer; and

and triggering the first control signal to switch to the second mode in response to the number of the effective data reaching a second preset threshold so as to provide the first data message for the physical layer interface module.

13. The core particle of claim 10, wherein the physical layer function module further comprises a receive state machine sub-module, a data message receive sub-module, and a control message receive sub-module,

the first physical layer interface module is further configured to: receiving a communication message provided from the other core particle and providing the communication message to the data message receiving sub-module and the control message receiving sub-module,

the data message receiving submodule is configured to: the communication message is received and the message is sent to the server,

the control message receiving sub-module is configured to: receiving the communication message and providing the second state entry message to the receive state machine sub-module in response to the communication message being the second state entry message,

the receive state machine module is configured to: and responding to the second state entering message, controlling the data message receiving sub-module to stop receiving the second data message, and controlling the first physical layer interface module to be switched from the working state to the low power consumption state.

14. The core particle of claim 13, wherein the data message receiving sub-module provides the second data message to the data bus module in response to the communication message being the second data message.

15. The core particle of claim 13, wherein the first physical layer interface module comprises a receive sub-module coupled to the receive state machine sub-module,

the receive state machine sub-module is configured to: and controlling the receiving sub-module to be switched from the working state to the low-power consumption state.

16. The core particle of claim 15, wherein the receive state machine submodule is further configured to: providing a fourth control signal to the receiving sub-module to enable the receiving sub-module to enter the low power consumption state from the working state,

and the receiving sub-module is in the working state in response to the fourth control signal being in the first control mode, and is in the low power consumption state in response to the fourth control signal being in the second control mode.

17. The core particle of claim 16, wherein the second control mode causes at least a portion of the circuit structure in the receiving sub-module to be off, causing the receiving sub-module to be in the low power state, the first control mode causes the at least a portion of the circuit structure to be on, causing the receiving sub-module to be in the operational state,

The receiving sub-module comprises a plurality of data receiving channels for transmitting the data message, and the second control mode enables at least part of circuit structures in the receiving sub-module to be closed, and the method comprises the following steps:

the second control mode causes a circuit structure in a data receiving channel other than a target data receiving channel among the plurality of data receiving channels in the receiving sub-module to be turned off; or the receiving sub-module further comprises the sideband signal path, and the second control mode causes each circuit structure in the plurality of data receiving channels in the receiving sub-module to be turned off.

18. The core particle of claim 17, wherein the receive sub-module comprises a clock phase control unit and a clock switching unit, the plurality of data receive channels each comprising a data receive buffer and a serial-to-parallel conversion unit, each data receive buffer being coupled to the physical link, the serial-to-parallel conversion unit being coupled to the data receive buffer, the serial-to-parallel conversion unit being configured to receive serial data provided by the data receive buffer and to convert the serial data to parallel data,

the clock switch unit is connected with the clock phase control unit and connected with the serial-parallel conversion unit,

The clock phase control unit is configured to receive a clock signal, control a phase of the clock signal, and after the phase control of the clock signal, provide the clock signal to the clock switching unit, the clock switching unit is configured to provide the clock signal to the serial-parallel conversion unit,

the at least part of the circuit structure comprises: a data reception buffer in at least one of the plurality of data reception channels and the clock switching unit.

19. The core particle of claim 16, wherein the control message receiving sub-module is further configured to:

responding the communication message as the awakening message, sending the awakening message to the receiving state machine submodule,

the receive state machine sub-module is configured to: responding to the received awakening message, and switching the fourth control signal into the first control mode so as to control the receiving sub-module to enter the working state;

the control message receiving sub-module is further configured to: providing the exit message to the receiving state machine sub-module in response to the communication message being the state exit message,

The receive state machine sub-module is further configured to: and responding to the state exit message, and controlling the data message receiving sub-module to start receiving the second data message.

20. A control method of a core particle, wherein the core particle comprises a physical layer functional module and a first physical layer interface module, the first physical layer interface module is used for being electrically connected with a second physical layer interface module of another core particle through a physical link,

the method comprises the following steps:

controlling the physical layer function module to switch from providing a first data message to the first physical layer interface module to providing a first state entry message to the first physical layer interface module in response to a first mode of a first control signal, causing the first physical layer interface module to switch from providing the first data message to the other core particle via the physical link to providing the first state entry message to the other core particle via the physical link, and controlling the first physical layer interface module to enter a low power consumption state from an operating state after the first physical layer interface module provides the first state entry message to the other core particle,

wherein the first state entry message is used for notifying the other core particle to enter the low power consumption state, the power consumption of the first physical layer interface module in the low power consumption state is smaller than that in the working state,