CN115756144A

CN115756144A - Power consumption control device and method and high-speed interconnection interface

Info

Publication number: CN115756144A
Application number: CN202211476091.7A
Authority: CN
Inventors: 梁岩
Original assignee: Chengdu Haiguang Microelectronics Technology Co Ltd
Current assignee: Chengdu Haiguang Microelectronics Technology Co Ltd
Priority date: 2022-11-23
Filing date: 2022-11-23
Publication date: 2023-03-07

Abstract

The embodiment of the invention discloses a power consumption control device, a power consumption control method and a high-speed interconnection interface, wherein the device arranged on the transmitting end side of the high-speed interconnection interface comprises the following components: the interface power consumption management state machine is used for controlling the sending end to enter or exit the low power consumption state and inputting different enabling signals to the clock gating unit when the high-speed interconnection interface needs to enter or exit the low power consumption state; and the clock gating unit is used for controlling the transmission of the local clock signal of the sending end to be closed and opened through the enabling signal of the interface power consumption management state machine so as to enable the sending end to: and the local clock signal of the sending end controlled by the clock gating unit is sent to the receiving end through a clock transmission channel, and the data is sent to the receiving end through a data transmission channel based on the local clock signal of the sending end controlled by the clock gating unit. The embodiment of the invention can be suitable for the scene of the management of the power consumption state of the high-speed interconnection interface and can realize the quick switching of the low-power consumption state of the high-speed interconnection interface.

Description

Power consumption control device and method and high-speed interconnection interface

Technical Field

The invention relates to the field of high-speed interconnection, in particular to a power consumption control device and method and a high-speed interconnection interface.

Background

Conventional high-speed interconnect interfaces (e.g., chiplets) classify states according to power consumption: PD (Power Down), PQ (Power quiet), PA (Power Active), etc. These states are switched cyclically according to the requirements of the upper layer protocol, so-called power management.

The PA is a state in data transmission of the high-speed interconnect interface, and power consumption is relatively large in this state. If the data is not transmitted for a long time, the high-speed interconnection interface needs to enter a PQ or PD state from a PA state so as to reduce power consumption, and then enters the PA state from the PQ state again when the data is transmitted next time. The high-speed interconnection interface has a high speed when switching the state, otherwise the average power consumption of the whole system is large.

However, in the prior art, the switching time of the high-speed interconnection interface state is relatively long, and especially, the fast switching of the low-power consumption state cannot be realized.

Disclosure of Invention

In view of this, embodiments of the present invention provide a power consumption control apparatus and method, and a high-speed interconnect interface, so as to implement fast switching of a low power consumption state of the high-speed interconnect interface.

In a first aspect, an embodiment of the present invention provides a power consumption control device, which is disposed on a transmission end side of a high-speed interconnect interface, where the device includes:

an interface power management state machine to: when the high-speed interconnection interface needs to enter a low-power-consumption state, controlling a sending end of the high-speed interconnection interface to enter the low-power-consumption state, and inputting a first enabling signal to a clock gating unit; when the high-speed interconnection interface needs to exit the low-power-consumption state, controlling a sending end of the high-speed interconnection interface to exit the low-power-consumption state, and inputting a second enabling signal to the clock gating unit;

a clock gating unit to: controlling the transmission of a local clock signal of a transmitting end of the high-speed interconnection interface to be switched off and switched on through the first enable signal and the second enable signal so that the transmitting end of the high-speed interconnection interface performs the following operations: and the local clock signal of the sending end controlled by the clock gating unit is sent to the receiving end through a clock transmission channel, and the data is sent to the receiving end through a data transmission channel based on the local clock signal of the sending end controlled by the clock gating unit.

Further, the interface power consumption management state machine is further configured to: and determining that the high-speed interconnection interface needs to enter or exit a low-power consumption state according to the power consumption requirement of the upper layer protocol.

Further, the interface power consumption management state machine is used for controlling the sending end of the high-speed interconnection interface to enter a low power consumption state, and includes:

and after the first enabling signal is input into the clock gating unit, waiting for a preset time length, and controlling a sending end of the high-speed interconnection interface to enter a low-power consumption state after the waiting is finished.

In a second aspect, an embodiment of the present invention provides another power consumption control apparatus, which is disposed on a receiving side of a high-speed interconnect interface, where the apparatus includes a receiving-end power consumption control unit, configured to:

detecting whether a receiving end of the high-speed interconnection interface receives a sending end clock signal through a clock transmission channel;

and controlling the receiving end of the high-speed interconnection interface to enter or exit a low power consumption state according to the detection result, wherein the receiving end of the high-speed interconnection interface processes the sending end data received through the data transmission channel based on the sending end clock signal.

Further, the receiving end power consumption control unit is used for controlling the receiving end of the high-speed interconnection interface to enter or exit the low power consumption state according to the detection result, and includes:

outputting a first control signal to control the data receiving enabling end of the receiving end of the high-speed interconnection interface to be invalid after detecting the existence of the received clock signal of the sending end;

and outputting a second control signal after detecting that the received clock signal of the sending terminal is available, so as to control the data receiving enabling terminal of the receiving terminal of the high-speed interconnection interface to be effective.

Further, the receiving-end power consumption control unit includes: a write clock signal terminal for inputting the received clock signal of the transmitting terminal; the read clock signal end inputs a receiving end local clock control signal; a null signal terminal outputting a null signal as the first control signal or the second control signal; wherein, the first and the second end of the pipe are connected with each other,

after the clock signal of the receiving end is from the existence to the nonexistence, the writing pointer stops counting, the reading pointer continues to increase under the drive of the reading clock until the reading pointer is equal, the power consumption control unit of the receiving end is read empty, an output signal is used as an empty signal of a first control signal, and the empty signal is synchronized to a reading clock domain by a synchronizer and is used for controlling the reading pointer;

and after the received clock signal of the sending end is available, the write pointer starts counting, the read pointer starts counting when the control signal output by the synchronizer becomes effective, the read pointer and the write pointer are unequal, and a null signal serving as a second control signal is output.

Further, the receiving end power consumption control unit further includes a synchronizer for synchronizing the null signal output by the receiving end power consumption control unit to the read clock domain to control the read pointer, and the read pointer can be changed only when the output signal of the synchronizer is high.

Further, the synchronizer includes at least one stage of D flip-flops, wherein, when the D flip-flops are cascaded in multiple stages, in a signal end of the cascaded D flip-flops:

the input end D of the first-stage D trigger is connected with a high level; the input end D of the next-stage D trigger is connected with the output end Q of the previous-stage D trigger; the output end Q of the last stage D trigger is connected with the read enabling end of the receiving end power consumption control unit;

the signal input by the clock terminal Clk of each stage of trigger is obtained according to the local clock signal of the receiving terminal, and the Reset terminal Reset is connected with the empty signal terminal of the power consumption control unit of the receiving terminal.

In a third aspect, an embodiment of the present invention provides a power consumption control apparatus, including: the power consumption control apparatus according to the first aspect; and a power consumption control apparatus as described in the second aspect above.

In a fourth aspect, an embodiment of the present invention provides a high-speed interconnect interface, including: the transmitting terminal, the receiving terminal, the data transmission channel and clock transmission channel to connect the receiving and transmitting terminal; and the power consumption control device according to the third aspect.

Further, the sending end includes:

the first asynchronous FIFO memory is used for storing sending end data, wherein a writing clock signal end of the first asynchronous FIFO memory inputs a sending end local clock signal, and a reading clock signal end inputs a clock signal output by the data serial-parallel converter;

a data serial-to-parallel converter respectively connected with the first asynchronous FIFO memory, the data transmitter and the clock gating unit, and used for: reading sending end data in the first asynchronous FIFO memory, performing serial-parallel conversion on the data and outputting the data to a data transmitter; the clock signal output by the clock gating unit is subjected to serial-parallel conversion and then output to the first asynchronous FIFO memory;

the data transmitter is connected with the data transmission channel and used for driving the data transmission channel and transmitting the serial-parallel converted data of the transmitting end to a receiving end of the high-speed interconnection interface through the data transmission channel;

the adjusting unit is connected with the clock gating unit and used for outputting the local clock signal of the sending end to the clock gating unit after frequency multiplication and phase modulation processing;

the clock serial-parallel converter is respectively connected with the clock gating unit and the clock transmitter and is used for performing serial-parallel conversion on the clock signal output by the clock gating unit and outputting the clock signal to the clock transmitter;

and the clock transmitter is used for driving the clock transmission channel and transmitting the clock signal after serial-parallel conversion to the receiving end of the high-speed interconnection interface through the clock transmission channel.

Further, the receiving end includes:

the data receiver is used for driving a data transmission channel and receiving the data of the sending end;

a data clock deserializer respectively connected to the clock receiver, the data receiver, and the second asynchronous FIFO memory for: carrying out serial-parallel conversion on the sending end clock signal received by the clock receiver and the sending end data received by the data receiver, and outputting the serial-parallel conversion to a second asynchronous FIFO memory;

the second asynchronous FIFO memory is used for synchronizing the sending end data subjected to serial-parallel conversion by the data clock data serial-parallel converter to the receiving end local clock so as to complete clock domain conversion, wherein a writing clock signal end of the second asynchronous FIFO memory inputs the clock signal output by the serial-parallel converter, and a reading clock signal end of the second asynchronous FIFO memory inputs the receiving end local clock signal;

and the clock receiver is connected with the receiving end power consumption control unit and the data clock serial-parallel converter and is used for driving the clock transmission channel, receiving the clock signal sent by the sending end and outputting the clock signal to the receiving end power consumption control unit and the data clock serial-parallel converter.

Further, the interface is a chiplet interconnection interface.

In a fifth aspect, an embodiment of the present invention provides a power consumption control method, which is applied to the power consumption control apparatus in the first aspect, and the method includes:

when the high-speed interconnection interface needs to enter a low-power-consumption state, the interface power consumption management state machine controls a sending end of the high-speed interconnection interface to enter the low-power-consumption state and inputs a first enabling signal to the clock gating unit; when the high-speed interconnection interface needs to exit the low-power-consumption state, controlling a sending end of the high-speed interconnection interface to exit the low-power-consumption state, and inputting a second enabling signal to the clock gating unit;

the clock gating unit controls the transmission of a local clock signal of a sending end to be closed and opened through a first enabling signal and a second enabling signal, so that the sending end of the high-speed interconnection interface can execute the following operations: and the local clock signal of the sending end controlled by the clock gating unit is sent to the receiving end of the high-speed interconnection interface through a clock transmission channel, and the data is sent to the receiving end of the high-speed interconnection interface through a data transmission channel based on the local clock signal of the sending end controlled by the clock gating unit.

Further, the method further comprises:

and the interface power consumption management state machine determines that the high-speed interconnection interface needs to enter or exit the low power consumption state according to the power consumption requirement of the upper layer protocol.

Further, the interface power consumption management state machine controls the sending end of the high-speed interconnection interface to enter a low power consumption state, and the method comprises the following steps:

In a sixth aspect, an embodiment of the present invention provides another power consumption control method, which is applied to the power consumption control apparatus in the second aspect, and the method includes:

detecting whether a receiving end of a high-speed interconnection interface receives a clock signal of a sending end through a clock transmission channel;

Further, controlling the receiving end of the high-speed interconnection interface to enter or exit the low power consumption state according to the detection result, comprising:

According to the technical scheme provided by the embodiment of the invention, under the condition that the cost of other data transmission channels is not additionally increased, the power consumption requirement information is carried by controlling whether the local clock signal of the sending end exists or not, and then the sending end and the receiving end are controlled to enter or exit from the low power consumption state, so that the quick switching of the low power consumption state of the high-speed interconnection interface is realized, the average power consumption of the high-speed interface is reduced, and the method and the device are particularly suitable for the interconnection requirements of low power consumption, high bandwidth and low delay.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of a high-speed interconnect interface transmitting end side device according to an embodiment of the present invention;

fig. 2a is a schematic structural diagram of a high-speed interconnect interface receiving end-side device according to a second embodiment of the present invention;

fig. 2b is a schematic structural diagram of a synchronizer according to a second embodiment of the present invention;

fig. 2c is a schematic diagram of a timing relationship between signals of a high-speed interconnect interface receiving end side power consumption control apparatus according to a second embodiment of the present invention.

Fig. 3 is a schematic structural diagram of a high-speed interconnect interface according to a third embodiment of the present invention;

fig. 4 is a schematic diagram of a timing relationship between signals of a high-speed interconnect interface according to a third embodiment of the present invention.

Detailed Description

Embodiments of the present invention are described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example one

An embodiment of the present invention provides a high-speed interconnect interface transmitting end side apparatus, and referring to fig. 1, the transmitting end side apparatus includes a power consumption control apparatus 10 and a transmitting end (including a data transmitting module 11 and a clock transmitting module 12) which are arranged on the transmitting end side of the high-speed interconnect interface. Wherein, the power consumption control device 10 includes:

an interface power management state machine 101 to: when the high-speed interconnection interface needs to enter a low power consumption state, controlling a sending end (specifically, a data sending module 11) of the high-speed interconnection interface to enter the low power consumption state, and inputting a first enabling signal to the clock gating unit 102; when the high-speed interconnection interface needs to exit the low-power-consumption state, controlling a sending end (specifically, the data sending module 11) of the high-speed interconnection interface to exit the low-power-consumption state, and inputting a second enabling signal to the clock gating unit 102;

a clock gating unit 102 to: the method comprises the following steps of controlling the turning off and turning on of local clock signal transmission of a transmitting terminal through a first enabling signal and a second enabling signal so as to enable the transmitting terminal (specifically the clock transmitting module 12) of the high-speed interconnection interface to execute the following operations: the local clock signal of the sending end controlled by the clock gating unit 102 is sent to the receiving end of the high-speed interconnection interface through the clock transmission channel, and the data is sent to the receiving end of the high-speed interconnection interface through the data transmission channel based on the local clock signal of the sending end controlled by the clock gating unit 102.

The two enable signals input by the interface power consumption management state machine 101 to the clock gating unit 102 may be respectively distinguished by the level of the level signal voltage, for example, a high level signal is input to the clock gating unit 102 as a first enable signal, and a low level signal is input to the clock gating unit 102 as a second enable signal. The clock gating unit 102 controls the transmission of the local clock signal of the transmitting end to be closed after receiving the first enable signal, and controls the transmission of the local clock signal of the transmitting end to be opened after receiving the second enable signal. Therefore, the clock signal transmitted to the receiving end by the transmitting end of the high-speed interconnection interface through the clock transmission channel is not a continuous but a local clock signal of the transmitting end, and whether the clock signal can be received by the receiving end of the high-speed interconnection interface identifies the power consumption requirement information carried in the clock signal is the following: whether the low power consumption state is exited or entered, and then the power consumption state of the receiving end is switched according to the power consumption requirement. It should be noted that the clock gating unit 102 may control the transmission closing period of the local clock signal of the transmitting end, and may also control the clock transmission channel to transmit other non-clock signals, as long as the receiving end of the high-speed interconnect interface receives other non-clock signals transmitted by the transmitting end through the clock transmission channel, it may be determined that the signal is no longer the local clock signal of the transmitting end, for example, the clock gating unit 102 controls the transmission closing period of the local clock signal of the transmitting end to keep transmitting low-level signals.

In the embodiment of the present invention, the gated clock of the clock gating unit 102 has two input clock signals: one is the sending-end local clock signal shown in fig. 1, which may be generated by the sending-end local clock, then input to the clock gating unit 102 after frequency multiplication and phase modulation, and the clock gating unit 102 controls the on/off of its transmission; the other is a clock signal (not shown in fig. 1) for normal operation of the clock gating cell 102, which may be generated by the transmit-side local clock and then input directly to the clock gating cell 102.

Further, the interface power consumption management state machine 101 is further configured to: and determining that the high-speed interconnection interface needs to enter or exit a low-power consumption state according to the power consumption requirement of the upper layer protocol.

As a preferred embodiment, in order to ensure the correctness of data transmission, when the low power consumption state needs to be entered, it should be ensured that the receiving end of the high-speed interconnection interface preferentially stops receiving data from the sending end, and then the sending end of the high-speed interconnection interface stops sending data to the receiving end of the high-speed interconnection interface. Correspondingly, the interface power consumption management state machine 101 is configured to control the sending end of the high-speed interconnect interface to enter a low power consumption state, and includes: after the first enable signal is input to the clock gating unit 102, a preset time duration is waited, and after the waiting is finished, the sending end (specifically, the data sending module 11) of the high-speed interconnect interface is controlled to exit from the low power consumption state. Wherein, the preset duration is longer than the following duration: the interface power consumption management state machine 101 inputs the first enable signal to the clock gating unit 102, until the receiving end of the high-speed interconnect interface completes the switching of the power consumption state of the receiving end according to the clock signal sent by the sending end under the control of the first enable signal, which may be specifically set by a person skilled in the art according to needs and actual situations.

It should be noted that, in this embodiment, the power consumption control device 10 may be configured as a part of a transmitting end of the high-speed interconnection interface and disposed inside the transmitting end of the high-speed interconnection interface, and of course, part or all of components of the power consumption control device 10 may also be separately disposed outside the transmitting end of the high-speed interconnection interface, which is not limited in this respect.

Correspondingly, the present embodiment further provides a power consumption control method, which is applied to the power consumption control apparatus in the present embodiment, and the method includes:

when the high-speed interconnection interface needs to enter a low-power-consumption state, the interface power consumption management state machine controls the sending end to enter the low-power-consumption state and inputs a first enabling signal to the clock gating unit; when the high-speed interconnection interface needs to exit the low-power-consumption state, controlling the sending end to exit the low-power-consumption state, and inputting a second enabling signal to the clock gating unit;

the clock gating unit controls the transmission of a local clock signal of the sending end to be closed and opened through a first enabling signal and a second enabling signal, so that the sending end performs the following operations: and the local clock signal of the sending end controlled by the clock gating unit is sent to the receiving end through a clock transmission channel, and the data is sent to the receiving end through a data transmission channel based on the local clock signal of the sending end controlled by the clock gating unit.

As a preferred embodiment, the method further comprises: and the interface power consumption management state machine determines that the high-speed interconnection interface needs to enter or exit the low-power consumption state according to the power consumption requirement of the upper layer protocol.

Illustratively, the interface power consumption management state machine controls the sending end of the high-speed interconnection interface to enter a low power consumption state, including: and after the first enabling signal is input into the clock gating unit, waiting for a preset time length, and controlling a sending end of the high-speed interconnection interface to enter a low-power consumption state after the waiting is finished.

The power consumption control device and the power consumption control method provided in this embodiment belong to the same inventive concept, and the technical details that are not described in the power consumption control method of this embodiment may refer to the related descriptions in the power consumption control device, and are not described herein again.

Example two

The embodiment of the present invention provides a high-speed interconnect interface receiving end side device, referring to fig. 2a, the receiving end side device includes a power consumption control device 20 and a receiving end (including a data receiving module 21 and a clock receiving module 22) which are arranged on the receiving end side of the high-speed interconnect interface. Wherein, the power consumption control device 20 includes a receiving end power consumption control unit 201, configured to:

detecting whether a receiving end (specifically, a clock receiving module 22) of the high-speed interconnection interface receives a sending end clock signal through a clock transmission channel;

and controlling a receiving end (specifically, the data receiving module 21) of the high-speed interconnection interface to enter or exit a low power consumption state according to the detection result, wherein the receiving end (specifically, the data receiving module 21) of the high-speed interconnection interface processes the sending end data received through the data transmission channel based on the sending end clock signal.

Illustratively, the receiving-end power consumption control unit 201 is configured to control the receiving end of the high-speed interconnect interface to enter or exit the low power consumption state according to the detection result, and includes:

outputting a first control signal to control the data receiving enabling end of the receiving end of the high-speed interconnection interface to be invalid after detecting that the received clock signal of the transmitting end is from the existence to the nonexistence;

The two control signals output by the receiving end power consumption control unit 201 may be distinguished by the level of the level signal voltage, which depends on the requirement for the level signal voltage when the data receiving enable end is valid or invalid, for example: when the data receiving enable end is a low-level signal and is invalid, the receiving end power consumption control unit 201 outputs the low-level signal as a first control signal to the data receiving enable end; when the high level signal of the data receiving enable terminal is valid, the receiving terminal power consumption control unit 201 outputs the high level signal as the second control signal to the data receiving enable terminal. The data receiving enabling end may be disposed in the receiving end (specifically, the data receiving module 21), where the receiving end (specifically, the data receiving module 21) performs sending end data receiving when the enabling end is valid, and otherwise the receiving end (specifically, the data receiving module 21) stops sending end data receiving when the enabling end is invalid.

For the receiving-end power consumption control unit 201, the empty signal output principle of the existing asynchronous FIFO memory can be multiplexed to implement the function of the unit. Specifically, the receiving-end power consumption control unit 201 includes: a write clock signal terminal for inputting the received clock signal of the transmitting terminal; the read clock signal end inputs a receiving end local clock control signal; a null signal terminal outputting a null signal as the first control signal or the second control signal; wherein, the first and the second end of the pipe are connected with each other,

after the received sending end clock signal is started, the write pointer stops counting, the read pointer continues to increase under the drive of the read clock until the read-write pointer is equal, the receiving end power consumption control unit 201 is read empty, an output signal is used as an empty signal of the first control signal, and the empty signal is synchronized to a read clock domain by a synchronizer and used for controlling the read pointer;

It should be noted that the principle of outputting the null signal under the action of the read clock, the write clock, the read pointer and the write pointer in the receiving-end power consumption control unit 201 is similar to the principle of outputting the null signal under the action of the read clock, the write clock, the read pointer and the write pointer in the conventional asynchronous FIFO memory, and details thereof are not described herein.

In the above description, the power consumption control apparatus 20 provided in this embodiment further includes a synchronizer 202, configured to synchronize the null signal output by the receiving-end power consumption control unit 201 to the read clock domain to control the read pointer. Specifically, the synchronizer 202 may be designed by a delay circuit. Preferably, the synchronizer 202 includes at least one stage of D flip-flops, wherein when the D flip-flops are cascaded in multiple stages, in the signal end of the cascaded D flip-flops:

the input end D of the first-stage D trigger is connected with a high level; the input end D of the next-stage D trigger is connected with the output end Q of the previous-stage D trigger; the output end Q of the last stage D flip-flop is connected to the read enable end of the receiving end power consumption control unit 201;

the signal input by the clock terminal Clk of each stage of flip-flop is obtained from the local clock signal of the receiving terminal, and the Reset terminal Reset is connected to the empty signal terminal of the receiving terminal power consumption control unit 201.

The number of stages of the cascaded D flip-flops in the synchronizer may be designed by persons skilled in the art according to the depth of the receiving-end power consumption control unit 201, the clock frequency difference, and the switching time. Fig. 2b is a synchronizer composed of two stages of D flip-flops according to the second embodiment.

It should be noted that, when the number of stages of the D flip-flops in the synchronizer 202 is multi-stage, the clock terminals Clk of the D flip-flops at each stage may be directly connected to the output terminal of the local clock of the receiving terminal, that is, the clock input signals of the D flip-flops at each stage are the same-phase local clock signals of the receiving terminal, and of course, the following steps may also be performed: the clock terminal Clk of the next stage D flip-flop is inverted from the clock signal of the clock terminal Clk of the previous stage D flip-flop. The clock signal input to the synchronizer 202 and the receiver-side local clock control signal input to the receiver-side power consumption control section 201 are independent of each other, and both signals may be generated by the receiver-side local clock, but may have different frequencies.

It should be noted that, in this embodiment, the power consumption control device 20 may be disposed inside the receiving end of the high-speed interconnect interface as a part of the component of the receiving end of the high-speed interconnect interface, and certainly, some or all of the components of the power consumption control device 10 may also be disposed outside the receiving end of the high-speed interconnect interface separately, which is not limited in particular.

The signal timing relationship of the power consumption control device on the receiving end side in the present embodiment is shown in fig. 2c, which is referred to fig. 2c:

a clock signal of a sending end received by a receiving end of the high-speed interconnection interface is used as a write clock input of the FIFO of the power consumption control device, and a clock control signal generated by a local clock is used as a read clock input of the power consumption control device;

when a receiving end of the high-speed interconnection interface receives a clock signal of a sending end, writing is stopped, a reading clock can read the power consumption control device to be empty, once the power consumption control device is empty, reading and writing pointers are equal, an empty signal output end of the power consumption control device is pulled down, and then the receiving end is controlled to enter a low power consumption state;

when a receiving end of the high-speed interconnection interface receives a clock signal retransmitted by a sending end, a write pointer of the power consumption control device is immediately increased, the read pointer needs to wait for the read pointer to enable a signal to be effective for reading, and when the read pointer and the read pointer are not equal, a null signal output end of the power consumption control device is pulled high, so that the receiving end is controlled to exit from a low power consumption state;

and compared with a signal at the empty signal output end, the signal synchronized by the synchronizer at the receiving end of the high-speed interconnection interface is delayed for a period of time and is used for enabling the read pointer.

Correspondingly, this embodiment further provides a power consumption control method, which is applied to the power consumption control device in this embodiment, and the method includes:

and controlling the receiving end of the high-speed interconnection interface to enter or exit a low power consumption state according to the detection result, wherein the receiving end of the high-speed interconnection interface processes the sending end data received through the data transmission channel based on the sending end clock signal. Illustratively, the controlling the receiving end of the high-speed interconnection interface to enter or exit the low power consumption state according to the detection result includes:

and outputting a second control signal to control the data receiving enabling end of the receiving end of the high-speed interconnection interface to be effective after detecting that the received clock signal of the sending end exists from the nonexistence.

On the basis of the first embodiment and the second embodiment, an embodiment of the present invention further provides a power consumption control apparatus, including: the power consumption control device provided on the transmission end side of the high-speed interconnect interface in the first embodiment, and the power consumption control device provided on the reception end side of the high-speed interconnect interface in the second embodiment. The power consumption control devices on the two sides of the receiving and transmitting end act together to complete the low power consumption state switching of the whole system of the high-speed interconnection interface.

EXAMPLE III

An embodiment of the present invention provides a high-speed interconnect interface, including: the transmitting end and the receiving end are connected with a data transmission channel and a clock transmission channel of the transmitting and receiving end; and the power consumption control device provided by the first embodiment and the power consumption control device provided by the second embodiment. Of course, the power consumption control device provided in the first embodiment may also be embedded in the transmitting end, and the power consumption control device provided in the second embodiment may also be embedded in the receiving end.

In specific implementation, the high-speed interconnection interface is a chiplet interconnection interface, and the interface structure is shown in fig. 3 and specifically includes the following components.

1. Transmitting end side

(1) A data transmission module comprising:

the first asynchronous FIFO memory 301 is configured to store the sending-end data, wherein a writing clock signal end of the first asynchronous FIFO memory 301 inputs the sending-end local clock signal, and a reading clock signal end inputs the clock signal output by the data serial-to-parallel converter 302;

a data serial-to-parallel converter 302, respectively connected to the first asynchronous FIFO memory 301, the data transmitter 303 and the clock gating unit 308 of the first power consumption control device, for: reading the sending end data in the first asynchronous FIFO memory 301, performing serial-parallel conversion on the data, and outputting the data to the data transmitter 303; the clock signal output by the clock gating unit 308 is output to the first asynchronous FIFO memory 301 after being subjected to serial-parallel conversion;

the data transmitter 303 is connected to the data transmission channel, and is configured to drive the data transmission channel and transmit the serial-to-parallel converted data of the transmitting end to the receiving end of the high-speed interconnection interface through the data transmission channel;

(2) A clock transmission module comprising:

the adjusting unit 304 is connected to the clock gating unit 308, and is configured to perform frequency multiplication and phase modulation on the local clock signal at the transmitting end, and output the frequency-multiplied and phase-modulated local clock signal to the clock gating unit 308;

the clock serial-parallel converter 305 is respectively connected with the clock gating unit 308 and the clock transmitter 306, and is used for performing serial-parallel conversion on the clock signal output by the clock gating unit 308 and outputting the clock signal to the clock transmitter 306;

and the clock transmitter 306 is configured to drive the clock transmission channel, and transmit the serial-to-parallel converted clock signal to the receiving end of the high-speed interconnect interface through the clock transmission channel.

(3) A first power consumption control apparatus comprising:

an interface power management state machine 307 for: when the high-speed interconnection interface needs to enter a low-power-consumption state, controlling a data transmitter 303 of a transmitting end to enter the low-power-consumption state, and inputting a first enabling signal to a clock gating unit 308; when the high-speed interconnection interface needs to exit the low-power consumption state, controlling the data transmitter 303 of the transmitting end to exit the low-power consumption state, and inputting a second enabling signal to the clock gating unit 308;

a clock gating unit 308 to: the turn-off and turn-on of the transmission of the local clock signal of the transmitting end are controlled by the first enable signal and the second enable signal, so that the clock deserializer 305 of the transmitting end transmits the local clock signal of the transmitting end controlled by the clock gating unit 308 to the receiving end of the high-speed interconnect interface through the clock transmission channel, and the data deserializer 302 of the transmitting end transmits data to the receiving end of the high-speed interconnect interface through the data transmission channel based on the local clock signal of the transmitting end controlled by the clock gating unit 308.

The first power consumption control device in this embodiment is the same as the power consumption control device provided in the first embodiment, and reference may be made to the related description in the first embodiment for specific details that are not described in detail in this embodiment.

2. Receiving end side

(1) Data receiving module

A data receiver 311 for driving a data transmission channel and receiving the sender data;

a data clock deserializer 312, respectively connected to the clock receiver 314, the data receiver 311 and the second asynchronous FIFO memory 313, for: serial-parallel conversion is carried out on the sending end clock signal received by the clock receiver 314 and the sending end data received by the data receiver 311, and the sending end clock signal and the sending end data are output to the second asynchronous FIFO memory 313;

a second asynchronous FIFO 313, configured to synchronize the sender data serial-to-parallel converted by the data clock serial-to-parallel converter 312 to the receiver local clock to complete clock domain conversion, where a write clock signal end inputs the clock signal output by the data clock serial-to-parallel converter 312, and a read clock signal end inputs the receiver local clock signal;

(2) Clock receiving module

And the clock receiver 314, connected to the receiving-end power consumption control unit 315 and the data clock serial-parallel converter 312, is configured to drive a clock transmission channel, receive a clock signal sent by a sending end of the high-speed interconnect interface, and output the clock signal to the receiving-end power consumption control unit 315 and the data clock serial-parallel converter 312.

(3) Second power consumption control device

A receiving-end power consumption control unit 315 configured to: detecting whether a receiving end of the high-speed interconnection interface receives a sending end clock signal through a clock transmission channel; and controlling the data receiver 311 at the receiving end to enter or exit a low power consumption state according to the detection result.

In specific implementation, the receiving-end power consumption control unit 315 outputs a first control signal to control the disabling of the enabling end of the data receiver 311 of the receiving end after detecting that the sending-end clock signal received by the clock receiver 314 of the receiving end is invalid; and outputting a second control signal to control the enabling end of the data receiver 311 at the receiving end to be effective after detecting that the received clock signal at the transmitting end is absent.

Illustratively, the receiving-end power consumption control unit 315 includes: a write clock signal terminal for inputting a transmit-end clock signal received by the clock receiver 314 of the receive terminal; the read clock signal end inputs a receiving end local clock control signal; a null signal terminal outputting a null signal as the first control signal or the second control signal; wherein the content of the first and second substances,

Further, the second power consumption control device further includes a synchronizer 316, configured to synchronize the null signal output by the receiving-end power consumption control unit 315 to the read clock domain to control the read pointer.

The second power consumption control device in this embodiment is the same as the power consumption control device provided in the second embodiment, and reference may be made to the related description in the second embodiment for details of the technology that is not described in detail in this embodiment.

It should be noted that the data deserializer 302 on the transmitting end side and the data clock deserializer 312 on the receiving end side perform a pair of inverse operations on the processing of the data, and if the data deserializer 302 performs a serial-to-parallel conversion on the data, the data clock deserializer 312 performs a parallel-to-serial conversion on the data, and if the data deserializer 302 performs a parallel-to-serial conversion on the data, the data clock deserializer 312 performs a serial-to-parallel conversion on the data. Similarly, the clock deserializer 305 on the transmitting side and the data clock deserializer 312 on the receiving side process the clock signal as a pair of inverse operations: one is a conversion from serial to parallel and the other is a conversion from parallel to serial. Also, on the same side, the serial-to-parallel conversion of the data and clock signals is the same conversion operation, either from serial to parallel or from parallel to serial.

The timing relationship between signals in the high-speed interconnect interface is shown in fig. 4, which is shown in fig. 4:

when a local clock signal of a sending end is changed from a zero state to a zero state under the control of a clock gating unit, a data sender stops sending data after waiting for a preset time length, the sending end enters a low power consumption state, and in the state, a clock transmission channel transmits a differential zero and a data transmission channel transmits a zero; the receiving end power consumption control unit judges whether the clock signal received from the transmitting end changes from the existing state to the non-existing state, the data receiver is immediately controlled to stop receiving data, the receiving end enters a low power consumption state, and the synchronizer delays the null signal output by the receiving end power consumption control unit for a period of time;

subsequently, when a local clock signal of a sending end is controlled by the clock gating unit to be unchanged, the data sender starts to prepare for sending data, the sending end immediately exits from a low-power-consumption state, and in the state, the transmission difference of the clock transmission channel is not zero any more, and the transmission of the data transmission channel is not zero any more; the receiving end power consumption control unit judges whether the received clock signal from the transmitting end is changed from non-existence to existence, the receiving end power consumption control unit immediately exits from a low power consumption state, and the synchronizer delays the null signal output by the receiving end power consumption control unit for a period of time.

When the low-power-consumption state needs to be entered, the receiving end immediately enters the low-power-consumption state after detecting that the clock signal of the receiving end changes from being present to being absent, and the sending end needs to wait for the preset time length to enter the low-power-consumption state so as to meet the requirement that the receiving end stops receiving data first and then the sending end stops sending data. When the low-power-consumption state needs to be exited, the sending end immediately enters the low-power-consumption state under the control of the clock gating unit, and the time is consumed due to the fact that the clock signal of the sending end is transmitted on the clock transmission channel and processed inside the receiving end power-consumption control unit, the receiving end exits the low-power-consumption state and is delayed from the sending end, and therefore the state switching is that the sending end starts to prepare data to be sent and then the receiving end starts to prepare data to be received.

Different from the traditional interconnection interface, in the high-speed interconnection interface provided by the embodiment of the invention, the clock gating unit and the power consumption control device are additionally arranged on the transmitting end side, and the other power consumption control device is additionally arranged on the receiving end side.

It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The term "and/or" in the embodiments of the present invention describes an association relationship of associated objects, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on differences from other embodiments.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A power consumption control apparatus provided on a transmission end side of a high-speed interconnect interface, the apparatus comprising:

a clock gating unit to: controlling the transmission of a local clock signal of a transmitting end of the high-speed interconnection interface to be turned off and turned on through a first enabling signal and a second enabling signal, so that the transmitting end of the high-speed interconnection interface performs the following operations: and the local clock signal of the sending end controlled by the clock gating unit is sent to the receiving end through a clock transmission channel, and the data is sent to the receiving end through a data transmission channel based on the local clock signal of the sending end controlled by the clock gating unit.

2. The apparatus of claim 1, wherein the interface power management state machine is further to: and determining that the high-speed interconnection interface needs to enter or exit a low-power consumption state according to the power consumption requirement of the upper layer protocol.

3. The apparatus of claim 1, wherein the interface power management state machine is configured to control a transmit side of the high-speed interconnect interface to enter a low power state, and comprises:

and after the first enabling signal is input into the clock gating unit, waiting for a preset time length, and controlling a sending end of the high-speed interconnection interface to enter a low power consumption state after the end of waiting.

4. A power consumption control apparatus provided on a reception side of a high-speed interconnect interface, the apparatus comprising a reception-side power consumption control unit configured to:

5. The apparatus of claim 4, wherein the receiving-end power consumption control unit is configured to control the receiving end of the high-speed interconnect interface to enter or exit the low power consumption state according to the detection result, and includes:

6. The apparatus of claim 5, wherein the receiving-end power consumption control unit comprises: a write clock signal terminal for inputting the received clock signal of the transmitting terminal; the read clock signal end inputs a receiving end local clock control signal; a null signal terminal outputting a null signal as the first control signal or the second control signal; wherein the content of the first and second substances,

after the clock signal of the sending end received from the existence to the nonexistence, the write pointer stops counting, the read pointer continues to increase under the drive of the read clock until the read-write pointer is equal, the power consumption control unit of the receiving end is read empty, the output signal is used as an empty signal of the first control signal, and the empty signal is synchronized to a read clock domain by a synchronizer and is used for controlling the read pointer;

and after the received clock signal of the sending end exists, the write pointer starts counting, the read pointer starts counting when the control signal output by the synchronizer becomes effective, the read pointer and the write pointer are unequal, and a null signal serving as a second control signal is output.

7. The apparatus of claim 6, wherein the receiving-side power consumption control unit further comprises a synchronizer for synchronizing the null signal output from the receiving-side power consumption control unit to the read clock domain to control the read pointer, and the read pointer is changed only when the synchronizer output signal is high.

8. The apparatus of claim 7, wherein the synchronizer comprises at least one stage of D flip-flops, and wherein when the D flip-flops are cascaded in multiple stages, in the signal terminals of the cascaded D flip-flops:

9. A power consumption control apparatus, comprising:

the power consumption control apparatus according to any one of claims 1 to 3; and

the power consumption control device of any of claims 4-8 above.

10. A high-speed interconnect interface, comprising:

the transmitting end and the receiving end are connected with a data transmission channel and a clock transmission channel of the transmitting and receiving end; and, the power consumption control device of the above claim 9.

11. The interface according to claim 10, wherein the sender comprises:

the first asynchronous FIFO memory is used for storing the data of the sending end, wherein a writing clock signal end of the first asynchronous FIFO memory inputs a local clock signal of the sending end, and a reading clock signal end inputs a clock signal output by the data serial-parallel converter;

the data transmitter is connected with the data transmission channel and used for driving the data transmission channel and transmitting the serial-parallel converted data of the transmitting end to the receiving end of the high-speed interconnection interface through the data transmission channel;

12. The interface according to claim 10, wherein the receiving end comprises:

the data receiver is used for driving a data transmission channel and receiving sending end data;

a data clock deserializer respectively connected to the clock receiver, the data receiver, and the second asynchronous FIFO memory for: the sending end clock signal received by the clock receiver and the sending end data received by the data receiver are subjected to serial-parallel conversion and output to a second asynchronous FIFO memory;

the second asynchronous FIFO memory is used for synchronizing the data of the sending end after serial-parallel conversion by the data clock serial-parallel converter to the local clock of the receiving end so as to complete clock domain conversion, wherein the writing clock signal end of the second asynchronous FIFO memory inputs the clock signal output by the serial-parallel converter, and the reading clock signal end inputs the local clock signal of the receiving end;

and the clock receiver is connected with the receiving end power consumption control unit and the data clock serial-parallel converter and used for driving the clock transmission channel, receiving the clock signal sent by the sending end of the high-speed interconnection interface and outputting the clock signal to the receiving end power consumption control unit and the data clock serial-parallel converter.

13. The interface of claim 10, wherein the interface is a chiplet interconnect interface.

14. A power consumption control method applied to the power consumption control apparatus of any one of claims 1 to 3, characterized in that the method comprises:

15. The method of claim 14, further comprising:

16. The method of claim 14, wherein the interface power management state machine controls the initiator of the high-speed interconnect interface to enter a low power state, comprising:

17. A power consumption control method applied to the power consumption control apparatus according to any one of claims 4 to 8, characterized in that the method comprises:

18. The method of claim 17, wherein controlling a receiving end of the high-speed interconnect interface to enter or exit a low power consumption state according to the detection result comprises: