CN109842441A - A kind of high-voltage frequency converter optical signal loop test method and system - Google Patents
A kind of high-voltage frequency converter optical signal loop test method and system Download PDFInfo
- Publication number
- CN109842441A CN109842441A CN201910101407.6A CN201910101407A CN109842441A CN 109842441 A CN109842441 A CN 109842441A CN 201910101407 A CN201910101407 A CN 201910101407A CN 109842441 A CN109842441 A CN 109842441A
- Authority
- CN
- China
- Prior art keywords
- test
- code
- sent
- power cell
- code sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Optical Communication System (AREA)
Abstract
The invention discloses a kind of high-voltage frequency converter optical signal loop test method and systems, are related to high-voltage frequency converter communication test technical field comprising: master control system receives and parses through test instruction, generates test code streams；Test instruction includes initial code and pattern mode of operation, and test code streams obtain after being encoded by initial code；Pattern mode of operation is sent to power cell by master control system, and test code streams are then divided into two-way, is sent to power cell all the way, another way is as source code sequence；Power cell carries out bit manipulation to test code streams according to pattern mode of operation and obtains receiving code sequence, is then sent to master control system；After master control system receives reception code sequence, it is compared with source code sequence, obtains error code counting and the bit error rate.The reception code sequence that the present invention compares the source code sequence of its generation by master control system and power cell returns, calculates the bit error rate, by the bit error rate judge between corresponding power cell and master control system whether normal communication.
Description
Technical field
The present invention relates to high-voltage frequency converter communication test technical fields, and in particular to a kind of high-voltage frequency converter optical signal circuit
Test method and system.
Background technique
High-voltage frequency converter is made of a master control system and multiple power cells, and master control system and each power cell are logical
It crosses a pair of of optical fiber to be communicated, the control signal of transimission power unit.In field of industrial production such as electric power, chemical industry, coal mine, metallurgy
It is required that high-voltage frequency converter has high reliability, and can high-voltage frequency converter work normally, and whether depend on order circuit can be just
Really transmission data.
Master control system and the optical-fibre communications circuit of each power cell are made of many circuits, mainly by the string of master control system
Row Signal coding circuit, electro-optical conversion circuit, fiber optic cable, power cell opto-electronic receiver circuit and serial signal decoding circuit
Composition.When foregoing circuit device is deposited when abnormal, communication function just will affect.
Whether the method for existing test failure power cell quotes communication event when having directly observation high-voltage frequency converter work
Barrier, or tested using the fiber-optic signal loop-around test tooling specially made, the former error is larger, and inefficiency, after
Person needs to carry out communication function test one by one to each power cell, and efficiency is lower, and test fixture is invested and opened
Hair, cost is larger, in addition, voltage is up to 6kV or 10kV when due to high-voltage frequency converter work, for the safety for ensuring operator,
Power on every time and under it is electrically operated have to comply with safety standard and process, it is more that test expends the time.
Summary of the invention
In view of the deficiencies in the prior art, the purpose of the present invention is to provide a kind of high-voltage frequency converter optical signal circuits
Test method and system can fast and efficiently detect communication quality between master control system and power cell.
The present invention provides a kind of high-voltage frequency converter optical signal loop test methods comprising step:
Master control system receives and parses through test instruction, generates test code streams；Test instruction includes that initial code and pattern operate
Mode, test code streams obtain after being encoded by initial code；
Pattern mode of operation is sent to power cell by master control system, and test code streams are then divided into two-way, are sent all the way
To power cell, another way is as source code sequence；
Power cell carries out bit manipulation to test code streams according to pattern mode of operation and obtains receiving code sequence, is then sent to
Master control system；
After master control system receives reception code sequence, it is compared with source code sequence, obtains error code counting, and then obtain
To the bit error rate.
Based on the above technical solution, test code streams are sent to power cell all the way, specifically include:
Test code streams are subjected to frame processing, obtain data frame；
Data frame is converted into the bit stream that step-by-step is successively serially sent, bit stream is then converted into optical signal, passes through first
Optical fiber is transmitted to power cell.
Based on the above technical solution, power cell obtains test code streams progress bit manipulation according to pattern mode of operation
To code sequence is received, it is then sent to master control system, is specifically included:
Power cell will receive optical signal from the first optical fiber and be converted into bit stream, and bit stream is converted into data frame；
Data frame is decoded, pattern mode of operation and test code streams are extracted；
Bit manipulation is carried out to test code streams according to pattern mode of operation to obtain receiving code sequence；
Frame processing is carried out to code sequence is received, obtains data frame；
Data frame is converted into bit stream, bit stream is then converted into optical signal, master control system is transmitted to by the second optical fiber.
Based on the above technical solution, after master control system receives reception code sequence, by itself and the progress of source code sequence
Comparison obtains error code counting, specifically includes:
Master control system will receive optical signal from the second optical fiber and be converted into bit stream, and bit stream is converted into data frame；
Data frame is decoded, extracts and receives code sequence；
Code sequence will be received and source code sequence carries out one-to-one comparison, obtain error code counting.
Based on the above technical solution, pattern mode of operation is that step-by-step is negated or do not operated.
Based on the above technical solution, initial code generates test code streams, test patterns according to pseudo-random binary sequence
Stream is pseudo noise code PRBS7 code stream.
The present invention also provides a kind of high-voltage frequency converter optical signal loop-around test systems for realizing the above method comprising one
Master control system and multiple power cells, master control system include transmission unit and receiving unit；
Transmission unit generates test code streams for receiving and parsing through test instruction；Test instruction includes initial code and pattern
Mode of operation, test code streams obtain after being encoded by initial code；Transmission unit is also used to pattern mode of operation being sent to function
Rate unit, and test code streams are divided into two-way, it is sent to power cell all the way, another way is sent to receiving unit as original
Code sequence；
Power cell is used to receive the test code streams all the way and pattern mode of operation that transmission unit is sent, and is grasped according to pattern
Make mode test code streams progress bit manipulation is obtained receiving code sequence, is then sent to receiving unit；
Receiving unit compares it with source code sequence for receiving the reception code sequence that power cell is sent,
Error code counting is obtained, and then obtains the bit error rate.
Based on the above technical solution, transmission unit includes:
Instruction parser is used to receive and parse through the test instruction that Human machine interface is sent；
Pattern generator is used to generate test code streams according to initial code, and test code streams is divided into two-way, all the way with code
Type mode of operation is transmitted to power cell；Another way enters receiving unit as source code sequence；
First editing machine, the test code streams for being used to send pattern generator carry out frame processing, obtain data frame；
First signal sending circuit is used to the data frame that the first editing machine is sent being converted into bit stream；
First electro-optical conversion circuit is used to the bit stream that the first signal sending circuit is sent being converted to optical signal, and leads to
It crosses the first optical fiber and is transmitted to power cell.
Based on the above technical solution, power cell includes:
Second photoelectric conversion circuit is used to the optical signal received from the first optical fiber being converted into bit stream；
Second signal receives circuit, is used to the bit stream that the second photoelectric conversion circuit is sent being converted into data frame；
Second decoder is used to for the data frame that second signal reception circuit is sent being decoded, extracts pattern operation
Mode and test code streams；
Converter is used to carry out bit manipulation to test code streams according to pattern mode of operation to obtain receiving code sequence；
Second encoder is used to carry out frame processing to the reception code sequence received, obtains data frame；
Second signal transmitting line, the data frame for being used to send second encoder are converted into bit stream；
Second electro-optical conversion circuit is used to the bit stream that second signal transmitting line is sent being converted to optical signal, pass through
Second optical fiber is transmitted to master control system.
Based on the above technical solution, receiving unit includes:
First photoelectric conversion circuit is used to the optical signal received from the second optical fiber being converted into bit stream；
First signal receiving circuit is used to the bit stream that the first photoelectric conversion circuit is sent being converted into data frame；
First decoder is used to be decoded the data frame that the first signal receiving circuit is sent, and extracts and receives code sequence
Column；
Error rate calculation device is used to compare the reception code sequence that the first decoder is sent with source code sequence,
Error code counting is obtained, and then obtains the bit error rate；
Output circuit is calculated, is used to the bit error rate being sent to HMI.
Compared with the prior art, the advantages of the present invention are as follows:
(1) high-voltage frequency converter optical signal loop test method of the invention compares the original of its generation by master control system
Code sequence and power cell return reception code sequence, calculate the bit error rate, by the bit error rate judge corresponding power cell with
Between master control system whether normal communication.
(2) hardware design of the present invention without changing high-voltage frequency converter can be quick, quasi- without newly-increased test fixture
Really look for out of order power cell.
Detailed description of the invention
Fig. 1 is the flow chart of high-voltage frequency converter optical signal loop test method provided in an embodiment of the present invention；
Fig. 2 is the flow chart of step S2 in the embodiment of the present invention；
Fig. 3 is the flow chart of step S3 in the embodiment of the present invention；
Fig. 4 is the flow chart of step S4 in the embodiment of the present invention；
Fig. 5 is the generating principle figure of PRBS7 code stream provided in an embodiment of the present invention；
Fig. 6 is the schematic diagram of high-voltage frequency converter provided in an embodiment of the present invention；
The signal of Fig. 7 loop-around test system between master control system provided in an embodiment of the present invention and a power cell
Figure.
Specific embodiment
Invention is further described in detail with reference to the accompanying drawings and embodiments.
Shown in Figure 1, the embodiment of the present invention provides a kind of high-voltage frequency converter optical signal loop test method, for testing
Optical-fibre communications function between the master control system and power cell of high-voltage frequency converter, comprising the following steps:
S1. master control system receives and parses through test instruction, generates test code streams；Test instruction includes that initial code and pattern are grasped
Make mode, test code streams obtain after being encoded by initial code.Wherein, initial code is generated according to pseudo-random binary sequence and is tested
Code stream, test code streams are pseudo noise code PRBS7 code stream.
S2. pattern mode of operation is sent to power cell by master control system, and test code streams are then divided into two-way, and riches all the way
Power cell is given, another way is as source code sequence；
S3. power cell carries out bit manipulation to test code streams according to pattern mode of operation and obtains reception code sequence, then sends out
Give master control system；
S4. after master control system receives reception code sequence, it is compared with source code sequence, obtains error code counting, into
And obtain the bit error rate.
Component one of of the HMI as high-voltage frequency converter itself, the operating mode of itself includes normal mode of operation.This implementation
In example, optical signal Loop communication test pattern is increased newly in HMI, for carrying out communication test to signal circuit.HMI is being sent just
Before beginning code, communication test mode instruction is sent in advance to power cell, indicated horsepower unit is transferred to test mode, then sends out again
Send pattern mode of operation and initial code.
In the present embodiment, instructs, that is, needed to each power list when master control system receives the test that Human machine interface issues
Member carries out error rate test.Master control system issues test code streams, each power cell to each power cell by optical fiber circuit
After receiving test code streams, conversion process is carried out according to the requirement of master control system and uploads to master control system again.Pass through master control system
The reception code sequence that the source code sequence and power cell for comparing its generation return, can be obtained error code counting, calculates error code
Rate, then by the bit error rate judge between corresponding power cell and master control system whether normal communication, when the bit error rate is beyond pre-
If can determine whether when value and indicate fault power unit.Wherein, the reception code sequence that source code sequence and power cell return
Using one-to-one way of contrast.
Test code streams are sent to power cell all the way in above-mentioned steps S2, specifically include: test code streams are subjected to frame processing,
The data frame as unit of byte is obtained, data frame is then converted into the bit stream that step-by-step is successively serially sent, and bit stream is turned
It is changed to optical signal, power cell is transmitted to by the first optical fiber.
Shown in Figure 2, above-mentioned steps S2 is specifically included:
S201. master control system receives and parses through test instruction, generates test code streams；
S202. test code streams are subjected to frame processing by byte, obtain data frame；
S203. data frame is converted into the bit stream that step-by-step is successively sent, bit stream is then converted into optical signal, pass through first
Optical fiber is transmitted to power cell.
Shown in Figure 3, above-mentioned steps S3 is specifically included:
S301. after power cell receives the optical signal that the first optical fiber transmits, bit stream is converted optical signals into, then by position
Stream is by byte conversion at data frame；
S302. data frame is decoded, extracts pattern mode of operation and test code streams；
S303. bit manipulation is carried out to test code streams according to pattern mode of operation to obtain receiving code sequence；
S304. to code sequence is received by byte progress frame processing, data frame is obtained；
S305. data frame is converted into bit stream, bit stream is then converted into optical signal, master control is transmitted to by the second optical fiber
System.
Shown in Figure 4, above-mentioned steps S4 is specifically included:
S401. after master control system receives the optical signal that the second optical fiber transmits, bit stream is converted optical signals into, then by position
Circulation changes data frame into.
S402. data frame is decoded, extracts and receives code sequence.
S403. code sequence will be received and source code sequence carries out one-to-one comparison, and obtain error code counting, and then missed
Code rate.
Judging result whether above-mentioned steps S4 further includes by the bit error rate and normal communication is converted into man-machine interface (HMI
Human Machine Interface) displayable form, and be sent in HMI, to show the corresponding mistake of each power cell
Code rate and communication whether normal judging result, convenient for checking.
Above-mentioned pattern mode of operation is that step-by-step is negated or do not operated.Preferably, pattern mode of operation negates for step-by-step, with true
It protects power cell and receives and done a step-by-step after test code streams and negate processing, rather than simple forwarding, it is ultimately delivered to influence
The polarity of the electric signal of FPGA CPLD pin.
In the embodiment of the present invention, test code streams are binary system random test code stream PRBS (Pseudo-Random Binary
Sequence) 7 code stream.PRBS7 code stream is seven random sequences, and circulation primary needs 127 bit.Therefore initial code selection
8bit binary system pattern produces the PRBS7 code stream of 127bit, the time which completes a cycle is most short, can save
Testing time.
For PRBS7 code stream, the principle process for generating test code streams by initial code is as shown in Figure 5, it is only necessary to use 7 shiftings
Bit register and simple XOR gate can be realized.
When initial code is 00000001,127 obtained code streams, in addition the output (D7) when moment 0, is constituted
128 bit data frames are distributed as shown in table 1 below by byte.
128 bit data frames of table 1PRBS7 code stream
| BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 | |
| BYTE1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| BYTE2 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
| BYTE3 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
| BYTE4 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| BYTE5 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
| BYTE6 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
| BYTE7 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 |
| BYTE8 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
| BYTE9 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 |
| BYTE10 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
| BYTE11 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
| BYTE12 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 |
| BYTE13 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 |
| BYTE14 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 |
| BYTE15 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
| BYTE16 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Above-mentioned 16 byte BYTE, according to BYTE1, BYTE2 ..., the sequence of BYTE16, one by one by FPGA pin,
And each BYTE successively press BIT0, BIT1, BIT2 ..., the sequence of BIT7 sends.
High-voltage frequency converter exports three-phase frequency modulation and voltage modulation AC power source, and every phase is made of the equal power cell of quantity；Root
According to the height of high-voltage frequency converter operating voltage, the quantity of every phase power cell is between 5-9.When operating voltage is 6kV, often
The quantity of phase power cell is 5, and the special every phase of type increases by 1；When operating voltage is 10kV, the number of every phase power cell
Amount is 8, and the special every phase of type increases by 1.
In the present embodiment, by a FPGA, (Field-Programmable Gate Array, scene can compile master control system
Journey gate array) it realizes, in each power cell internal, for cost consideration, communication function is by a CPLD (Complex
Programmable Logic Device, Complex Programmable Logic Devices) it realizes.For each type of compatibility, in control system
It is interior, it is designed according to the capacity of every 10 units of phase, i.e., establishes 30 channels in the master control system of high-voltage frequency converter, often
A channel function is identical, to control power cell.Master control system and each power cell are communicated by a pair of of optical fiber, are wrapped
Include a root receiving fiber and a transmission optical fiber, the control signal of transimission power unit.Therefore 9 power lists of phase every for one
In the high-voltage frequency converter complete machine of member, the number of fibers for communicating is up to 3*9*2=54 root.
Master control system and the physical layer communication mode of power cell use serial communication mode, and communication clock frequency is
6.25MHz, each bit bit duration are 1/6.25MHz=0.16 microsecond；An every 8 bit i.e. byte conducts
One frame is sent, and data frame format is as shown in table 2 below.
2 data frame format of table
In an idle state, i.e., when no data are transmitted, FPGA CPLD pin level is high level, and duration
For 5 bit bit length times.
When there is data transfer, pin level can drop to 0 level first, this is a start bit, indicate subsequent incite somebody to action
Having the data of a byte will transmit；After start bit, a level will be received, state 1 or 0 represents this byte
The 1st, indicated with BIT0, successively 8 of a byte be transmitted, i.e. BIT1, BIT2, BIT3, BIT4, BIT5,
BIT6, BIT7, will there is a bit check position later, value be above-mentioned 8 data CRC (Cyclic Redundancy Check,
Cyclic redundancy check code) calculated value will transmit the last one bit later, being worth is 1, as stop position, a byte transmission
It finishes.
When continuously transmitting byte, 5 spare bits, the start bit of each byte, check bit between byte twice are considered
And stop position, the time for transmitting an octet is actually 5+1+8+1+1=16 bit time.Therefore, one
The length of PRBS7 code stream is 127, in addition the position bit at 0 moment, amounts to 128 bit lengths, the time tranfer by 16 bytes is complete
At.After the time tranfer of every 16 bytes completes a string of PRBS7 code streams, transmission PRBS7 code is repeated, until test is completed.
Since the statistical unit of the bit error rate is the error code number in every million bit, in the test of a bit error rate
When, default sends 2,000,000 bit, then detects the quantity of the wherein wrong position bit.Testing time calculation formula is such as
Under:
The total data position * data bit actual transmissions time=2000000* (16/8) * 0.16us=0.64 seconds.
Therefore, it after all BIT in above-mentioned table 2 are all sent completely, then sends from the beginning, 2000000/ need to be passed through
After 128=15652 wheel, 2000000 BIT have been sent.
When testing, the operating mode that HMI is transmitted to master control system be communication test mode, at this point, the interface HMI after
Continuous prompt setting initial code, power cell are to the mode of operation and total code stream digit of the pattern received.Wherein, initial code
8 binary systems that cannot be all 0, value range is 00000001~11111111, and initial code is in the present embodiment
00000001；Pattern mode of operation is defaulted as step-by-step inversion operation, and total code stream digit is 2,000,000 bit.
30 channels share same set of PRBS7 code stream, and 30 channels respectively send all BIT in above-mentioned table 2.It compares
When, it counts in code stream identical BIT and is worth different position number.When detecting a BIT difference, then to this channel
Error code number carries out adding one.After the completion of all 2000000 all compare, calculated according to error code number/2000000 each logical
The bit error rate in road simultaneously uploads to HMI.
Referring to shown in Fig. 6 and Fig. 7, the embodiment of the present invention also provides a kind of high-voltage frequency converter optical signal for realizing the above method
Loop-around test system, including a master control system and multiple power cells, master control system include transmission unit and receiving unit.
Above-mentioned transmission unit generates test code streams for receiving and parsing through test instruction；Test instruction include initial code and
Pattern mode of operation, test code streams obtain after being encoded by initial code；Transmission unit is also used to send pattern mode of operation
It is divided into two-way to power cell, and by test code streams, is sent to power cell all the way, another way is sent to receiving unit conduct
Source code sequence.
Above-mentioned power cell is for receiving communication test mode instruction, in order to be transferred to test mode；Power cell is also used
In receiving the test code streams all the way sent of transmission unit and pattern mode of operation, and according to pattern mode of operation to test code streams into
Line position, which operates to obtain, receives code sequence, is then sent to receiving unit.
Above-mentioned receiving unit carries out it with source code sequence pair for receiving the reception code sequence that power cell is sent
Than obtaining error code counting, and then obtain the bit error rate.
In the present embodiment, transmission unit includes instruction parser MCI, pattern generator MPG, the first editing machine MFG, first
Signal sending circuit MTX and the first electro-optical conversion circuit MOT.
Instruction parser is used to receive and parse through the test instruction that HMI is sent, and is then sent to test instruction after parsing
Pattern generator.
Pattern generator includes linear feedback shift register LFSR (linear feedback shift registers)
It is formed with exclusive or XOR (exclusive OR) circuit, for generating test code streams according to the initial code in test instruction.This implementation
In example, initial code is pseudo noise code PRBS7 code stream, i.e. pattern generator can generate the test code streams of 127bit, and by test patterns
Flow point is two-way, is sent to the first editing machine all the way, and another way enters receiving unit as source code sequence.
The test code streams that first editing machine is used to send pattern generator carry out frame processing according to communications protocol, are counted
According to frame, it is then forwarded to the first signal sending circuit.
First signal sending circuit is a kind of high speed serialization transmitting line, and the data frame for sending the first editing machine turns
It changes the bit stream that step-by-step is successively sent into, and is sent to the first electro-optical conversion circuit.
First electro-optical conversion circuit is used to the bit stream that the first signal sending circuit is sent being converted to optical signal, the first optical fiber
It is inserted on this circuit interface, the optical signal after conversion is transmitted in power cell by the first optical fiber.
In the present embodiment, power cell includes the second photoelectric conversion circuit UOR, second signal reception circuit U RX, the second solution
Code device UFD, converter UFC, second encoder UCF, second signal transmitting line UTX and the second electro-optical conversion circuit UOT.
Second photoelectric conversion circuit is used to the optical signal received from the first optical fiber being converted into bit stream, and bit stream is sent out
It send to second signal and receives circuit.
It is a kind of high speed serialization reception circuit, the position for sending the second photoelectric conversion circuit that second signal, which receives circuit,
Circulation changes data frame into, is then forwarded to the second decoder.
Second decoder is used for the number that according to the communications protocol arranged with master control system, second signal reception circuit is sent
It is decoded according to frame, extracts pattern mode of operation and test code streams, and test code streams and pattern mode of operation are sent to conversion
Device.Above-mentioned pattern mode of operation is that step-by-step is negated or do not operated.Preferably, pattern mode of operation negates for step-by-step.
Converter is used to carry out bit manipulation to test code streams according to the pattern mode of operation to obtain receiving code sequence,
And it is sent to second encoder.
The effect of second encoder is similar to the effect of the first encoder, for carrying out at frame to the reception code sequence received
Reason, obtains data frame, is then forwarded to second signal transmitting line.
Second signal transmitting line is also a kind of high speed serialization transmitting line, the data frame for sending second encoder
It is converted into bit stream and is sent to the second electro-optical conversion circuit.
Second electro-optical conversion circuit is used to the bit stream that second signal transmitting line is sent being converted to optical signal, passes through second
Optical fiber is transmitted to master control system.
In the present embodiment, receiving unit includes the first photoelectric conversion circuit MOR, the first signal receiving circuit MRX, the first solution
Code device MFD, error rate calculation device MCK and calculating output circuit MEO.
First photoelectric conversion circuit is used to the optical signal received from the second optical fiber being converted into bit stream, and is sent to the
One signal receiving circuit.
First signal receiving circuit is a kind of high speed serialization reception circuit, the position for sending the first photoelectric conversion circuit
Circulation changes data frame into, and is sent to the first decoder.
First decoder is used for according to the communications protocol arranged with power cell, the number sent to the first signal receiving circuit
It is decoded according to frame, extracts and receive code sequence, be sent to error rate calculation device.
Error rate calculation device is used for the reception code sequence that the first decoder is sent and the source code that pattern generator is sent
Sequence compares, and obtains error code counting, the bit error rate is calculated by error code, and the bit error rate is sent to calculating output
Circuit.
Since HMI data representation format and master control system are different, calculate output circuit and be used to the bit error rate being converted into HMI
Displayable form, and be sent in HMI.
The test macro of the embodiment of the present invention, is suitable for above-mentioned test method, and the hardware without changing high-voltage frequency converter is set
Meter can simply, efficiently detect master control system on the basis of not increasing additional hardware cost without newly-increased test fixture
Optical fiber circuit communication quality between system and power cell, quickly and accurately looks for out of order power cell.
The present invention is not limited to the above-described embodiments, for those skilled in the art, is not departing from
Under the premise of the principle of the invention, several improvements and modifications can also be made, these improvements and modifications are also considered as protection of the invention
Within the scope of.The content being not described in detail in this specification belongs to the prior art well known to professional and technical personnel in the field.
Claims (10)
1. a kind of high-voltage frequency converter optical signal loop test method, which is characterized in that itself comprising steps of
Master control system receives and parses through test instruction, generates test code streams；The test instruction includes that initial code and pattern operate
Mode, the test code streams obtain after being encoded by the initial code；
The pattern mode of operation is sent to power cell by the master control system, and the test code streams are then divided into two-way,
It is sent to power cell all the way, another way is as source code sequence；
The power cell carries out bit manipulation to test code streams according to the pattern mode of operation and obtains receiving code sequence, then sends out
Give master control system；
After the master control system receives the reception code sequence, it is compared with source code sequence, obtains error code counting, into
And obtain the bit error rate.
2. high-voltage frequency converter optical signal loop test method as described in claim 1, which is characterized in that test code streams are sent out all the way
Power cell is given, is specifically included:
The test code streams are subjected to frame processing, obtain data frame；
The data frame is converted into the bit stream that step-by-step is successively serially sent, bit stream is then converted into optical signal, passes through first
Optical fiber is transmitted to power cell.
3. high-voltage frequency converter optical signal loop test method as claimed in claim 2, which is characterized in that the power cell root
Bit manipulation is carried out to test code streams according to the pattern mode of operation to obtain receiving code sequence, is then sent to master control system, specifically
Include:
The power cell will receive optical signal from the first optical fiber and be converted into bit stream, and bit stream is converted into data frame；
The data frame is decoded, pattern mode of operation and test code streams are extracted；
Bit manipulation is carried out to test code streams according to the pattern mode of operation to obtain receiving code sequence；
Frame processing is carried out to the reception code sequence, obtains data frame；
The data frame is converted into bit stream, bit stream is then converted into optical signal, master control system is transmitted to by the second optical fiber.
4. high-voltage frequency converter optical signal loop test method as claimed in claim 3, which is characterized in that the master control system is received
To after the reception code sequence, it is compared with source code sequence, obtains error code counting, specifically include:
The master control system will receive optical signal from the second optical fiber and be converted into bit stream, and bit stream is converted into data frame；
The data frame is decoded, extracts and receives code sequence；
Code sequence will be received and source code sequence carries out one-to-one comparison, obtain error code counting.
5. high-voltage frequency converter optical signal loop test method as described in claim 1, it is characterised in that: the pattern operation side
Formula is that step-by-step is negated or do not operated.
6. high-voltage frequency converter optical signal loop test method as described in claim 1, it is characterised in that: the initial code according to
Pseudo-random binary sequence generates the test code streams, and the test code streams are pseudo noise code PRBS7 code stream.
7. a kind of high-voltage frequency converter optical signal loop-around test system for realizing claim 1 the method, which is characterized in that it is wrapped
A master control system and multiple power cells are included, the master control system includes transmission unit and receiving unit；
The transmission unit generates test code streams for receiving and parsing through test instruction；Test instruction include initial code and
Pattern mode of operation, the test code streams obtain after being encoded by the initial code；Transmission unit is also used to the pattern
Mode of operation is sent to power cell, and test code streams are divided into two-way, is sent to power cell all the way, another way is sent to
Receiving unit is as source code sequence；
The power cell is used to receive the test code streams all the way and pattern mode of operation that the transmission unit is sent, and according to institute
It states pattern mode of operation test code streams progress bit manipulation is obtained receiving code sequence, is then sent to the receiving unit；
The receiving unit compares it with source code sequence for receiving the reception code sequence that power cell is sent,
Error code counting is obtained, and then obtains the bit error rate.
8. high-voltage frequency converter optical signal loop-around test system as claimed in claim 7, which is characterized in that the transmission unit packet
It includes:
Instruction parser is used to receive and parse through the test instruction that Human machine interface is sent；
Pattern generator is used to generate test code streams according to the initial code, and the test code streams is divided into two-way, all the way
It transmits with the pattern mode of operation to power cell；Another way enters the receiving unit as source code sequence；
First editing machine, the test code streams for being used to send the pattern generator carry out frame processing, obtain data frame；
First signal sending circuit is used to the data frame that first editing machine is sent being converted into bit stream；
First electro-optical conversion circuit is used to the bit stream that first signal sending circuit is sent being converted to optical signal, and leads to
It crosses the first optical fiber and is transmitted to power cell.
9. high-voltage frequency converter optical signal loop-around test system as claimed in claim 8, which is characterized in that the power cell packet
It includes:
Second photoelectric conversion circuit is used to the optical signal received from the first optical fiber being converted into bit stream；
Second signal receives circuit, is used to the bit stream that second photoelectric conversion circuit is sent being converted into data frame；
Second decoder is used to for the data frame that second signal reception circuit is sent being decoded, extracts pattern operation
Mode and test code streams；
Converter is used to carry out bit manipulation to test code streams according to the pattern mode of operation to obtain receiving code sequence；
Second encoder is used to carry out frame processing to the reception code sequence received, obtains data frame；
Second signal transmitting line, the data frame for being used to send second encoder are converted into bit stream；
Second electro-optical conversion circuit is used to the bit stream that second signal transmitting line is sent being converted to optical signal, passes through second
Optical fiber is transmitted to master control system.
10. high-voltage frequency converter optical signal loop-around test system as claimed in claim 9, which is characterized in that the receiving unit
Include:
First photoelectric conversion circuit is used to the optical signal received from the second optical fiber being converted into bit stream；
First signal receiving circuit is used to the bit stream that first photoelectric conversion circuit is sent being converted into data frame；
First decoder is used to be decoded the data frame that first signal receiving circuit is sent, and extracts and receives code sequence
Column；
Error rate calculation device is used to compare the reception code sequence that first decoder is sent with source code sequence,
Error code counting is obtained, and then obtains the bit error rate；
Output circuit is calculated, is used to the bit error rate being sent to HMI.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910101407.6A CN109842441A (en) | 2019-01-31 | 2019-01-31 | A kind of high-voltage frequency converter optical signal loop test method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910101407.6A CN109842441A (en) | 2019-01-31 | 2019-01-31 | A kind of high-voltage frequency converter optical signal loop test method and system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109842441A true CN109842441A (en) | 2019-06-04 |
Family
ID=66884357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910101407.6A Pending CN109842441A (en) | 2019-01-31 | 2019-01-31 | A kind of high-voltage frequency converter optical signal loop test method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109842441A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113132060A (en) * | 2021-04-21 | 2021-07-16 | 潍柴动力股份有限公司 | Message data transmission method and device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102123060A (en) * | 2011-03-24 | 2011-07-13 | 索尔思光电（成都）有限公司 | FPGA (Field Programmable Gate Array) based error code testing method |
| CN103795593A (en) * | 2014-01-24 | 2014-05-14 | 武汉大学 | Testing system and method of uplink of high-speed communication processor of spaceship |
| CN205070774U (en) * | 2015-10-21 | 2016-03-02 | 辽宁荣信电气传动技术有限责任公司 | Two optic fibre looped netowrk communication topological structure of high -voltage inverter power unit |
| CN108111221A (en) * | 2017-12-22 | 2018-06-01 | 四川九洲空管科技有限责任公司 | A kind of fiber link automatic testing method based on certain hip-based platform digital radar |
-
2019
- 2019-01-31 CN CN201910101407.6A patent/CN109842441A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102123060A (en) * | 2011-03-24 | 2011-07-13 | 索尔思光电（成都）有限公司 | FPGA (Field Programmable Gate Array) based error code testing method |
| CN103795593A (en) * | 2014-01-24 | 2014-05-14 | 武汉大学 | Testing system and method of uplink of high-speed communication processor of spaceship |
| CN205070774U (en) * | 2015-10-21 | 2016-03-02 | 辽宁荣信电气传动技术有限责任公司 | Two optic fibre looped netowrk communication topological structure of high -voltage inverter power unit |
| CN108111221A (en) * | 2017-12-22 | 2018-06-01 | 四川九洲空管科技有限责任公司 | A kind of fiber link automatic testing method based on certain hip-based platform digital radar |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113132060A (en) * | 2021-04-21 | 2021-07-16 | 潍柴动力股份有限公司 | Message data transmission method and device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| MX2008002628A (en) | A relay-to-relay direct communication system and method in a electric power system. | |
| CN101702639B (en) | Check value calculation method and device of cyclic redundancy check | |
| CN102957511B (en) | Adaptive deceleration method of data transmission | |
| CN103780322A (en) | Low-cost high-reliability high-speed network communication chip testing method and circuits | |
| CN102752098B (en) | For the measurement of error code method synchronous based on pseudo-random code sequence of communication system | |
| CN101771525B (en) | High-speed digital communication line error code detection device and method | |
| CN105955114A (en) | Safe input system based on dynamic pulse verification | |
| CN109842441A (en) | A kind of high-voltage frequency converter optical signal loop test method and system | |
| CN100385427C (en) | Communication controller and method of transforming information | |
| CN110943762A (en) | Direct-current power line carrier communication method based on differential Manchester coding and air conditioner | |
| CN102340368A (en) | Method, system and device for monitoring error codes in CPRI (Common Public Radio Interface) link | |
| CN104052588B (en) | For the method to realize the precise time stamp by IEEE1588 using the system of FEC encoder | |
| CN113691340A (en) | Ring main unit digital terminal based on Manchester coding and data transmission method thereof | |
| CN105072058B (en) | A kind of positive and negative phase coding method of data and data transmission method based on optical fiber transmission | |
| CN112532618B (en) | Non-transparent protocol conversion method and device for joint debugging test of stability control test system | |
| CN103199865B (en) | A kind of light adaptive serial port decoding circuit | |
| CN102098102B (en) | Burst mode code error tester for optical circuit terminal optical module of gigabit passive optical network | |
| US9337959B2 (en) | Defect propagation of multiple signals of various rates when mapped into a combined signal | |
| CN1964478A (en) | A random processing method for scrambling/descrambling in digital video broadcast system | |
| CN101442380A (en) | Method and apparatus for testing error rate based on high speed serial interface encoded mode | |
| CN115037419B (en) | Method for serial transmission of variable-length coded data in chip testing process | |
| CN108650047B (en) | Serial data receiving real-time synchronous monitoring circuit and monitoring method | |
| CN2684471Y (en) | Optical transmitter and receiver with embedded error code testing function | |
| EP0094254A2 (en) | Integrated scrambler-encoder using PN sequence generator | |
| CN1671084A (en) | Optical transmitter and receiver with embedded error code test function and method for implementing end-to-end error code test |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190604 |