CN109841673A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
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- CN109841673A CN109841673A CN201811311350.4A CN201811311350A CN109841673A CN 109841673 A CN109841673 A CN 109841673A CN 201811311350 A CN201811311350 A CN 201811311350A CN 109841673 A CN109841673 A CN 109841673A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000010410 layer Substances 0.000 claims description 162
- 239000011229 interlayer Substances 0.000 claims description 77
- 125000006850 spacer group Chemical group 0.000 claims description 74
- 238000000034 method Methods 0.000 claims description 46
- 238000000151 deposition Methods 0.000 claims description 33
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 9
- 238000003851 corona treatment Methods 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 13
- 238000002955 isolation Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 7
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 101000956368 Trittame loki CRISP/Allergen/PR-1 Proteins 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Abstract
Disclose semiconductor device and its manufacturing method.Semiconductor device includes: gate electrode, is located in substrate；Upper overlay pattern is located on gate electrode；And lower overlay pattern, between gate electrode and upper overlay pattern.Lower overlay pattern includes: first part, between gate electrode and upper overlay pattern；And multiple second parts, from the corresponding side surface that first part extends to upper overlay pattern.Most top surface in each of upper overlay pattern covering second part.
Description
This application claims Korea Spro 10-2017-016937 submitted on November 29th, 2017 in Korean Intellectual Property Office
The full content of the equity of state's patent application, the South Korea patent application is included herein by reference.
Technical field
This disclosure relates to semiconductor device, more particularly, to semiconductor device and its system including field effect transistor
Make method.
Background technique
Semiconductor device includes the integrated circuit being made of Metal Oxide Semiconductor Field Effect Transistor (MOSFET).With
Semiconductor device size and design rule be gradually reduced, the size of MOSFET is also gradually reduced.The diminution of MOSFET can make
The operating characteristic of semiconductor device deteriorates.Therefore, carrying out it is various research come manufacture with excellent properties and meanwhile overcome due to
The integrated caused semiconductor device limited of semiconductor device.
Summary of the invention
Some embodiments provide have the semiconductor device and its manufacturing method for improving electrical characteristics.
Some embodiments provide semiconductor device and its manufacturing methods, wherein the method maintains process allowance.
Accoding to exemplary embodiment, the disclosure is directed to a kind of semiconductor device, and the semiconductor device includes: gate electrode,
In substrate；Upper overlay pattern is located on gate electrode；And lower overlay pattern, between gate electrode and upper overlay pattern,
Wherein, lower overlay pattern includes: first part, between gate electrode and upper overlay pattern；And multiple second parts, from
A part extends on the corresponding side surface of overlay pattern, wherein in each of upper overlay pattern covering second part
Most top surface.
Accoding to exemplary embodiment, the disclosure is directed to a kind of semiconductor device, and the semiconductor device includes: gate electrode,
In substrate；Upper overlay pattern is located on gate electrode；Lower overlay pattern, between gate electrode and upper overlay pattern；And
Interlayer dielectric layer is located in substrate simultaneously covering grid electrode, upper overlay pattern and lower overlay pattern, wherein the top of upper overlay pattern
Surface is located at sustained height relative to the top surface of substrate and interlayer dielectric layer in the vertical direction, wherein lower overlay pattern
Most top surface be located at the height lower than the height of the top surface of interlayer dielectric layer relative to substrate in the vertical direction.
Accoding to exemplary embodiment, the disclosure is for a kind of method for manufacturing semiconductor device, which comprises in base
The interlayer dielectric layer for sacrificing gate pattern and covering sacrifice gate pattern is formed on bottom；Removal sacrifices gate pattern to be situated between in interlayer
Gap is formed in electric layer；Gate electrode is formed in gap；The inner surface and gate electrode of coverage gap are formed on interlayer dielectric layer
Top surface lower caldding layer；The mask pattern of a part of covering lower caldding layer is formed in gap；Remove lower caldding layer
Other parts are with overlay pattern under the formation in gap, wherein the other parts of lower caldding layer are not masked pattern covering；And
Form the upper overlay pattern of the remainder in filling gap.
Detailed description of the invention
Fig. 1 shows the plan view for showing semiconductor device accoding to exemplary embodiment.
Fig. 2 shows the cross-sectional views intercepted along the line I-I', line II-II' and line III-III' of Fig. 1.
Fig. 3 shows the perspective view for showing the gate structure of Fig. 1.
Fig. 4 to Figure 10 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, described to cut open
View shows the method for manufacture semiconductor device accoding to exemplary embodiment.
Figure 11 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, the section view diagram
Semiconductor device accoding to exemplary embodiment is gone out.
Figure 12 and Figure 13 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, described to cut open
View shows the method for manufacture semiconductor device accoding to exemplary embodiment.
Figure 14 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, the section view diagram
Semiconductor device accoding to exemplary embodiment is gone out.
Figure 15 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, the section view diagram
The method of manufacture semiconductor device accoding to exemplary embodiment is gone out.
Figure 16 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, the section view diagram
Semiconductor device accoding to exemplary embodiment is gone out.
Figure 17 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, the section view diagram
The method of manufacture semiconductor device accoding to exemplary embodiment is gone out.
Figure 18 shows the plan view for showing semiconductor device accoding to exemplary embodiment.
Figure 19 shows the cross-sectional view of line I-I' and line the II-II' interception along Figure 18.
Figure 20 shows the cross-sectional view of line I-I' and line the II-II' interception along Figure 18, and the section view shows basis and shows
The semiconductor device of example property embodiment.
Specific embodiment
Hereinafter, some embodiments be will be described in detail with reference to accompanying drawings, to help that inventive concept is expressly understood.
Fig. 1 shows the plan view for showing semiconductor device accoding to exemplary embodiment.Fig. 2 shows along Fig. 1's
The cross-sectional view of line I-I', line II-II' and line II-III' interception.Fig. 3 shows the perspective view for showing the gate structure of Fig. 1.
Referring to figs. 1 to Fig. 3, substrate 100 can be provided with the device isolation layer ST for limiting active patterns ACT on it.Base
Bottom 100 can be silicon base, germanium substrate or silicon-on-insulator (SOI) substrate, or may include silicon base, germanium substrate or insulation
Silicon (SOI) substrate on body.Device isolation layer ST may include such as oxide, nitride or nitrogen oxides.Active patterns ACT can
To extend on the direction D1 parallel with the top surface of substrate 100.In some embodiments, as shown in Figure 2, device isolation layer
ST can have the top surface substantially coplanar with the top surface of active patterns ACT.In other embodiments, with it is shown in Figure 2
Difference, device isolation layer ST can expose the side surface on the top of active patterns ACT.In this case, active patterns ACT can
To include the top (or fin) exposed by device isolation layer ST.
Substrate 100 can be provided with the gate structure GS across active patterns ACT on it.Gate structure GS can with
Extend on the parallel second direction D2 of the top surface of substrate 100.First direction D1 and second direction D2 can it is intersected with each other and
Vertically.Gate structure GS can be set as multiple in substrate 100.Multiple gate structure GS can be across active patterns
ACT extends, and can be separated from each other with D1 along a first direction.
Gate structure GS may include the gate electrode GE extended across active patterns ACT, the covering in gate electrode GE
Pattern CAP, the gate dielectric pattern GI between gate electrode GE and substrate 100 and on the side surface of gate electrode GE
Gate spacer GSP.Gate electrode GE can have the linearity configuration extended in a second direction d 2.Gate spacer GSP can be with
It is arranged in correspondence on the opposite flank of gate electrode GE, and each of gate spacer GSP can be along gate electrode GE
Corresponding side surface extend in a second direction d 2.Gate dielectric pattern GI can be along the bottom surface of gate electrode GE second
Extend on the D2 of direction, and can be along the side surface between gate electrode GE and each gate spacer GSP of gate electrode GE
Extend in a second direction d 2.Gate electrode GE may include conductive metal nitride (for example, titanium nitride, tantalum nitride etc.) and metal
One of (for example, aluminium, tungsten etc.) or more.Gate electrode GE may include the metal material with work function different from each other
Material.Gate dielectric pattern GI may include at least one layer of high k dielectric layer.For example, gate dielectric pattern GI may include hafnium oxide,
One of hafnium silicate, zirconium oxide and zirconium silicate or more.Gate spacer GSP may include nitride (for example, nitridation
Silicon).
Overlay pattern CAP can extend in a second direction d 2 along the top surface of gate electrode GE.Overlay pattern CAP can be with
Upper overlay pattern 120 including being located in gate electrode GE and the lower covering between gate electrode GE and upper overlay pattern 120
Pattern 110.When watching in the plan view, each of lower overlay pattern 110 and upper overlay pattern 120 can be along gate electrodes
The top surface of GE extends in a second direction d 2.Lower overlay pattern 110 can separate upper overlay pattern 120 with gate electrode GE.
For example, upper overlay pattern 120 can be spaced apart across lower overlay pattern 110 with gate electrode GE in the vertical direction.Overlay pattern
CAP can also include the boundary between upper overlay pattern 120 and lower overlay pattern 110, and upper overlay pattern 120 is under
Boundary between overlay pattern 110 may include oxide.
Lower overlay pattern 110 may include in the horizontal direction between gate electrode GE and upper overlay pattern 120
A part of 110P1 and in the vertical direction from the corresponding side surface that first part 110P1 extends to upper overlay pattern 120
Second part 110P2.The second part 110P2 of lower overlay pattern 110 can be arranged in correspondence in the opposite of upper overlay pattern 120
On side surface, and each of second part 110P2 can be along the corresponding side surface of upper overlay pattern 120 in second party
Extend on D2.The most top surface of lower overlay pattern 110 can be most top surface in each of second part 110P2.At it
Different from shown in its embodiment, each of the second part 110P2 of lower overlay pattern 110 can have far from base
The shape being tapered on the direction at bottom 100.For example, each of second part 110P2 can have in the first direction dl
Width, the width in each of second part 110P2 in the first direction dl can be along the direction far from substrate 100
(that is, in the vertical direction) reduces.When watching in section, lower overlay pattern 110 can be shaped as U-shaped.Gate dielectric figure
Case GI can extend between gate electrode GE in each of gate spacer GSP, to contact with lower overlay pattern 110.Example
Such as, overlay pattern 110 under the most top surface of gate dielectric pattern GI can contact at the region below second part 110P2
Lower surface.
It will be appreciated that when element is referred to as " connection " or " in conjunction with " to another element or " " another element "upper",
The element can be directly connected to or be bonded directly to another element, perhaps directly on another element or can be with
There are intermediary elements.On the contrary, working as element is referred to as " being directly connected to " another element, " binding directly " another element or " direct
" another element "upper" when, be not present intermediary element.Other words for describing relationship between element should be in a similar way
Explain (for example, " ... between " and " between directly existing ... ", " adjacent " and " direct neighbor " etc.).However, unless up and down
Text is otherwise noted, otherwise " contact " as the term is used herein or " with ... contact " indicate to be directly connected to (that is, touching).
Upper overlay pattern 120 can cover the most top surface 110U of lower overlay pattern 110.For example, upper overlay pattern 120 can
To cover most top surface 110U in each of the second part 110P2 of lower overlay pattern 110.Upper overlay pattern 120 can be with
The most top surface 110U of lower overlay pattern 110 is contacted.The most top surface 110U of lower overlay pattern 110 can phase in the vertical direction
Substrate 100 is located at the height lower than the height of the top surface 120U of upper overlay pattern 120.The one of upper overlay pattern 120
Part can be placed between the second part 110P2 of lower overlay pattern 110.Described a part of upper overlay pattern 120 can fill out
Fill the space between the second part 110P2 of lower overlay pattern 110.
Upper overlay pattern 120 may include main body 120BP and from main body 120BP towards the protrusion outstanding of substrate 100
120PP.Main body 120BP can have the first width W1, and protrusion 120PP can have the second width less than the first width W1
W2.First width W1 can be the maximum width of the main body 120BP in the measurement of D1 along a first direction, and the second width W2 can be
The maximum width of protrusion 120PP in the measurement of D1 along a first direction.In example shown in figure 2, the width of main body 120BP
It can be constant width in the vertical direction with the width of protrusion 120PP.In some embodiments, different from shown in, when
Each of second part 110P2 of lower overlay pattern 110 have along vertical direction far from substrate 100 direction on gradually
When the shape to attenuate, the second width W2 of protrusion 120PP can be increased up in the side far from substrate 100 along vertical direction.
The protrusion 120PP of upper overlay pattern 120 can be placed between the second part 110P2 of lower overlay pattern 110, upper overlay pattern
120 main body 120BP can cover most top surface 110U in each of the second part 110P2 of lower overlay pattern 110.On cover
The main body 120BP of lid pattern 120 can most top surface 110U in each of the second part 110P2 with lower overlay pattern 110
Contact.The most top surface 110U of lower overlay pattern 110 can be located at relative to substrate 100 than upper overlay pattern in the vertical direction
At the low height of the height of the top surface 120U of 120 main body 120BP.It is every in lower overlay pattern 110 and upper overlay pattern 120
A may include nitride (for example, silicon nitride).
Source/drain region SD can be arranged in active patterns ACT on the opposite side of gate structure GS.For example, source/drain region SD
It can be formed in active patterns ACT between the adjacent gate spacer GSP in gate spacer GSP.Active patterns ACT
It can have the part for being located at below gate structure GS and being stacked in the vertical direction with gate structure GS, and active patterns
The part of ACT may be used as channel region CH.Interlayer dielectric layer 130 can be set in substrate 100, and cover gate structure
GS and source/drain region SD.For example, interlayer dielectric layer 130 can surround the side surface of gate structure GS and cover source/drain in Fig. 2
Area SD.Interlayer dielectric layer 130 can have and the top surface 120U of upper overlay pattern 120 (or the main body with upper overlay pattern 120
The top surface 120U of 120BP) substantially coplanar top surface 130U.For example, the top surface 130U of interlayer dielectric layer 130 can with it is upper
The top surface 120U of overlay pattern 120 is located at same vertical height.The most top surface 110U of lower overlay pattern 110 (covers under or
Most top surface 110U in each of the second part 110P2 of lid pattern 110) it can be in the vertical direction relative to substrate 100
At the height low positioned at the height of the top surface 130U than interlayer dielectric layer 130.Interlayer dielectric layer 130 may include for example aoxidizing
Silicon layer.
Contact 140 can be set on the opposite side of gate structure GS.Contact 140 can penetrate interlayer dielectric layer
130 with substrate 100 to be electrically connected.Contact 140 can be electrically connected to corresponding source/drain region on the opposite side of gate structure GS
SD.Contact 140 may include one of doped semiconductor, metal, metal silicide and conductive metal nitride or more
Kind.
Gate structure GS may include the first area R1 and the second area R2, and the opposite side of the first area R1 is provided with contact 140,
The opposite side of second area R2 is set as not having contact 140.At the first area R1 of gate structure GS, upper overlay pattern 120
It can be contacted with contact 140.For example, the main body 120BP of upper overlay pattern 120 can at the first area R1 of gate structure GS
To be contacted with contact 140.At the second area R2 of gate structure GS, gate spacer GSP extends to overlay pattern CAP
Corresponding side surface on, most top surface in each of gate spacer GSP can be with the top surface of interlayer dielectric layer 130
130U is substantially coplanar.In some embodiments, gate spacer GSP can have as gate spacer GSP is closer to interlayer
The top surface 130U of dielectric layer 130 and the shape being tapered.Each of gate spacer GSP can be placed in overlay pattern
Between CAP and interlayer dielectric layer 130, and it can be contacted with overlay pattern CAP.For example, at the second area R2 of gate structure GS,
Each of the second part 110P2 of lower overlay pattern 110 can be placed between the protrusion 120PP of overlay pattern 120 and grid
Between each of spacing body GSP, while being contacted with each of gate spacer GSP.At the second area R2 of gate structure GS,
The main body 120BP of upper overlay pattern 120 can be contacted with gate spacer GSP.
Gate structure GS and source/drain region SD may be constructed field effect transistor.For example, gate structure GS and source/drain region SD
It may be constructed p type field effect transistor.It is connect although it is not shown, interlayer dielectric layer 130 can be provided with to be connected on it
The wiring of contact element 140.Wiring (not shown) can be electrically connected to source/drain region SD by contact 140.
Fig. 4 to Figure 10 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, described to cut open
View shows the method for manufacture semiconductor device accoding to exemplary embodiment.
Referring to Fig. 4, device isolation layer ST can be formed in substrate 100 to limit active patterns ACT.STI can be used
(shallow trench isolation) technique is to form device isolation layer ST.Active patterns ACT can be formed as extending in the first direction dl.
It can be sequentially formed etching stopping layer (not shown) in substrate 100 and sacrifice grid layer (not shown).Etching
Stop-layer may include such as silicon oxide layer.Sacrificing grid layer may include the material for having etching selectivity for etching stopping layer
Material.Sacrificing grid layer may include such as polysilicon.It can make sacrificial gate pole pattern layers to be formed and sacrifice gate pattern 160.
Sacrificing gate pattern 160 can be formed as extending in a second direction d 2 and across active patterns ACT.Sacrifice gate pattern
160 formation may include gate mask pattern 170 being formed on sacrificing grid layer and by using gate mask pattern 170
Sacrifice grid layer is etched as etching mask.Gate mask pattern 170 may include such as silicon nitride.Sacrifice the erosion of grid layer
Quarter may include executing the etch process for having etching selectivity for etching stopping layer.Formed sacrifice gate pattern 160 it
Afterwards, etching stopping layer can be removed from the opposite side for sacrificing gate pattern 160, allows to sacrificing below gate pattern 160
Form etch stop pattern 150.Etch stop pattern 150 can be along the bottom surface of sacrifice gate pattern 160 in second direction
Extend on D2.
Gate spacer GSP can be accordingly formed on the side surface for sacrificing gate pattern 160.Gate spacer GSP
It may include such as silicon nitride.The formation of gate spacer GSP may include being formed on the base for sacrificing gate pattern 160
Gate spacer layer (not shown) is formed on bottom 100 and is etched anisotropically through gate spacer layer.
Source/drain region SD can be formed in the active patterns ACT on opposite sides for sacrificing gate pattern 160.Source/drain region SD
Formation may include for example execute selective epitaxial growth process with sacrifice gate pattern 160 active figure on opposite sides
Extension pattern is formed in case ACT.Selectively, the formation of source/drain region SD may include executing ion implantation technology to sacrifice
Impurity doped region is formed in the active patterns ACT on opposite sides of gate pattern 160.
Referring to Fig. 5, interlayer dielectric layer 130 can be formed in substrate 100, and gate pattern 160 and source/drain are sacrificed with covering
Area SD.Interlayer dielectric layer 130 may include such as silica.Interlayer dielectric layer 130 can be made to be planarized to expose sacrifice grid
The top surface of pattern 160 and the top surface of gate spacer GSP.Grid can be removed when planarizing interlayer dielectric layer 130
Mask pattern 170.
Referring to Fig. 6, it can remove and sacrifice gate pattern 160 and etch stop pattern 150.It therefore, can be in interlayer dielectric
Gap 180 is formed between gate spacer GSP in layer 130.For example, between being formed between each pair of gate spacer GSP
Gap 180.The formation in gap 180 may include having etching choosing for interlayer dielectric layer 130 and gate spacer GSP by executing
The etch process of selecting property sacrifices gate pattern 160 and etch stop pattern 150 to etch.
Gate dielectric pattern GI and gate electrode GE can be formed in gap 180.For example, gate dielectric pattern GI and grid electricity
The formation of pole GE may include that the gate dielectric (not shown) for being partially filled with gap 180 is formed on interlayer dielectric layer 130,
The gate electrode layer (not shown) for being filled up completely gap 180 is formed on gate dielectric, and makes gate dielectric and gate electrode
Layer planarization is exposed until the top surface 130 of interlayer dielectric layer.Flatening process can expose the top table of gate spacer GSP
Face.Gate electrode layer can be etched on the top of gate electrode layer, until gate electrode layer reach in gap 180 desired thickness with
Form gate electrode GE.Furthermore, it is possible to gate dielectric not by gate electrode GE cover top on etch gate dielectric, with
Form gate dielectric pattern GI.Gate dielectric pattern GI can be placed between gate electrode GE and substrate 100, and can be in grid electricity
Extend between each of pole GE and gate spacer GSP.In some embodiments, gate dielectric pattern GI can have perpendicular
Top surface of the histogram upwards relative to substrate 100 and gate electrode GE is located at the most top surface at basic same level.Gate electrode GE
The lower part in gap 180 can be filled with gate dielectric pattern GI.
Referring to Fig. 7, lower caldding layer 182 can be formed, on interlayer dielectric layer 130 to be partially filled with the upper of gap 180
Portion.Lower caldding layer 182 can be formed as conformally the inner surface on the top of coverage gap 180, the top surface of gate electrode GE and
The most top surface of gate dielectric pattern GI.The formation of lower caldding layer 182 may include in H2The relatively low gas of plasma density
The first depositing operation is executed under atmosphere.For example, the first depositing operation may include indirect H2Corona treatment does not include H2Deng from
Daughter processing.First depositing operation can be (or may include) in H2The original executed under the relatively low atmosphere of plasma density
Sublayer depositing operation.Lower caldding layer 182 may include such as silicon nitride.
Mask pattern 185 can be formed in gap 180 to cover a part of lower caldding layer 182.Mask pattern 185
Formation may include the mask layer to form the remainder on top in filling gap 180 and etching mask layer until mask layer exists
Reach desired thickness in the top in gap 180 in the vertical direction.Mask pattern 185 may include such as spin-coating hardmask
(SOH) material (for example, carbon-containing bed).
Referring to Fig. 8, the other parts for not being masked the covering of pattern 185 of lower caldding layer 182 can be removed, to cover under formation
Lid pattern 110.Lower overlay pattern 110 can be placed between mask pattern 185 and gate electrode GE and mask pattern 185 and grid
Between dielectric pattern GI, and it can extend between mask pattern 185 and each gate spacer GSP.Lower overlay pattern 110
Most top surface 110U can be located in the vertical direction relative to the top surface of substrate 100 and mask pattern 185 it is substantially same
At level.
Referring to Fig. 9, mask pattern 185 can be removed.It can be covered by executing cineration technics and/or stripping technology to remove
Mould pattern 185.After removing mask pattern 185, between upper caldding layer 187 being formed on interlayer dielectric layer 130 to fill
The remainder of gap 180.The formation of upper caldding layer 187 may include in H2Is executed under the relatively high atmosphere of plasma density
Two depositing operations.For example, the second depositing operation may include direct H2Corona treatment.Second depositing operation can be (or
May include) in H2The atom layer deposition process executed under the relatively high atmosphere of plasma density.Upper caldding layer 187 can wrap
Include such as silicon nitride.Due in H2Plasma density ratio executes the H of the atmosphere of the first depositing operation2Plasma density is opposite
Execute the second depositing operation under high atmosphere, thus upper caldding layer 187 can have it is smaller than the impurity content of lower caldding layer 182
Impurity content.Therefore, upper caldding layer 187 can be formed to have the density bigger than the density of lower caldding layer 182.
Referring to Fig.1 0, the planarization of upper caldding layer 187 can be made until exposure interlayer dielectric layer 130.As flatening process
As a result, upper overlay pattern 120 can be formed locally in gap 180.Lower overlay pattern 110 and upper overlay pattern 120 can
To constitute overlay pattern CAP.Gate structure GS can be by between gate electrode GE, gate dielectric pattern GI, overlay pattern CAP and grid
Spacing body GSP is constituted or is formed.
Contact hole 140H can be formed in the interlayer dielectric layer on opposite sides 130 of gate structure GS.Contact hole 140H
Source/drain region SD can be exposed on the opposite side of gate structure GS.The formation of contact hole 140H may include executing etch process
To etch interlayer dielectric layer under the etching condition that there is etching selectivity for overlay pattern CAP and gate spacer GSP
130.Since upper caldding layer 187 is formed to have the density bigger than the density of lower caldding layer 182, when execute etch process with
When forming contact hole 140H, upper overlay pattern 120 can show bigger than the etch-resistance of lower overlay pattern 110 anti-etching
Property.
In general, the overlay pattern on gate electrode can be formed as include silicon nitride single pattern.It can be by H2Deng
The depositing operation that executes under the relatively high atmosphere of plasma density forms overlay pattern.In this case, when executing deposition
When technique, hydrogen can be diffused into gate electrode, therefore, can be difficult to control the threshold voltage of gate electrode.
According to some embodiments, overlay pattern CAP can be formed as including upper overlay pattern 120 and lower overlay pattern 110
Multilayered structure.It can be by H2The second depositing operation is executed under the relatively high atmosphere of plasma density to form upper covering
Pattern 120, and can be by H2The first depositing operation is executed under the relatively low atmosphere of plasma density to cover to be formed down
Lid pattern 110.It minimizes or subtracts in such a case, it is possible to be diffused into hydrogen in gate electrode GE
Few hydrogen is diffused into gate electrode GE, and hereafter, lower overlay pattern 110 can be in the second deposition for being used to form upper overlay pattern 120
Inhibit during technique or hydrogen is prevented to be diffused into gate electrode GE.Therefore, can more easily control grid electrode GE threshold voltage.
In addition, upper overlay pattern 120 can be shown than lower covering when executing etch process to form contact hole 140H
The big etch-resistance of the etch-resistance of pattern 110.Upper overlay pattern 120 can be formed as covering the most top of lower overlay pattern 110
Surface 110U, in this case, lower overlay pattern 110 can be minimum during the etch process for being used to form contact hole 140H
Ground exposure.Therefore, during the etch process for being used to form contact hole 140H, it may be possible to make the loss of overlay pattern CAP most
Smallization or the loss for preventing overlay pattern CAP, and it is able to maintain the process allowance of etch process.
Therefore, not only process allowance can be safely obtained in manufacture semiconductor device, but also semiconductor device may be used also
With the improvement with electrical characteristics.
Referring back to Fig. 1 and Fig. 2, contact 140 can be formed in contact hole 140H.The formation of contact 140 can be with
Including forming the conductive layer of filling contact hole 140H on interlayer dielectric layer 130 and making conductive layer planarization until exposure interlayer
Dielectric layer 130.Contact 140 may include in such as doped semiconductor, metal, metal silicide and conductive metal nitride
It is one or more of.Although it is not shown, can be formed on interlayer dielectric layer 130 wiring (not shown) with contact
140 connections.Wiring can be electrically connected to source/drain region SD by contact 140.
Figure 11 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, the section view diagram
Semiconductor device accoding to exemplary embodiment is gone out.To simplify the explanation, description below will focus on and referring to figs. 1 to figure
The difference of 3 semiconductor devices discussed.
Referring to Fig.1 and Figure 11, overlay pattern CAP may include upper overlay pattern 120 and lower overlay pattern 110.Upper covering
Pattern 120 can be spaced apart across lower overlay pattern 110 with gate electrode GE.In addition, upper overlay pattern 120 can be across lower covering
Each of pattern 110 and gate spacer GSP are spaced apart.For example, lower overlay pattern 110 can be located at upper overlay pattern 120
Between gate electrode GE and between upper overlay pattern 120 and gate spacer GSP.
Lower overlay pattern 110 may include first part 110P1 between gate electrode GE and upper overlay pattern 120 and
Second part 110P2 from the corresponding side surface that first part 110P1 extends to upper overlay pattern 120.When in section
When viewing, lower overlay pattern 110 can be shaped as U-shaped.Gate dielectric pattern GI can each of gate spacer GSP with
Extend between gate electrode GE, to be contacted with lower overlay pattern 110.For example, the most top surface of gate dielectric pattern GI can be with
The following table face contact of lower overlay pattern 110.It is connect in addition, each of gate spacer GSP can have with lower overlay pattern 110
The most top surface of touching.In some embodiments, the most top surface of gate spacer GSP can be one from gate spacer GSP
A side surface extends to another side surface of gate spacer GSP and the downwards inclined surface of overlay pattern 110.
Upper overlay pattern 120 may include main body 120BP and from main body 120BP towards the protrusion outstanding of substrate 100
120PP.Main body 120BP can have the first width W1, and protrusion 120PP can have second width smaller than the first width W1
W2.In some embodiments, the first width W1 can be the first width range, and the second width W2 can be the second width range,
First width range can be bigger than the second width range.For example, main body 120BP can have first reduced in the vertical direction
Width W1 (for example, the first width is larger at the bottom of main body 120BP and smaller at the top of main body 120BP), protrusion
120PP can have increase in the vertical direction the second width W2 (for example, the second width at the bottom of protrusion 120PP compared with
It is small and larger at the top of protrusion 120PP).In this example, the widest first width W1 of main body 120BP compares protrusion
The widest second width W2 of 120PP is big.
The protrusion 120PP of upper overlay pattern 120 can be placed between the second part 110P2 of lower overlay pattern 110, above be covered
In each of a part of second part 110P2 that can cover lower overlay pattern 110 of the main body 120BP of lid pattern 120 most
Top surface 110U.The most top surface 110U of lower overlay pattern 110 can be located at relative to substrate 100 than above covering in the vertical direction
At the low height of the height of the top surface 120U of the main body 120BP of lid pattern 120.The top surface 130U of interlayer dielectric layer 130 can
It is basic with the top surface 120U (or top surface 120U with the main body 120BP of upper overlay pattern 120) with upper overlay pattern 120
It is coplanar.
Gate structure GS may include the first area R1 and the second area R2, and the opposite side of the first area R1 is provided with contact 140,
The opposite side of second area R2 is set as not having contact 140.At the first area R1 of gate structure GS, overlay pattern CAP can
To be contacted with contact 140.For example, lower overlay pattern 110 can be with contact 140 at the first area R1 of gate structure GS
Contact.For example, at the first area R1 of gate structure GS, each of second part 110P2 of lower overlay pattern 110 can be with
Contact 140 contacts, and can be placed between contact 140 and the protrusion 120PP of upper overlay pattern 120.Lower overlay pattern
110 second part 110P2 can separate the protrusion 120PP of upper overlay pattern 120 and contact 140.In gate structure GS
The first area R1 at, the main body 120BP of upper overlay pattern 120 can be contacted with contact 140.In the secondth area of gate structure GS
At R2, overlay pattern CAP can be contacted with interlayer dielectric layer 130.For example, at the second area R2 of gate structure GS, lower covering
Each of second part 110P2 of pattern 110 can be contacted with interlayer dielectric layer 130, and can be placed in interlayer dielectric layer
Between 130 and the protrusion 120PP of upper overlay pattern 120.The second part 110P2 of lower overlay pattern 110 can be by upper coverage diagram
The protrusion 120PP of case 120 and interlayer dielectric layer 130 separate.At the second area R2 of gate structure GS, upper overlay pattern 120
Main body 120BP can be contacted with interlayer dielectric layer 130.
Figure 12 and Figure 13 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, described to cut open
View shows the method for manufacture semiconductor device accoding to exemplary embodiment.For example, Figure 12 and Figure 13 show manufacture figure
The illustrative methods of 11 semiconductor device.To simplify the explanation, description below will focus on is begged for referring to Fig. 4 to Figure 10
The difference of the manufacturing method of opinion.
As referring to discussing fig. 4 to fig. 6, substrate 100 can be provided on it limit the device of active patterns ACT every
Absciss layer ST and the sacrifice gate pattern 160 extended across active patterns ACT.Erosion can be formed below gate pattern 160 sacrificing
It carves and stops pattern 150, and gate spacer GSP can be formed on the corresponding side surface for sacrificing gate pattern 160.It can be with
Source/drain region SD is formed in the active patterns ACT on opposite sides for sacrificing gate pattern 160, can form interlayer dielectric layer 130
Gate pattern 160 and source/drain region SD are sacrificed with covering.Can remove sacrifice gate pattern 160 and etch stop pattern 150 with
Gap 180 is formed between gate spacer GSP in interlayer dielectric layer 130.Gate electrode GE and gate dielectric pattern can be formed
GI is to fill the lower part in gap 180.
Referring to Fig.1 2, the top of gate spacer GSP can be removed, therefore, interlayer dielectric layer 130 can be arranged wherein
There is the sunk area 181 of the inner surface of exposed interlayer dielectric layer 130.Sunk area 181 can be by the interior table of interlayer dielectric layer 130
The most top surface restriction in face, the top surface of gate electrode GE, the most top surface of gate dielectric pattern GI and gate spacer GSP.
The removal on the top of gate spacer GSP may include executing for interlayer dielectric layer 130, gate electrode GE and gate dielectric pattern
GI has the etch process of etching selectivity.
Lower caldding layer 182 can be formed, on interlayer dielectric layer 130 to be partially filled with sunk area 181.Lower caldding layer
182 can be formed as the inner surface for conformally covering sunk area 181.Mask pattern can be formed in sunk area 181
185, to partly cover lower caldding layer 182.The formation of lower caldding layer 182 and mask pattern 185 can be discussed with referring to Fig. 7
Manufacturing method it is essentially identical.
Referring to Fig.1 3, the other parts for not being masked the covering of pattern 185 of lower caldding layer 182 can be removed, under being formed
Overlay pattern 110.Lower overlay pattern 110 can be placed between mask pattern 185 and gate electrode GE and mask pattern 185 and grid
Between the dielectric pattern GI of pole, and extend on the side surface of mask pattern 185.The most top surface of lower overlay pattern 110
110U can be located at basic same level relative to substrate 100 and the top surface of mask pattern 185 in the vertical direction.
Subsequent technique can be essentially identical with the manufacturing method that is discussed referring to Fig. 2, Fig. 9 and Figure 10.
Figure 14 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, the section view diagram
Semiconductor device accoding to exemplary embodiment is gone out.To simplify the explanation, description below will focus on and referring to figs. 1 to figure
The difference of 3 semiconductor devices discussed.
It may include the upper overlay pattern 120 in gate electrode GE and be located at Figure 14, overlay pattern CAP referring to Fig.1
Lower overlay pattern 110 between gate electrode GE and upper overlay pattern 120.When watching in the planes, lower overlay pattern 110 and upper
Each of overlay pattern 120 can extend in a second direction d 2 along the top surface of gate electrode GE.Upper overlay pattern 120 can
To be spaced apart across lower overlay pattern 110 with gate electrode GE.For example, lower overlay pattern 110 can be located at upper overlay pattern 120 with
Between gate electrode GE and between upper overlay pattern 120 and gate dielectric pattern GI.
When watching in section, each of lower overlay pattern 110 and upper overlay pattern 120 can have rectangle shape
Shape.Gate dielectric pattern GI can extend between gate electrode GE in each of gate spacer GSP, thus with lower coverage diagram
Case 110 contacts.For example, the most top surface of gate dielectric pattern GI can be contacted with the bottom surface of lower overlay pattern 110.Upper covering
Pattern 120 can cover the most top surface 110U of lower overlay pattern 110, the top surface 130U of interlayer dielectric layer 130 can with it is upper
The top surface 120U of overlay pattern 120 is substantially coplanar.The most top surface 110U of lower overlay pattern 110 can phase in the vertical direction
Substrate 100 is located at the height lower than the height of the top surface 130U of interlayer dielectric layer 130.Upper overlay pattern 120 can be with
It is contacted with the most top surface 110U of lower overlay pattern 110.
Gate structure GS may include the first area R1 and the second area R2, and the opposite side of the first area R1 is provided with contact 140,
The opposite side of second area R2 is set as not having contact 140.At the first area R1 of gate structure GS, upper overlay pattern 120
It can be contacted with contact 140.At the second area R2 of gate structure GS, gate spacer GSP extends to overlay pattern
On the corresponding side surface of CAP, most top surface in each of gate spacer GSP can be with the top table of interlayer dielectric layer 130
Face 130U is substantially coplanar.Each of gate spacer GSP can be placed between overlay pattern CAP and interlayer dielectric layer 130, and
And it is contacted with lower overlay pattern 110 and upper overlay pattern 120.
Figure 15 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, the section view diagram
The method of manufacture semiconductor device accoding to exemplary embodiment is gone out.For example, Figure 15 shows the semiconductor dress of manufacture Figure 14
The illustrative methods set.To simplify the explanation, the manufacturing method that description below will focus on and be discussed referring to Fig. 4 to Figure 10
Difference.
As referring to discussing fig. 4 to fig. 6, substrate 100 can be provided on it limit the device of active patterns ACT every
Absciss layer ST and sacrifice gate pattern 160 across active patterns ACT.It can stop sacrificing to be formed to etch below gate pattern 160
Only pattern 150, and gate spacer GSP can be formed on the corresponding side surface for sacrificing gate pattern 160.It can be sacrificial
Source/drain region SD is formed in the active patterns ACT on opposite sides of domestic animal gate pattern 160, can form interlayer dielectric layer 130 to cover
Lid sacrifices gate pattern 160 and source/drain region SD.It can remove and sacrifice gate pattern 160 and etch stop pattern 150 in grid
Gap 180 is formed between spacer GSP.Gate electrode GE and gate dielectric pattern GI can be formed to fill the lower part in gap 180.
Referring to Fig.1 5, lower caldding layer (not shown) can be formed on interlayer dielectric layer 130 to fill the upper of gap 180
Portion.Lower caldding layer can be formed as the top for substantially completely filling gap 180.The formation of lower caldding layer may include execution
One depositing operation.It can be in its H2The first depositing operation is executed under the relatively low atmosphere of plasma density.For example, the first deposition
Technique may include indirect H2Corona treatment does not include H2Corona treatment.Lower caldding layer may include for example nitrogenizing
Silicon.Lower caldding layer can be etched until reaching desired thickness or depth in the vertical direction in gap 180, to cover under formation
Lid pattern 110.
Subsequent technique can be essentially identical with the manufacturing method that is discussed referring to Fig. 2, Fig. 9 and Figure 10.
Figure 16 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, the section view diagram
Semiconductor device accoding to exemplary embodiment is gone out.To simplify the explanation, description below will focus on and referring to figs. 1 to figure
The difference of 3 semiconductor devices discussed.
Referring to Fig.1 and Figure 16, overlay pattern CAP may include upper overlay pattern 120 and gate electrode GE in gate electrode GE
With the lower overlay pattern 110 between upper overlay pattern 120.When watching in the plan view, lower overlay pattern 110 and upper overlay pattern
Each of 120 can extend in a second direction d 2 along the top surface of gate electrode GE.Upper overlay pattern 120 can be under
Overlay pattern 110 is spaced apart with gate electrode GE.In addition, upper overlay pattern 120 can be across lower overlay pattern 110 and gate spacer
Each of part GSP is spaced apart.For example, lower overlay pattern 110 can between upper overlay pattern 120 and gate electrode GE and
Between upper overlay pattern 120 and gate spacer GSP.
Gate dielectric pattern GI can extend between gate electrode GE in each of gate spacer GSP, thus under
Overlay pattern 110 contacts.Each of gate spacer GSP can have the most top surface contacted with lower overlay pattern 110.On
Overlay pattern 120 can cover the most top surface 110U of lower overlay pattern 110, and the top surface 130U of interlayer dielectric layer 130 can be with
It is substantially coplanar with the top surface 120U of upper overlay pattern 120.The most top surface 110U of lower overlay pattern 110 can be in vertical direction
On be located at the height lower than the height of the top surface 130U of interlayer dielectric layer 130 relative to substrate 100.Upper overlay pattern 120
It can be contacted with the most top surface 110U of lower overlay pattern 110.In some embodiments, the most top surface of gate spacer GSP
It can be and extend to another side surface of gate spacer GSP from a side surface of gate spacer GSP and cover downwards
The inclined surface of lid pattern 110.
Gate structure GS may include the first area R1 and the second area R2, and the opposite side of the first area R1 is provided with contact 140,
The opposite side of second area R2 is set as not having contact 140.At the first area R1 of gate structure GS, lower overlay pattern 110
It can be contacted with contact 140 with upper overlay pattern 120.At the second area R2 of gate structure GS, lower overlay pattern 110 and upper
Overlay pattern 120 can be contacted with interlayer dielectric layer 130.
Figure 17 shows the cross-sectional view of line I-I', line II-II' and line the III-III' interception along Fig. 1, the section view diagram
The method of manufacture semiconductor device accoding to exemplary embodiment is gone out.For example, Figure 17 shows the semiconductor dresses of manufacture Figure 16
The illustrative methods set.To simplify the explanation, the manufacturing method that description below will focus on and be discussed referring to Fig. 4 to Figure 10
Difference.
As referring to discussing fig. 4 to fig. 6, substrate 100 can be provided on it limit the device of active patterns ACT every
Absciss layer ST and sacrifice gate pattern 160 across active patterns ACT.It can stop sacrificing to be formed to etch below gate pattern 160
Only pattern 150, and gate spacer GSP can be formed on the corresponding side surface for sacrificing gate pattern 160.It can be sacrificial
Source/drain region SD is formed in the active patterns ACT on opposite sides of domestic animal gate pattern 160, can form interlayer dielectric layer 130 to cover
Lid sacrifices gate pattern 160 and source/drain region SD.It can remove and sacrifice gate pattern 160 and etch stop pattern 150 in grid
Gap 180 is formed between spacer GSP.Gate electrode GE and gate dielectric pattern GI can be formed to fill the lower part in gap 180.
Referring to Fig.1 7, the top of gate spacer GSP can be removed, therefore, interlayer dielectric layer 130 can be arranged wherein
There is the sunk area 181 of the inner surface of exposed interlayer dielectric layer 130.Sunk area 181 can be by the interior table of interlayer dielectric layer 130
The most top surface restriction in face, the top surface of gate electrode GE, the most top surface of gate dielectric pattern GI and gate spacer GSP.Grid
The removal on the top of interpolar spacing body GSP may include executing for interlayer dielectric layer 130, gate electrode GE and gate dielectric pattern GI
Etch process with etching selectivity.
Lower caldding layer (not shown) can be formed, on interlayer dielectric layer 130 to fill sunk area 181.Lower caldding layer
It can be formed as substantially completely filling sunk area 181.The formation of lower caldding layer may include executing the first depositing operation.It can
In H2The first depositing operation is executed under the relatively low atmosphere of plasma density.For example, between the first depositing operation may include
Meet H2Corona treatment does not include H2Corona treatment.Lower caldding layer may include such as silicon nitride.It can etch down and cover
Cap rock until reaching desired thickness or depth in the vertical direction in sunk area 181, to form lower overlay pattern 110.
Subsequent technique can be essentially identical with the manufacturing method that is discussed referring to Fig. 2, Fig. 9 and Figure 10.
Figure 18 shows the plan view for showing semiconductor device accoding to exemplary embodiment.Figure 19 is shown along Figure 18's
The cross-sectional view of line I-I' and line II-II' interception.To simplify the explanation, description below will focus on and referring to figs. 1 to Fig. 3 institute
The difference of the semiconductor device of discussion.
8 and Figure 19 referring to Fig.1, gate structure GS may include the first grid structure GS1 being stacked with the first channel region CH1
With the second grid structure GS2 being stacked with the second channel region CH2.First channel region CH1 can have than the second channel region CH2's
The small channel length (for example, length in the direction di) of channel length (for example, length in the direction di).In some implementations
Example in, each of first grid structure GS1 and second grid structure GS2 may include gate electrode GE, gate dielectric pattern GI,
Gate spacer GSP and overlay pattern CAP.Overlay pattern CAP may include upper overlay pattern 120 and lower overlay pattern 110.It removes
Except grid length different from each other, first grid structure GS1 and second grid structure GS2 may be constructed such that basic each other
It is identical.For example, the width of first grid structure GS1 in the direction di can compare second gate in the embodiment of Figure 18 and Figure 19
The width of pole structure GS2 in the direction di is small.
Figure 20 shows the cross-sectional view of line I-I' and line the II-II' interception along Figure 18, and the section view shows basis and shows
The semiconductor device of example property embodiment.To simplify the explanation, following description will focus on and be discussed referring to figs. 1 to Fig. 3
The difference of semiconductor device.
8 and Figure 20 referring to Fig.1, gate structure GS may include the first grid structure GS1 being stacked with the first channel region CH1
With the second grid structure GS2 being stacked with the second channel region CH2.First channel region CH1 can have than the second channel region CH2's
The small channel length (for example, length in the direction di) of channel length (for example, length in the direction di).In some implementations
In example, each of first grid structure GS1 and second grid structure GS2 may include gate electrode GE, gate dielectric pattern GI
With gate spacer GSP.First grid structure GS1 may include overlay pattern CAP.Overlay pattern CAP may include upper covering
Pattern 120 and lower overlay pattern 110.On the contrary, second grid structure GS2 may include single layer overlay pattern CAP_1.Single layer covering
Pattern CAP_1 may include material identical with the material of upper overlay pattern 120, and can be by executing and being used to form
The depositing operation of overlay pattern 120 identical depositing operation is formed.Only it is supplied to lower 110 property of can choose of overlay pattern
One gate structure GS1.Single layer overlay pattern CAP_1 can with include gate electrode GE and grid in second grid structure GS2
Dielectric pattern GI contact.Single layer covering can be placed in including each of the gate spacer GSP in second grid structure GS2
Between pattern CAP_1 and interlayer dielectric layer 130.
According to certain exemplary embodiments, overlay pattern CAP can be formed as including upper overlay pattern 120 and lower coverage diagram
The multilayered structure of case 110.Lower overlay pattern 110 can be by H2First executed under the relatively low atmosphere of plasma density
Depositing operation is formed.It is minimized in such a case, it is possible to be diffused into hydrogen in gate electrode GE during the first depositing operation
Or reduce hydrogen and be diffused into gate electrode GE, hereafter, lower overlay pattern 110 can be used to form the of upper overlay pattern 120
Inhibit during two depositing operations or hydrogen is prevented to be diffused into gate electrode GE.Therefore, the threshold value electricity of gate electrode GE can be easy to control
Pressure.
In addition, upper overlay pattern 120 can be shown than lower covering when executing etch process to form contact hole 140H
The big etch-resistance of the etch-resistance of pattern 110.Upper overlay pattern 120 can be formed as covering the most top of lower overlay pattern 110
Therefore surface 110U during the etch process for being used to form contact hole 140H, can make overlay pattern CAP minimization of loss,
Or prevent overlay pattern CAP from losing.Therefore, it can be kept more than technique during the etch process for being used to form contact hole 140H
Amount.
Therefore, not only process allowance can be safely obtained in manufacture semiconductor device, but also semiconductor device can be with
Improvement with electrical characteristics.
Foregoing description provides the exemplary embodiment for explaining inventive concept.Therefore, inventive concept is not limited to above-mentioned
Embodiment, and those skilled in the art will appreciate that, in the feelings for the spirit and essential characteristics for not departing from inventive concept
Under condition, variation in form and details can be wherein being carried out.
Claims (25)
1. a kind of semiconductor device, the semiconductor device include:
Gate electrode is located in substrate；
Upper overlay pattern is located on gate electrode；And
Lower overlay pattern, between gate electrode and upper overlay pattern,
Wherein, lower overlay pattern includes:
First part, between gate electrode and upper overlay pattern；And
Multiple second parts, from the corresponding side surface that first part extends to upper overlay pattern,
Wherein, most top surface in each of upper overlay pattern covering second part.
2. semiconductor device according to claim 1, wherein at least part of upper overlay pattern fills lower overlay pattern
Second part between space.
3. semiconductor device according to claim 2, wherein most push up table in each of the second part of lower overlay pattern
Face is located at the height lower than the height of the top surface of upper overlay pattern relative to substrate in the vertical direction.
4. semiconductor device according to claim 3, the semiconductor device further include:
Interlayer dielectric layer is located in substrate simultaneously covering grid electrode, lower overlay pattern and upper overlay pattern,
Wherein, the top surface of upper overlay pattern and the top surface of interlayer dielectric layer are coplanar, and
Wherein, most top surface in each of the second part of lower overlay pattern is located at relative to substrate than layer in the vertical direction
Between dielectric layer top surface the low height of height at.
5. semiconductor device according to claim 1, wherein the upper overlay pattern includes:
Main body has the first width；And
Protrusion has second width smaller than the first width, and protrusion extends from main body towards substrate,
Wherein, protrusion is placed between the second part of lower overlay pattern, and
Wherein, most top surface in each of main body covering second part.
6. semiconductor device according to claim 5, the semiconductor device further include:
Multiple contacts are electrically connected to substrate on the opposite side of gate electrode,
Wherein, gate electrode, lower overlay pattern and upper overlay pattern constitute gate structure,
Wherein, gate structure includes:
Firstth area, opposite side are provided with contact；And
Secondth area, opposite side are set as not having contact, and
Wherein, the main body of upper overlay pattern contacts at the firstth area of gate structure with contact.
7. semiconductor device according to claim 6, the semiconductor device further include:
Multiple gate spacers, on the corresponding side surface of gate electrode,
Wherein, at the secondth area of gate structure, each of the second part of lower overlay pattern is placed in the prominent of overlay pattern
It rises between the corresponding gate spacer in gate spacer, and
Wherein, the main body of upper overlay pattern is contacted with gate spacer.
8. semiconductor device according to claim 6, the semiconductor device further include:
Multiple gate spacers, on the corresponding side surface of gate electrode；And
Interlayer dielectric layer, is located in substrate and covering grid electrode, lower overlay pattern, upper overlay pattern, multiple contacts and multiple
Gate spacer,
Wherein, upper overlay pattern is spaced apart across lower overlay pattern with gate spacer, and
Wherein, the main body of each of second part of lower overlay pattern and upper overlay pattern at the secondth area of gate structure with
Interlayer dielectric layer contact.
9. semiconductor device according to claim 8, wherein most top surface in each of gate spacer and lower covering
Pattern contacts.
10. semiconductor device according to claim 1, wherein gate electrode is first gate electrode,
Wherein, upper overlay pattern and lower overlay pattern constitute multilayer overlay pattern in first gate electrode,
Wherein, semiconductor device further include:
Second gate electrode is located in substrate；And
Additional overlay pattern, is located on the second gate electrode,
Wherein, adding overlay pattern has the structure different from the structure of multilayer overlay pattern, and
Wherein, the first channel length of the first channel region being stacked with first gate electrode in the horizontal direction is less than and second gate electricity
Extremely the second channel length of the second stacked channel region in the horizontal direction.
11. a kind of semiconductor device, the semiconductor device include:
Gate electrode is located in substrate；
Upper overlay pattern is located on gate electrode；
Lower overlay pattern, between gate electrode and upper overlay pattern；And
Interlayer dielectric layer is located in substrate simultaneously covering grid electrode, upper overlay pattern and lower overlay pattern,
Wherein, the top surface of upper overlay pattern is located at relative to the top surface of substrate and interlayer dielectric layer same in the vertical direction
At height, and
Wherein, the most top surface of lower overlay pattern is located at the top surface than interlayer dielectric layer relative to substrate in the vertical direction
At highly low height.
12. semiconductor device according to claim 11, wherein the most top surface of upper overlay pattern and lower overlay pattern connects
Touching.
13. semiconductor device according to claim 11, wherein lower overlay pattern includes:
First part, between gate electrode and upper overlay pattern；And
Multiple second parts, from the corresponding side surface that first part extends to upper overlay pattern,
Wherein, the most top surface of lower overlay pattern is most top surface in each of the second part of lower overlay pattern.
14. semiconductor device according to claim 13, wherein above overlay pattern includes:
Main body has the first width in the horizontal direction；And
Protrusion has second width smaller than the first width in the horizontal direction, and protrusion is in the vertical direction from main body towards base
Bottom extends,
Wherein, protrusion is placed between the second part of lower overlay pattern, and
Wherein, most top surface in each of main body covering second part.
15. semiconductor device according to claim 14, wherein most pushed up in each of the second part of lower overlay pattern
Surface is located at the height lower than the height of the top surface of the main body of upper overlay pattern relative to substrate in the vertical direction.
16. semiconductor device according to claim 14, the semiconductor device further include:
Multiple gate spacers, on the corresponding side surface of gate electrode；
Wherein, each of the second part of lower overlay pattern be placed in the protrusion of overlay pattern with it is corresponding in gate spacer
Gate spacer between, and
Wherein, the main body of upper overlay pattern is contacted with gate spacer.
17. semiconductor device according to claim 14, the semiconductor device further include:
Multiple gate spacers, on the corresponding side surface of gate electrode,
Wherein, upper overlay pattern is spaced apart across lower overlay pattern with gate spacer,
Wherein, the second part of lower overlay pattern separates the protrusion of upper overlay pattern and interlayer dielectric layer, and
Wherein, the main body of upper overlay pattern is contacted with interlayer dielectric layer.
18. semiconductor device according to claim 11, the semiconductor device further include:
Gate dielectric pattern, between substrate and gate electrode,
Wherein, gate dielectric pattern is extended in vertical direction on the side surface of gate electrode and is contacted with lower overlay pattern.
19. semiconductor device according to claim 11, wherein gate electrode is first gate electrode,
Wherein, upper overlay pattern and lower overlay pattern constitute multilayer overlay pattern in first gate electrode,
Wherein, semiconductor device further include:
Second gate electrode is located in substrate；And
Additional overlay pattern, is located on the second gate electrode,
Wherein, additional overlay pattern includes single layer structure, and the single layer structure includes material identical with the material of upper overlay pattern
Material, and
Wherein, the first channel length of the first channel region being stacked with first gate electrode in the horizontal direction is less than and second gate electricity
Extremely the second channel length of the second stacked channel region in the horizontal direction.
20. semiconductor device according to claim 11, described device further include:
Multiple contacts penetrate interlayer dielectric layer and are electrically connected to substrate on the opposite side of gate electrode,
Wherein, gate electrode, lower overlay pattern and upper overlay pattern constitute gate structure,
Wherein, gate structure includes the firstth area and the secondth area, and the opposite side in the firstth area is provided with contact, the opposite side in the secondth area
It is set as not having contact, and
Wherein, upper overlay pattern contacts at the firstth area of gate structure with contact.
21. semiconductor device according to claim 11, wherein wrap on the boundary between upper overlay pattern and lower overlay pattern
Include oxide.
22. a kind of method for manufacturing semiconductor device, which comprises
The interlayer dielectric layer for sacrificing gate pattern and covering sacrifice gate pattern is formed on the substrate；
Removal sacrifices gate pattern to form gap in interlayer dielectric layer；
Gate electrode is formed in gap；
The lower caldding layer of the inner surface of coverage gap and the top surface of gate electrode is formed on interlayer dielectric layer；
The mask pattern of a part of covering lower caldding layer is formed in gap；
The other parts of lower caldding layer are removed with overlay pattern under the formation in gap, wherein other portions of lower caldding layer
Divide and is not masked pattern covering；And
Form the upper overlay pattern of the remainder in filling gap.
23. according to the method for claim 22, wherein the step of forming lower caldding layer includes executing the first depositing operation,
Wherein, the first depositing operation includes indirect H2Corona treatment does not include H2Corona treatment.
24. according to the method for claim 23, wherein include: the step of overlay pattern in formation
The upper caldding layer of the remainder in filling gap is formed on interlayer dielectric layer；And
Make top surface of the upper caldding layer planarization until exposing interlayer dielectric layer,
Wherein, the step of forming upper caldding layer includes executing the second depositing operation, and the second depositing operation includes direct H2Plasma
Processing.
25. according to the method for claim 22, wherein the step of forming lower caldding layer includes executing the first depositing operation,
It wherein, include the second depositing operation of execution the step of overlay pattern in formation to form upper caldding layer, and
Wherein, in the H than executing the atmosphere under the second depositing operation2The small H of plasma density2Under plasma density atmosphere
Execute the first depositing operation.
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| US11749753B2 (en) * | 2020-06-15 | 2023-09-05 | Taiwan Semiconductor Manufacturing Company Limited | Methods of forming a semiconductor device with a gate structure having a dielectric protection layer |
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| US20190165114A1 (en) | 2019-05-30 |
| KR20190063097A (en) | 2019-06-07 |
| US20210005729A1 (en) | 2021-01-07 |
| US11557656B2 (en) | 2023-01-17 |
| KR102432866B1 (en) | 2022-08-17 |
| US10811505B2 (en) | 2020-10-20 |
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