JP2010153523A - Manufacturing method of semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device which is formed via a step for polishing the surface of an interlayer insulating film. <P>SOLUTION: On a main surface s1 of a silicon substrate 1, a high-breakdown strength gate G1 consisting of a high-breakdown strength gate insulating film IG1 and a high-breakdown strength gate electrode EG1 is formed, and then, a salicide block film SAB and an interlayer insulating film IL are formed sequentially. The interlayer insulating film IL is polished by CMP. The salicide block film SAB is formed of, in the order starting from the lower layer, a protective oxide film t1 which is an insulating film whose body is silicon oxide and a protective nitride film t2, which is an insulating film whose body is silicon nitride. The interlayer insulating film IL is polished as deep as reaching the salicide block film SAB at the upper surface of the high-breakdown strength gate G1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique and a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device formed through a surface polishing process of an interlayer insulating film.

  For a semiconductor device, an integrated circuit in which elements having various characteristics formed on a semiconductor substrate are electrically connected by wiring is used. Examples of the integrated circuit include a control logic circuit, a drive circuit, and an information storage memory circuit. These are designed such that the types of semiconductor elements to be configured and the wiring method are configured so that a desired function can be exhibited.

  As a semiconductor element constituting an integrated circuit, for example, there is a field effect transistor (FET). A field effect transistor mainly has a MIS (Metal Insulator Semiconductor) structure in which a gate electrode is formed on a semiconductor substrate via an insulating film. Note that when a silicon oxide film or the like is used as the insulating film, it is called a MOS (Metal Oxide Semiconductor) structure. Such MIS field effect transistors (hereinafter simply referred to as MIS transistors) are covered with an interlayer insulating film on a semiconductor substrate and insulated from each other. A contact plug is formed so as to penetrate the interlayer insulating film, and is electrically connected to each terminal of the semiconductor element. On the interlayer insulating film, a metal wiring that electrically connects desired contact plugs is formed.

For example, in Japanese Patent Laid-Open No. 2003-243619 (Patent Document 1), the formation density of the gate electrode and the dummy gate layer of the MOS transistor in the logic circuit region on the semiconductor substrate is close to the formation density of the gate layer in the memory region. A technique for reducing the difference in the polishing speed of the insulating layer in both regions by CMP (Chemical and Mechanical Polishing) method is disclosed. Thereby, an insulating layer can be planarized more accurately.
JP 2003-243619 A

  Along with higher performance due to higher integration of integrated circuits, the wiring structure composed of the interlayer insulating film, contact plug (via plug) and metal wiring as described above becomes finer and more complicated. In particular, as a recent technical trend, interlayer insulating films have been multilayered in order to allow fine and complicated wiring patterns. In such multilayer wiring technology, it is important to improve the flatness of the lower layer. This is because the variation in the thickness of the lower interlayer insulating film becomes larger and affects the variation in the thickness of the upper interlayer insulating film. When the film thickness of the interlayer insulating film fluctuates as described above, when the contact hole is opened, an opening defect such that the thick part of the interlayer insulating film is not normally opened occurs. This results in a decrease in yield in the semiconductor device manufacturing process.

  In the manufacturing method studied by the present inventors, the interlayer insulating film deposited on the semiconductor substrate is subjected to surface polishing by the CMP method, thereby planarizing the interlayer insulating film. In this production method, the following problems have been found by further study by the present inventors.

  As a semiconductor device studied by the present inventors, for example, there is an LCD driver which is a semiconductor device for driving for displaying a liquid crystal display (LCD). The LCD driver has an integrated circuit with various functions such as an operation control circuit, a main memory circuit, a nonvolatile memory circuit, and a power supply control circuit, and these are mounted on one chip. Accordingly, the MIS transistor has various characteristics. In particular, there are a high-speed specification MIS transistor, a high breakdown voltage specification MIS transistor, a MIS transistor which is a component of a nonvolatile memory, and the like.

  The MIS transistors of the above specifications have different gate insulating film thicknesses, for example. Qualitatively, an MIS transistor having a thinner gate insulating film can operate at a higher speed, and an MIS transistor having a thicker gate insulating film can operate at a higher voltage. The LCD driver examined by the present inventors uses MIS transistors having different gate insulating film thicknesses in the range of 3 to 100 nm depending on required characteristics. Therefore, the LCD driver studied by the present inventors has a structure including gates having different heights on a semiconductor substrate.

  When the interlayer insulating film covering the plurality of MIS transistors composed of gates having different heights is polished by the CMP method, the following problems have been found by the inventors' investigation. That is, a problem has been found that a gate with a high altitude is shaved due to variations in the polishing rate. The etching of the gate causes deterioration of characteristics such as defective breakdown voltage, and causes a decrease in reliability.

  Therefore, an object of the present invention is to provide a technique for improving the reliability of a semiconductor device formed through a step of polishing an interlayer insulating film.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  In the present application, a plurality of inventions are disclosed. An outline of one embodiment of the inventions will be briefly described as follows.

  A gate is formed by sequentially forming a gate insulating film and a gate electrode on the main surface in the first region of the semiconductor substrate, and then a protective insulating film and an interlayer insulating film are sequentially formed on the main surface of the semiconductor substrate. In a method of manufacturing a semiconductor device including a step of polishing an interlayer insulating film by CMP, as a protective insulating film, a protective oxide film made of an insulating film mainly made of silicon oxide and an insulating film made mainly of silicon nitride The interlayer insulating film is polished until it reaches the protective insulating film on the upper surface of the gate.

  Of the plurality of inventions disclosed in the present application, effects obtained by the above-described embodiment will be briefly described as follows.

  That is, the reliability of the semiconductor device formed through the step of polishing the surface of the interlayer insulating film can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The structure of the semiconductor device according to the first embodiment will be described with reference to the drawings. The semiconductor device according to the first embodiment includes at least three types of MIS transistors having different gate insulating film thicknesses on the same chip.

  FIG. 1 shows a plan view of a main part of a high voltage MIS transistor Qh, which is a MIS transistor having a high operating voltage, included in the semiconductor device of the first embodiment. (A) is a plan view omitting the configuration formed on the silicon substrate (semiconductor substrate) 1, and (b) is a plan view illustrating the configuration formed on the silicon substrate 1. The plan view is hatched for convenience, but has no structural meaning. FIG. 2 shows a plan view of the main part of the nonvolatile memory NVM included in the semiconductor device of the first embodiment.

  FIG. 3 shows a cross-sectional view of a main part of the semiconductor device according to the first embodiment. (A) shows a cross-sectional view of the main part of the high-breakdown-voltage MIS transistor Qh, on the left side is a cross-sectional view taken along the line AA in FIG. FIG. 3 shows a cross-sectional view taken along the line B-B in FIG. FIG. 4B shows a cross-sectional view of the memory unit MIS transistor Qnvm constituting the nonvolatile memory NVM as viewed in the direction of the arrow along the line CC in FIG. Further, (b) also shows a cross-sectional view of the main part of the medium voltage MIS transistor Qm and the high speed MIS transistor Qw. The structure of the semiconductor device according to the first embodiment will be described with reference to FIGS. Note that although all the transistors described below are described as n-type conductivity, they may be p-type conductivity. In that case, the polarity of the semiconductor region such as the well is reversed.

  The operating voltage or withstand voltage of the high withstand voltage MIS transistor Qh is higher than that of the memory MIS transistor Qnvm, the medium withstand voltage MIS transistor Qm, and the high speed MIS transistor Qw. For example, the high breakdown voltage MIS transistor Qh has a breakdown voltage of about 20V. The operating voltage or withstand voltage of the memory MIS transistor Qnvm is approximately the same as that of the medium withstand voltage MIS transistor Qm and is higher than that of the high-speed MIS transistor Qw. For example, the withstand voltage of the memory MIS transistor Qnvm and the medium withstand voltage MIS transistor Qm is about 6V. The breakdown voltage of the high speed MIS transistor Qw is about 1.5V. The operating speed of the high-speed MIS transistor Qw is faster than that of the memory MIS transistor Qnvm, the medium withstand voltage MIS transistor Qm, and the high withstand voltage MIS transistor Qh. The operating speed of the memory MIS transistor Qnvm is approximately the same as that of the medium withstand voltage MIS transistor Qm and is faster than that of the high withstand voltage MIS transistor Qh.

  In the silicon substrate 1, the high voltage MIS transistor Qh is formed in the high voltage MIS region Rh, the nonvolatile memory NVM including the memory unit MIS transistor Qnvm is formed in the memory region Rnvm, and the medium voltage MIS transistor Qm is in the medium voltage MIS region Rm. The high speed MIS transistor Qw is formed in the high speed MIS region Rw. The silicon substrate 1 has a main circuit region (first region) where an integrated circuit is arranged and a peripheral region (second region) other than that. The regions Rh, Rnvm, Rm, and Rw in which the MIS transistors Qh, Qnvm, Qm, and Qw are disposed are all included in the main circuit region (first region) of the silicon substrate 1.

  The high breakdown voltage MIS transistor Qh in the first embodiment has the following components formed in the high breakdown voltage MIS region Rh. On the main surface s 1 of the silicon substrate 1, a shallow trench type isolation portion 2 is formed to define an active region 3. In the isolation part 2, an opening 4 for defining a source / drain region sd1, which will be described in detail later, is formed. Further, on the main surface s1 side of the silicon substrate 1, a p-well pw1, which is a p-type conductivity type semiconductor region, is formed so as to include the active region 3. Further, a source / drain region sd1 which is an n-type conductivity type semiconductor region is formed so as to be enclosed in the p well pw1 on the main surface s1 side of the silicon substrate 1. The source / drain region sd1 is formed in a region that reaches the end of the active region 3 from the opening 4 of the isolation portion 2 when viewed in plan. In the source / drain region sd1, a high-concentration n-type region 5 is formed in a portion defined by the opening 4.

  A high breakdown voltage gate (first gate) G1 is formed so as to cover the active region 3. The high breakdown voltage gate G1 includes a high breakdown voltage gate electrode (gate electrode) EG1 formed with a high breakdown voltage gate insulating film (first gate insulating film) IG1 therebetween. The high breakdown voltage gate insulating film IG1 is an insulating film mainly composed of silicon oxide of about 60 to 100 nm. The high breakdown voltage gate electrode EG1 is a conductor film mainly composed of polycrystalline silicon. A sidewall spacer 6 made of a silicon oxide film or a laminated insulating film of a silicon oxide film and a silicon nitride film is formed on the sidewall of the high breakdown voltage gate electrode EG1.

  A salicide block film (protective insulating film) SAB is formed so as to cover part of the high breakdown voltage gate G1. In other words, the upper surface of the high breakdown voltage gate electrode EG1 has a portion covered with the salicide block film SAB and a portion not covered. The salicide block film SAB is a laminated insulating film of a protective oxide film t1 that is an insulating film mainly composed of silicon oxide and a protective nitride film t2 that is an insulating film mainly composed of silicon nitride in order from the lower layer. The thicknesses of the protective oxide film t1 are about 50 nm and the protective nitride film t2 is about 10 nm, for example.

  A metal silicide layer sc is formed in a portion of the silicon substrate 1 that is not covered with the salicide block film SAB in a region made of silicon. That is, the upper surface of the high breakdown voltage gate electrode EG1 that is not covered with the salicide block film SAB and the surface of the source / drain region sd1 (high concentration n-type region 5) located in the opening 4 of the isolation portion 2 A silicide layer sc is formed. The metal silicide layer sc is a compound of a metal such as nickel or cobalt and silicon, and is a layer having high conductivity.

  The above is the configuration of the high breakdown voltage MIS transistor Qh according to the first embodiment.

  The memory unit MIS transistor Qnvm of the first embodiment has the following components formed in the memory region Rnvm. The memory unit MIS transistor Qnvm is formed in the active region 3 defined by the isolation unit 2 described above. A p well pw2 is formed on the main surface s1 side of the silicon substrate 1 so as to include the active region 3.

  On the main surface s1 of the silicon substrate 1, a memory gate (second gate) G2 is formed. The memory gate G2 includes a memory gate electrode (gate electrode) EG2 formed with a memory gate insulating film (second gate insulating film) IG2 therebetween. The memory gate insulating film IG2 is an insulating film mainly composed of silicon oxide of about 10 nm. The memory gate electrode EG2 is a conductor film mainly composed of polycrystalline silicon. Further, the height of the memory gate G2 viewed from the main surface s1 of the silicon substrate 1 is lower than the height of the high breakdown voltage gate G1 described above. This is because the memory gate insulating film IG2 is thinner than the high breakdown voltage gate insulating film IG1. Further, the side wall of the memory gate electrode EG2 is covered with the above-described sidewall spacer 6.

  In the active region 3, an extension region ex <b> 1, which is an n-type semiconductor region, is formed in a region located in the p-well pw <b> 2 below the side of the memory gate G <b> 2. In a region located in the p well pw2, a source / drain region sd2 which is an n-type conductivity type semiconductor region is formed. The extension region ex1 and the source / drain region sd2 are electrically connected, and the former has a lower impurity concentration and is shallower than the latter.

  The salicide block film SAB is formed so as to cover the memory gate G2. The salicide block film SAB is formed so as to cover the memory gate G2 and not to cover part of the source / drain region sd2 at the lower side. The aforementioned metal silicide layer sc is formed on the surface of the portion of the source / drain region sd2 that is not covered with the salicide block film SAB. The reason why the memory MIS transistor Qnvm of the first embodiment has the salicide block film SAB as described above will be described in detail later.

  The above is the configuration of the memory MIS transistor Qnvm of the first embodiment. The operation method of the nonvolatile memory NVM including the memory MIS transistor Qnvm will be described in detail later.

  The medium withstand voltage MIS transistor Qm in the first embodiment has the following components formed in the medium withstand voltage MIS region Rm. The medium withstand voltage MIS transistor Qm is formed in the active region 3 defined by the isolation portion 2 described above. A p well pw3 is formed on the main surface s1 side of the silicon substrate 1 so as to include the active region 3.

  On the main surface s1 of the silicon substrate 1, a medium withstand voltage gate (second gate) G3 is formed. The medium withstand voltage gate G3 is composed of a medium withstand voltage gate electrode (gate electrode) EG3 formed with a medium withstand voltage gate insulating film (second gate insulating film) IG3 therebetween. The medium voltage gate insulating film IG3 is an insulating film mainly composed of silicon oxide of about 10 nm. The medium voltage gate electrode EG3 is a conductor film mainly composed of polycrystalline silicon. The side wall of the medium voltage gate electrode EG3 is covered with the above-described side wall spacer 6.

  In the active region 3, an extension region ex2 which is an n-type conductivity type semiconductor region is formed in a region located in the p well pw3 at the lower side of the medium breakdown voltage gate G3. In a region located in the p well pw3, a source / drain region sd3 which is an n-type conductivity type semiconductor region is formed. The extension region ex2 and the source / drain region sd3 are electrically connected, and the former has a lower impurity concentration and is shallower than the latter.

  The above-described metal silicide layer sc is formed on the upper surface of the medium breakdown voltage gate electrode EG3 and the upper surface of the source / drain region sd3.

  The above is the configuration of the medium withstand voltage MIS transistor Qm in the first embodiment.

  The high speed MIS transistor Qw according to the first embodiment has the following components formed in the high speed MIS region Rw. The high-speed MIS transistor Qw is formed in the active region 3 defined by the isolation portion 2 described above. A p well pw4 is formed on the main surface s1 side of the silicon substrate 1 so as to include the active region 3.

  On the main surface s1 of the silicon substrate 1, a high-speed gate (second gate) G4 is formed. The high speed gate G4 is composed of a high speed gate electrode (gate electrode) EG4 formed with a high speed gate insulating film (second gate insulating film) IG4 interposed therebetween. The high-speed gate insulating film IG4 is an insulating film mainly composed of silicon oxide of about 3 nm. The high speed gate electrode EG4 is a conductor film mainly composed of polycrystalline silicon. The side wall of the high-speed gate electrode EG4 is covered with the above-described sidewall spacer 6.

  In the active region 3, an extension region ex3 that is an n-type semiconductor region is formed in a region located in the p-well pw 4 at the lower side of the high-speed gate G 4, and the p at the lower side of the sidewall spacer 6 is formed. In the region located in the well pw4, a source / drain region sd4 which is an n-type conductivity type semiconductor region is formed. The extension region ex3 and the source / drain region sd4 are electrically connected, and the former has a lower impurity concentration and is shallower than the latter.

  The above-described metal silicide layer sc is formed on the upper surface of the high-speed gate electrode EG4 and the upper surface of the source / drain region sd4.

  The above is the configuration of the high-speed MIS transistor Qw of the first embodiment.

  Further, an etching stop film (nitride film for processing connection holes) SAC made of an insulating film mainly composed of silicon nitride is formed on the silicon substrate 1 so as to cover the above configuration. On top of that, an interlayer insulating film IL made of an insulating film mainly composed of silicon oxide is formed so as to embed the above configuration. In other words, the etching stop film SAC is formed as a layer below the interlayer insulating film IL. Here, the interlayer insulating film IL of the first embodiment has a two-layer structure made of the same silicon oxide film. The usefulness of the two layers is demonstrated by the manufacturing method of the first embodiment. Here, for convenience, the first interlayer insulating film ILa and the second interlayer insulating film ILb are shown.

  A conductive contact plug cp is formed so as to penetrate the interlayer insulating film IL. The contact plug cp reaches the surface of the source / drain region sd1 where the metal silicide layer sc is formed (the main surface s1 of the silicon substrate 1) or each gate G1, G3, G4 where the metal silicide layer sc is formed. Is formed. The contact plug cp may be made of a conductive film mainly composed of tungsten, and may have a titanium / titanium nitride laminated film as a barrier metal at the interface with the interlayer insulating film IL.

  A metal wiring mw is formed on the upper surface of the interlayer insulating film IL. The metal wiring mw is formed so as to be electrically connected to the contact plug cp, and each terminal is connected so as to have a desired circuit configuration. The metal wiring mw is made of a conductor film mainly composed of aluminum, and may have a titanium / titanium nitride laminated film as a barrier metal on the upper and lower surfaces thereof.

  Next, an operation method of the nonvolatile memory NVM having the memory MIS transistor Qnvm will be described. The configuration and operation method of the nonvolatile memory NVM shown in FIG. 2 and FIG. 3B are described in, for example, Japanese Patent Application No. 2007-174683 previously filed by the present applicants. The operation method is the same as that described in paragraph numbers [0050] to [0056] of the application specification, that is, as described below.

  At the time of data writing, a positive control voltage of about 9 V, for example, is applied to the control gate wiring to which the other electrode of the capacitor CA of the nonvolatile memory NVM is connected in the cell to be written (selected cell). For example, a voltage of 0 V is applied to the control gate wiring connected to the non-selected cell. Further, a negative voltage of about −9 V, for example, is applied to the data write / erase bit line to which one electrode of the data write / erase capacitor CWE of the nonvolatile memory NVM of the selected cell is electrically connected. Apply. For example, a voltage of 0 V is applied to the bit line for data writing / erasing connected to the non-selected cell. Further, a voltage of, for example, 0 V is applied to the selection line (gate of the selection transistor QS), the source line (source of the read transistor QR), and the bit line for data writing (source of the selection transistor QS). Thus, data is written by injecting electrons into the floating gate electrode FG of the data writing / erasing capacitor CWE of the selected nonvolatile memory NVM by the FN tunnel current of the entire channel surface.

  At the time of batch erasing of data, a negative control voltage of about −9 V, for example, is applied to the control gate wiring to which the other electrode of the capacitor CA is connected across the non-volatile memory NVM of a plurality of cells. Further, a negative voltage of about 9 V, for example, is applied to the data write / erase bit line to which one electrode of the data write / erase capacitor CWE of the selected cell is electrically connected. Further, for example, 0 V is applied to the selection line, the source line, and the data writing bit line. As a result, electrons accumulated in the floating gate electrode FG of the data writing / erasing capacitor CWE of the plurality of nonvolatile memories NVM that perform data batch erasure are emitted by the FN tunnel current across the entire channel surface, and the plurality of cells are nonvolatile. The data in the memory NVM is erased at once.

  Here, extracting electrons from the floating gate electrode FG is defined as data erasing, but conversely, injecting electrons into the floating gate electrode FG can be defined as data erasing.

  At the time of data bit unit erasing, a negative control voltage of about −9 V, for example, is applied to the control gate line to which the other electrode of the capacitor CA of the nonvolatile memory NVM of the selected cell is connected. For example, a voltage of 0 V is applied to the control gate wiring of the non-selected cell. Further, a positive voltage of, for example, about 9 V is applied to the data write / erase bit line to which one electrode of the data write / erase capacitor CWE of the nonvolatile memory NVM of the selected cell is electrically connected. To do. For example, a voltage of 0 V is applied to the bit line for writing / erasing data in the non-selected cells. Further, for example, 0 V is applied to the selection line, the source line, and the data writing bit line. As a result, electrons accumulated in the floating gate electrode FG of the data write / erase capacitor CWE of the nonvolatile memory NVM of the selected cell to be erased are released by the FN tunnel current of the entire channel surface, and the nonvolatile of the selected cell Data in the volatile memory NVM is erased.

  At the time of data reading, a control voltage of 3 V, for example, is applied to the control gate wiring to which the other electrode of the capacitor CA of the nonvolatile memory NVM of the selected cell is connected. For example, a voltage of 0 V is applied to the control gate wiring of the non-selected cell. Further, a voltage of, for example, about 0 V is applied to the data write / erase bit line to which one electrode of the data write / erase capacitor CWE of the nonvolatile memory NVM of the selected cell is electrically connected. In addition, a voltage of about 3 V, for example, is applied to the selection line to which the gate electrode of the selection transistor QS of the nonvolatile memory NVM of the selected cell is electrically connected. Then, a voltage of about 1 V, for example, is applied to the bit line for data writing. Further, for example, 0 V is applied to the source line. As a result, the read transistor QR of the nonvolatile memory NVM that is a data read target is turned on, and the data stored in the selected cell is 0/1 depending on whether or not the drain current flows through the channel of the read transistor QR. Read out what.

  The above is the operation method of the nonvolatile memory NVM according to the first embodiment. The above-described data write / erase capacitor CWE has a MIS transistor structure, which is shown as a memory transistor Qnvm in the cross-sectional view of FIG.

  In the memory transistor Qnvm of the first embodiment, as described above, the salicide block film SAB is formed so as to cover the memory gate G1. This is used as a block film when the metal silicide layer sc is formed in a self-aligned manner (salicide formation), as will be described in detail later. For this purpose, it is sufficient to form the protective oxide film t1. On the other hand, in the first embodiment, it is more preferable that the protective nitride film t2 is formed on the protective oxide film t1, and the laminated film is the salicide block film SAB. The reason is the same as the description of the silicon nitride film 4a described in paragraphs [0032] to [0034] of the specification of the above Japanese Patent Application No. 2007-174683. That is, by forming the protective nitride film t2 as the salicide block film SAB, it is possible to suppress or prevent water, hydrogen ions, and the like from diffusing into the floating gate electrode FG.

  The above is the configuration of the semiconductor device of the first embodiment. The effects of each component will be described in detail in the manufacturing process shown below. A method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. The region on the silicon substrate 1 shown in each figure corresponds to the region shown in FIG.

  First, as shown in FIG. 4, an isolation portion 2 having an STI (Shallow Trench Isolation) structure is formed on the main surface s <b> 1 of the silicon substrate 1. The isolation region 2 defines the active region 3 described with reference to FIGS. Here, first, grooves are formed by performing anisotropic etching on the silicon substrate 1 using a photoresist film (not shown) patterned by a photolithography method as an etching mask. Subsequently, a silicon oxide film is formed on the main surface s1 of the silicon substrate 1 including the groove. Thereafter, the silicon oxide film is subjected to surface polishing so as to be embedded in the groove, thereby forming an isolation portion 2 having an STI structure.

  Subsequently, semiconductor regions of each conductivity type are formed on the main surface s1 side of the silicon substrate 1. In this step, p wells pw1, pw2, pw3, and pw4 in each region Rh, Rnvm, Rm, and Rs and a source / drain region sd1 in the high breakdown voltage MIS region Rh are formed. Here, first, impurity ions are introduced into the silicon substrate 1 by performing desired ion implantation in each region using a photoresist film (not shown) patterned by photolithography as an ion implantation mask. Thereafter, heat treatment is appropriately performed to activate or diffuse impurity ions, thereby forming each semiconductor region. In the above process, as long as the ion implantation conditions and the heat treatment conditions are the same, the processes may be shared. Thereby, the number of processes can be reduced. In addition, an ion implantation step for adjusting the impurity concentration of the channel region may be performed in this step.

  Next, as illustrated in FIG. 5, a gate insulating film IG that is an insulating film mainly composed of silicon oxide is formed on the main surface s <b> 1 of the silicon substrate 1. The gate insulating film IG is formed by a thermal oxidation method, a chemical vapor deposition (CVD) method, or the like. Further, the gate insulating film IG is formed so as to have a different thickness depending on each region. More specifically, the gate insulating film IG is formed in the memory region Rnvm and the medium withstand voltage MIS region Rm so as to have the same film thickness and thicker than the high-speed MIS region Rw. Further, the gate insulating film IG is formed in the high breakdown voltage MIS region Rh so as to be thicker than the memory region Rnvm and the medium breakdown voltage MIS region Rm. For example, a gate insulating film IG of about 60 to 100 nm is formed in the high withstand voltage MIS region Rh, about 10 nm is formed in the memory region Rnvm and medium withstand voltage MIS region Rm, and about 3 nm is formed in the high speed MIS region Rw.

  For this, first, a gate insulating film IG is formed on the silicon substrate 1 by a thermal oxidation method or a CVD method. Thereafter, the gate insulating film IG in the high breakdown voltage MIS region Rh is processed by photolithography or etching. Thereafter, the gate insulating film IG in the memory region Rnvm, the medium withstand voltage MIS region Rm, and the high-speed MIS region Rw is removed by photolithography or etching. Next, a gate insulating film IG is formed in the memory region Rnvm, the medium withstand voltage MIS region Rm, and the high-speed MIS region Rw on the silicon substrate 1 by using a thermal oxidation method. At this time, the silicon substrate 1 under the gate insulating film IG in the high breakdown voltage MIS region Rh is also oxidized. Thereafter, the gate insulating film IG in the high-speed MIS region Rw is removed by photolithography or etching. Next, the gate insulating film IG is formed in the high-speed MIS region Rw by using a thermal oxidation method. At this time, the silicon substrate 1 under the gate insulating film IG in the high breakdown voltage MIS region Rh, the memory region Rnvm, and the medium breakdown voltage MIS region Rm is also oxidized.

  In this way, as the gate insulating film IG in the high breakdown voltage MIS region Rh, the silicon oxide film when the gate insulating film IG is formed in the region, the gate insulating film IG in the memory region Rnvm, and the medium breakdown voltage MIS region Rm are formed. The silicon oxide film when formed and the silicon oxide film formed when the gate insulating film IG is formed in the high-speed MIS region Rw are laminated. The gate insulating film IG of the memory region Rnvm or the medium withstand voltage MIS region Rm includes a silicon oxide film when the gate insulating film IG is formed in the region and a gate insulating film IG when the gate insulating film IG is formed in the high-speed MIS region Rw. A silicon oxide film is stacked. In the high-speed MIS region Rw, a silicon oxide film formed when the gate insulating film IG is formed in the region is formed.

  Next, as shown in FIG. 6, a gate conductor film EG that is a conductor film mainly composed of polycrystalline silicon is formed on the main surface s <b> 1 of the silicon substrate 1. For this, a polycrystalline silicon film is formed by a CVD method or the like. Of the gate insulating film IG formed or processed up to the previous step, the gate insulating film IG in the high breakdown voltage MIS region Rh is referred to as a high breakdown voltage gate insulating film IG1.

  Subsequently, the gate conductor film EG or the underlying gate insulating film IG is processed in each region by photolithography or etching.

  In the high breakdown voltage MIS region Rh, the gate conductor film EG is processed so as to cover at least the active region 3 and to be disposed on the high breakdown voltage gate insulating film IG1, thereby forming the high breakdown voltage gate electrode EG1. In this manner, the high breakdown voltage gate G1 including the high breakdown voltage gate insulating film IG1 and the high breakdown voltage gate electrode EG1 is formed.

  Further, in the memory region Rnvm, the gate conductor film EG and the gate insulating film IG are processed so as to be disposed at a position overlapping with a part of the active region 3 in a plan view, whereby the memory gate electrode EG2 and the memory gate electrode EG2, respectively. A gate insulating film IG2 is formed. In this manner, the memory gate G2 including the memory gate insulating film IG2 and the memory gate electrode EG2 is formed.

  Further, in the medium withstand voltage MIS region Rm, by processing the gate conductor film EG and the gate insulating film IG so as to be disposed in a position overlapping with a part of the active region 3, the medium withstand voltage gate electrode EG3 and An intermediate voltage gate insulating film IG3 is formed. In this manner, the medium withstand voltage gate G3 including the medium withstand voltage gate insulating film IG3 and the medium withstand voltage gate electrode EG3 is formed.

  Further, in the high-speed MIS region Rw, the gate conductor film EG and the gate insulating film IG are processed so as to be disposed in a position overlapping with a part of the active region 3 in a plan view, whereby the high-speed gate electrode EG4 and the high-speed gate, respectively An insulating film IG4 is formed. In this manner, the high speed gate G4 including the high speed gate insulating film IG4 and the high speed gate electrode EG4 is formed.

  The gates G <b> 1 to G <b> 4 formed through the above steps have different heights as viewed from the main surface s <b> 1 of the silicon substrate 1. This is because the gate electrodes EG1 to EG4 have the same film thickness, and the gate insulating films IG1 to IG4 have different film thicknesses. More specifically, the memory gate G2 and the medium withstand voltage gate G3 have the same height and are higher than the high speed gate G4, and the high withstand voltage gate G1 is higher than the memory gate G2 and the medium withstand voltage gate G3. .

  Next, as shown in FIG. 7, extension regions ex1, ex2, and ex3 are formed on the main surface s1 side of the silicon substrate 1 located at the lower side of the memory gate G2, the medium voltage gate G3, and the high-speed gate G4. Form. Here, the extension region ex1 is formed at the lower side of the memory gate G2, the extension region ex2 is formed at the lower side of the medium breakdown voltage gate G3, and the extension region ex3 is formed at the lower side of the high-speed gate G4. Form. These are formed by ion implantation using a photoresist film (not shown) formed by a photolithography method or the like and each gate electrode as an ion implantation mask.

  Thereafter, sidewall spacers 6 are formed so as to cover the sidewalls of the memory gate G2, the medium breakdown voltage gate G3, and the high-speed gate G4. For this, first, a silicon oxide film is deposited so as to cover the main surface s <b> 1 of the silicon substrate 1. Thereafter, anisotropic etching is performed on the entire surface in the direction toward the main surface s1 of the silicon substrate 1 (etch back). As a result, the side wall spacer 6 can be formed while leaving the portion of the silicon oxide film that covered the side wall of each gate that was the stepped portion.

  Subsequently, the main surface s1 of the silicon substrate 1 in the opening 4 of the isolation portion 2 in the high breakdown voltage MIS region Rh, and the sidewall spacers 6 in the memory region Rnvm, medium breakdown voltage MIS region Rm, and high speed MIS region Rw. High-concentration n-type region 5 and source / drain regions sd2, sd3, and sd4 are formed on main surface s1 of silicon substrate 1 located at the lower side. Here, a high concentration n-type region 5 is formed in the opening 4 of the high breakdown voltage MIS region Rh, a source / drain region sd2 is formed in the memory region Rnvm, and a source / drain region sd3 is formed in the medium breakdown voltage MIS region Rm. The source / drain region sd5 is formed in the high-speed MIS region Rw. These are formed by ion implantation using a photoresist film (not shown) formed by a photolithography method or the like, and each gate electrode and the sidewall spacer 6 as an ion implantation mask.

  Through the above steps, the high voltage MIS region Rh, the memory region Rnvm, the medium voltage MIS region Rm, and the high speed MIS region Rw are respectively converted into the high voltage MIS transistor Qh, the memory unit MIS transistor Qnvm, the medium voltage MIS transistor Qm, and Thus, the basic configuration of the high-speed MIS transistor Qw is formed.

  Next, as shown in FIG. 8, a salicide block film SAB is formed so as to cover the memory gate G2. For this, first, a protective oxide film t1 and a protective nitride film t2 are sequentially formed by a CVD method or the like so as to cover the main surface s1 of the silicon substrate 1. Thereafter, the salicide block film SAB is left so as to cover the memory gate G2 by photolithography and etching, and the other portions are removed. Here, in the manufacturing method of the first embodiment, the salicide block film SAB covering the high breakdown voltage gate G1 which is the highest gate among the gates is also left so as to cover at least a part thereof. The reason why the salicide block film is left so as to cover the memory gate G2 is as described above. The reason why the salicide block film SAB is left on the high breakdown voltage gate G1 in the manufacturing method of the first embodiment will be described later in detail.

  Next, as shown in FIG. 9, a metal silicide layer sc is formed on the upper surface of each gate and the main surface s <b> 1 of the silicon substrate 1 that is not covered with the salicide block film SAB. More specifically, each part of the gate not covered with the salicide block film SAB is a part of the high breakdown voltage gate G1 that is not covered with the salicide block film SAB, a medium breakdown voltage gate G3, and a high-speed gate G4. In addition, a metal silicide layer sc is formed on these upper surfaces. Further, the main surface s1 of the silicon substrate 1 which is not covered with the salicide block film SAB is the upper surface of the source / drain regions sd1, sd2, sd3, sd4 of the regions Rh, Rnvm, Rm, Rw. The metal silicide layer sc is formed at the location. Even if the salicide block film SAB is not covered, the metal silicide layer sc is not formed in a portion made of a material other than silicon, such as a portion made of a silicon oxide film such as the separation portion 2 and the sidewall spacer 6.

  The metal silicide layer sc is formed in a self-aligned manner. The process is as follows. First, a metal film such as a cobalt film is deposited by sputtering or the like so as to cover the main surface s1 of the silicon substrate 1. Thereafter, heat treatment is performed. At this time, alloying (metal silicidation) occurs at a portion where the metal film and silicon such as a gate or a substrate are in contact, and metal silicide is formed. Thereafter, the metal film that has not become the metal silicide is removed, thereby forming the metal silicide layer sc in the portion where the metal film and silicon are in contact. Such a method for forming the metal silicide layer sc is referred to as a salicide (Self Align Silicide) method. Then, the salicide block film SAB is formed on the portion where the metal silicide layer sc is not desired to be formed before the metal film is formed as in the process of FIG. This prevents the portion where the salicide block film SAB is formed from coming into contact with the metal film, thereby preventing the portion from being silicided. Even if the salicide block film SAB is not covered, a metal silicidation reaction does not occur in a portion made of a material other than silicon, such as a portion made of a silicon oxide film such as the separation portion 2 and the side wall spacer 6. The layer sc is not formed.

  Next, as shown in FIG. 10, the main surface s1 of the silicon substrate 1 is sequentially covered with an etching stop film SAC and an interlayer insulating film IL. The etching stop film SAC is used as an etching stop film in an anisotropic etching process for later forming a contact hole in the interlayer insulating film IL. The interlayer insulating film IL is formed by depositing an insulating film mainly composed of silicon oxide by, for example, a CVD method. For the etching stop film SAC, an insulating film mainly composed of silicon nitride is deposited by, for example, a CVD method as a material having a high etching selectivity with the silicon oxide film. Here, the region including the salicide block film SAB under the etching stop film SAC is a region including a thick silicon nitride film. This is because the upper layer of the salicide block film SAB is a protective nitride film t2 made of a silicon nitride film, and an etching stop film SAC also made of a silicon nitride film is formed thereon.

  Next, as shown in FIG. 11, in order to planarize the interlayer insulating film IL, polishing is performed from the upper surface. Here, surface polishing is performed by a chemical mechanical polishing (CMP) method.

  In the manufacturing method of the semiconductor device of the first embodiment, the salicide block film SAB is applied as a stop film in the polishing process of the interlayer insulating film IL by CMP. More specifically, CMP is performed on the interlayer insulating film IL, and the interlayer insulating film IL is polished until the salicide block film SAB is reached. That is, in the manufacturing method of the first embodiment, the CMP for the interlayer insulating film IL is not controlled by, for example, time, but is performed until the position of the salicide block film SAB is reached. In particular, in the process of the first embodiment, the high breakdown voltage gate G1 is formed higher than the other gates. Therefore, the polishing of the interlayer insulating film IL by CMP is performed on the salicide block film SAB formed on the upper surface of the high voltage gate G1 prior to any region of the salicide block film SAB (for example, the portion covering the memory gate G2). Reach. Thus, in this step, the interlayer insulating film IL is polished until it reaches the salicide block film SAB on the upper surface of the high breakdown voltage gate G1. The effect of the manufacturing method including such steps will be described in detail later.

  Next, as shown in FIG. 12, an interlayer insulating film IL is further stacked on the upper surface of the interlayer insulating film IL flattened by CMP polishing in the previous step. Here, for convenience, the interlayer insulating film IL deposited first and subjected to CMP polishing in the previous process is referred to as a first interlayer insulating film ILa, and the interlayer insulating film IL stacked in this process is used as the second interlayer insulating film ILb. Is written. The second interlayer insulating film ILb is formed by the same material and the same method as the first interlayer insulating film ILa. Since the underlying first interlayer insulating film ILa is planarized by surface polishing, the increased surface of the second interlayer insulating film ILb can also be maintained flat. The second interlayer insulating film ILb is formed in order to increase the withstand voltage between the metal wiring and gates formed on the interlayer insulating film IL in a later step.

  Next, as shown in FIG. 13, a contact plug cp is formed so as to penetrate the interlayer insulating film IL and reach the main surface s1 of the silicon substrate 1 or each gate in the portion where the metal silicide layer sc is formed. For this purpose, first, a contact hole (connection hole) CH that penetrates the interlayer insulating film IL and reaches the metal silicide layer sc is formed by photolithography or anisotropic etching. At this time, the etching stop film SAC formed under the interlayer insulating film IL is used as an etch stopper (etching stop layer). Thereby, over-etching to the silicon substrate 1 or the like can be prevented. Subsequently, a conductive film such as tungsten is deposited so as to fill the contact hole CH, and surface polishing is performed to bury the conductive film only in the contact hole CH, thereby forming the contact plug cp. In this step, the barrier metal described with reference to FIG. 3 may be formed.

  Subsequently, a metal wiring mw is formed on the interlayer insulating film IL so as to be electrically connected to the contact plug cp. For this purpose, a metal film such as aluminum is deposited, and then patterned by a photolithography method, an etching method, or the like, thereby forming a metal wiring mw having a desired shape. In the manufacturing method of the first embodiment, since the metal wiring mw is formed after the second interlayer insulating film ILb is stacked, the lower surface of the metal wiring mw and the upper surface of the high voltage gate G1 are at least the salicide block film SAB. They are separated by an interlayer insulating film IL by a distance larger than the film thickness. In this step, the barrier metal described with reference to FIG. 3 may be formed. Through the above steps, a semiconductor device having a high voltage MIS transistor Qh, a memory unit MIS transistor Qnvm, a medium voltage MIS transistor, and a high speed MIS transistor Qw is manufactured. The above is the manufacturing method of the semiconductor device of the first embodiment.

  In the method of manufacturing the semiconductor device according to the first embodiment, as described with reference to FIG. 11, when the interlayer insulating film IL is polished, the polishing amount is not controlled by time or the like, but the high breakdown voltage gate G1. Polishing is performed until the upper salicide block film SAB is reached. As described above, in the manufacturing method of the first embodiment, the polishing is intentionally performed to a predetermined position such as the salicide block film SAB on the high breakdown voltage gate G1. As a result, variations in the interlayer film thickness after polishing due to variations in the polishing rate can be made difficult to occur. This is because according to the manufacturing method of the first embodiment, the polishing of the interlayer insulating film IL by CMP is not stopped by setting with time, but is stopped by the salicide block film SAB which is a predetermined component. is there. As a result, the reliability of the semiconductor device formed through the step of polishing the surface of the interlayer insulating film can be improved.

  Furthermore, in the method of manufacturing the semiconductor device of the first embodiment, the step of forming the salicide block film SAB on the upper surface of the highest gate (high breakdown voltage gate G1) in the semiconductor device having gates having different heights will be described. did. Accordingly, it is possible to make it difficult to cut a gate having a high altitude in the polishing process of the interlayer insulating film IL by CMP. As a result, the reliability of the semiconductor device formed through the step of surface polishing the interlayer insulating film can be further improved.

  In the method for manufacturing the semiconductor device according to the first embodiment, the step of stopping the polishing of the interlayer insulating film IL by the CMP using the salicide block film SAB has been described. Here, any layer that can stop the polishing of the interlayer insulating film IL, regardless of the salicide block film SAB, is equally effective even if another stop layer is applied. More specifically, for example, a silicon nitride film having high selectivity with respect to the etching of the interlayer insulating film IL made of a silicon oxide film is similarly effective when formed as a CMP stop layer. However, in the manufacturing method of the first embodiment, it is more preferable to apply the salicide block film SAB as described above. The reason will be explained below. The salicide block film SAB has a function as a block film for a metal silicidation reaction for selectively forming the metal silicide layer sc. This has nothing to do with the function as a CMP stop layer. In the first embodiment, a method is described in which such a salicide block film SAB is used in combination with the CMP stop layer. That is, the salicide block film SAB effective as a CMP stop layer can be formed without introducing a new layer. As a result, the number of steps of the semiconductor device manufacturing method can be reduced.

  In the semiconductor device manufacturing method of the first embodiment, the example in which the memory gate G2 constituting the nonvolatile memory NVM as described in FIG. 2 is formed on the same silicon substrate 1 has been described. The above effect is also effective when applied to a method for manufacturing a semiconductor device having no nonvolatile memory NVM. However, from the viewpoint of more efficiently forming the salicide block film SAB, it is more effective when applied to a method of manufacturing a semiconductor device having the nonvolatile memory NVM as shown in FIG. The reason is as follows. As described above with reference to FIG. 2, it is more preferable that the memory gate G2 of the nonvolatile memory NVM is particularly covered with the salicide block film SAB having the protective nitride film t2. In other words, the semiconductor device having such a nonvolatile memory NVM includes a step of forming the salicide block film SAB including the protective nitride film t2. Therefore, even in the manufacturing process of the first embodiment, if the salicide block film SAB is patterned so as to remain on the upper surface of the gate with the highest altitude (high withstand voltage), the above effect can be exhibited. It can be applied as a CMP stop layer. That is, the manufacturing method of the first embodiment can be implemented without adding a new process. As a result, the number of steps of the semiconductor device manufacturing method can be reduced.

  In the manufacturing method of the semiconductor device of the first embodiment, the etching stop film SAC is formed at a position above the salicide block film SAB and below the interlayer insulating film IL. As described above, the etching stop film SAC is a film applied for forming the contact hole CH, and is not essential for obtaining the effect of the interlayer insulating film IL in CMP. However, it is more preferable to form the etching stop film SAC from the viewpoint that the silicon nitride film as the protective nitride film t2 constituting the salicide block film SAB can be made apparently thicker. More specifically, it is as follows. The above effect is manifested by stopping the polishing using the salicide block film SAB in the step of polishing the interlayer insulating film IL by CMP. Therefore, by arranging the salicide block film SAB and the etching stop film SAC together, the silicon nitride film is apparently thicker and more effective as a CMP stop layer. As a result, the reliability of the semiconductor device formed through the step of surface polishing the interlayer insulating film can be further improved.

  It is also possible to consider a configuration in which the salicide block film SAB is not formed on the high breakdown voltage gate G1, and the etching stop film SAC is used as the CMP stop layer. From the following viewpoints, it is desirable to use the salicide block film SAB as the CMP stop layer as in the first embodiment. First, as described with reference to FIG. 13, the etching stop film SAC is used as an etching stopper when forming the contact hole CH, and is formed to have a film thickness required from the process. Therefore, it is not preferable to apply the etching stop film SAC as a CMP stop layer when polishing the interlayer insulating film IL and reduce the thickness. Second, when the salicide block film SAB is not formed on the upper surface of the high breakdown voltage gate G1, the etching stop film SAC is directly formed on the high breakdown voltage gate G1. When such an etching stop film SAC is applied as a CMP stop layer, there is a high risk that the polishing of the interlayer insulating film IL reaches the high breakdown voltage gate G1. Therefore, instead of using the etching stop film SAC alone as a CMP stop layer, the salicide block film SAB, or the salicide block film SAB and the etching stop film SAC, as in the method of manufacturing the semiconductor device of the first embodiment, It is more effective to use the laminated film as a CMP stop layer.

  In the first embodiment, the semiconductor device having a plurality of MIS transistors having different heights and the manufacturing method thereof have been described. However, the present invention is applied to a semiconductor having a MIS transistor having the same height and a manufacturing method thereof. Is equally effective. However, for example, when the influence of the etching by CMP on the gate where the salicide block film SAB is not formed on the upper surface is taken into consideration, the height is different, and the salicide block film SAB can be formed on the upper surface of the highest gate. It is more effective to apply the semiconductor device manufacturing method as in the first embodiment.

  Further, in the manufacturing method of the first embodiment, as described in the process of FIG. 12, the interlayer insulating film IL is increased in order to improve the breakdown voltage between the metal wiring mw and each gate (second interlayer insulation). Membrane ILb). On the other hand, the breakdown voltage can be ensured also by other processes as described below.

  FIG. 14 is a step subsequent to FIG. 7 and shows a step of forming the salicide block film SAB in the same manner as the step of FIG. Here, in particular, the lower protective oxide film t1 constituting the salicide block film SAB is formed to a thickness of about 80 to 120 nm, and the upper protective nitride film t2 is formed to a thickness of about 20 to 30 nm.

  Subsequently, an etching stop film SAC and an interlayer insulating film IL are formed by a process similar to that described with reference to FIGS. 9 to 11, and the interlayer insulating film IL is polished by a CMP method. At this time, polishing of the interlayer insulating film IL by CMP is stopped when the salicide block film SAB is reached using the salicide block film SAB as a stop layer.

  Next, as shown in FIG. 15, the contact plug cp and the metal wiring mw are formed in the same manner as the method shown in FIG. Here, the interlayer insulating film IL is not added as described with reference to FIG. That is, according to this manufacturing method, the lower surface of the metal wiring mw and the upper surface of the salicide block film SAB on the high breakdown voltage gate G1 are arranged at the same height. In this method, the salicide block film SAB is formed sufficiently thick without increasing the interlayer insulating film IL, so that the breakdown voltage between the metal wiring mw and each gate can be ensured. Thus, the number of processes can be further reduced by not increasing the interlayer insulating film IL. Further, since the contact plug cp and the metal wiring mw are formed in the interlayer insulating film IL that has been subjected to the CMP process, the processing can be performed in a flatter state. Further, since the interlayer insulating film IL for forming the contact hole CH becomes thinner, the aspect ratio of the contact hole CH becomes smaller, and the processing accuracy can be further improved. As a result, the reliability of the semiconductor device formed through the step of surface polishing the interlayer insulating film can be further improved.

  On the other hand, when the breakdown voltage between the metal wiring mw and each gate is an important semiconductor element, the method of increasing the interlayer insulating film IL as described above is preferable. Also in that case, forming the salicide block film SAB thickly can function as a stronger CMP stop layer and is more effective.

  Further, as described above, the salicide block film SAB of the first embodiment is a film formed in a region where the metal silicide layer sc is not formed, and the influence of the thickness on other processes is small. Therefore, the degree of freedom of the set film thickness of the salicide block film SAB is higher than, for example, an etching stop film SAC used as an etching stopper for the contact hole CH. Also from this point of view, the etching stop film SAC is not used alone as a CMP stop layer, but the salicide block film SAB or the salicide block film SAB and the etching stop as in the method of manufacturing the semiconductor device of the first embodiment. It is more effective to use a laminated film with the film SAC as a CMP stop layer.

(Embodiment 2)
The structure of the semiconductor device according to the second embodiment will be described with reference to FIG. FIG. 16 shows a semiconductor device according to the second embodiment having a high breakdown voltage MIS transistor Qh and a high-speed MIS transistor Qw having the same configuration as that described with reference to FIGS. 1 to 3 in the first embodiment. The principal part sectional drawing of is shown. These configurations can exhibit the same effects as those described in the first embodiment. The semiconductor device of the second embodiment further has a dummy gate Gd on the same silicon substrate 1. The high breakdown voltage MIS transistor Qh and the high-speed MIS transistor Qw are formed in the main circuit region (first region) Ra of the silicon substrate 1, and the dummy gate Gd is formed in the peripheral region (second region) Rp of the silicon substrate 1. Here, the peripheral region Rp is a surplus region that is on the same silicon substrate 1 as the main circuit region Ra and does not form a semiconductor element constituting the semiconductor device.

  Here, the dummy gate Gd has the following configuration. The height of the dummy gate Gd in the peripheral region Rp is the same as the height of the high voltage gate G1 in the main circuit region Ra. The dummy gate Gd has a dummy gate insulating film IGd and a dummy gate electrode EGd formed in order on the main surface s1 of the silicon substrate 1. The dummy gate insulating film IGd has the same thickness as the high breakdown voltage gate insulating film IG1. Further, the upper surface of the dummy gate Gd is also covered with the salicide block film SAB, like the high breakdown voltage gate G1. In addition, the sidewall spacer 6 and the etching stop film SAC have the same configuration as that of the high breakdown voltage MIS transistor Qh. Further, FIG. 16 shows a structure in which a specific configuration is not arranged on the silicon substrate 1 below the dummy gate Gd. Here, a p-well pw1, a separation portion 2, a source / drain region sd1, a high-concentration n-type region 5, or a metal silicide layer sc similar to the high-breakdown-voltage MIS transistor Qh may be disposed.

  Arranging the dummy gate Gd as described above is effective in terms of the manufacturing method. Below, the manufacturing method of the semiconductor device of this Embodiment 2 including the process of forming dummy gate Gd is demonstrated using FIGS.

  First, as shown in FIG. 17, the high breakdown voltage MIS transistor Qh and the high-speed MIS transistor Qw are formed in the main circuit region Ra by the same process as in FIGS. Further, a dummy gate Gd is formed in the peripheral region Rp. Here, the dummy gate Gd is formed in the same manner as the step of forming the high breakdown voltage gate G1 of the high breakdown voltage MIS transistor Qh. Therefore, the high breakdown voltage gate G1 and the dummy gate Gd have the same height. As described above, the high speed gate G4 of the high speed MIS transistor Qw is lower than the high breakdown voltage gate G1 and the dummy gate Gd.

  Next, as shown in FIG. 18, a salicide block film SAB composed of the protective oxide film t1 and the protective nitride film t2 is formed in the same manner as the process described in FIG. Here, patterning is performed so that the salicide block film SAB remains on the upper surface of the dummy gate Gd in addition to the upper surface of the high breakdown voltage gate G1.

  Next, as shown in FIG. 19, a metal silicide layer sc, an etching stop film SAC, and an interlayer insulating film IL are formed in the same manner as the steps described in FIG. 9 and FIG. Here, not only the configuration of the main circuit region Ra but also the interlayer insulating film IL is formed so as to cover the dummy gate Gd in the peripheral region Rp.

  Next, as shown in FIG. 20, the interlayer insulating film IL is polished by the CMP method in the same manner as the process described in FIG. In particular, as in the method of FIG. 11, the polishing of the interlayer insulating film IL by CMP is stopped at the salicide block film SAB on the high breakdown voltage gate G1. Here, in the manufacturing method of the second embodiment, the dummy gate Gd is formed so as to have the same height as the high-breakdown-voltage gate G1. Accordingly, when the polishing of the interlayer insulating film IL by CMP reaches the salicide block film SAB on the high breakdown voltage gate G1, it also reaches the salicide block film SAB on the dummy gate Gd. As described above, according to the method of manufacturing the semiconductor device of the second embodiment, the CMP can be stopped by the salicide block film SAB on the two gates of the high breakdown voltage gate G1 and the dummy gate Gd. In other words, the occupancy ratio of the gate having the same height as the high-breakdown-voltage gate G1 of the high gate can be increased on the silicon substrate 1. As a result, erosion can be reduced, and the interlayer insulating film IL can be polished so as to reduce the variation in film thickness. As a result, the reliability of the semiconductor device formed through the step of surface polishing the interlayer insulating film can be further improved.

  In the subsequent process, the interlayer insulating film IL is increased, the contact hole CH is processed, the contact plug cp is formed, and the metal wiring mw is formed in the same manner as the process described with reference to FIGS. Through the above steps, the semiconductor device of the second embodiment shown in FIG. 16 can be formed. As described with reference to FIG. 14 and FIG. 15, the same effect can be obtained by forming the salicide block film SAB thick and forming the wiring structure without increasing the interlayer insulating film IL.

  In addition, it is more effective to dispose dummy gates Gd in the following locations in the peripheral region Rp other than the main circuit region Ra that forms the semiconductor elements constituting the semiconductor device in the surface of the silicon substrate 1. It is.

  FIG. 21 is a block diagram of an LCD driver DD as an example of the semiconductor device according to the second embodiment. In the LCD driver DD, the processing circuit 7 is disposed substantially at the center, and an SRAM (Static Random Access Memory) circuit 8 serving as a main storage device is disposed relatively close to the processing circuit 7. A control circuit 9 such as a gate driver, a source driver, or an input / output circuit is disposed around the processing circuit 7 and the SRAM circuit 8. Further, a nonvolatile memory circuit 10 serving as an auxiliary storage device is disposed at a position far from the processing circuit 7. The region where these circuits 7 to 10 are arranged is the main circuit region Ra in FIG.

  The SRAM circuit 8 is mainly configured by a high-speed MIS transistor Qw formed in the high-speed MIS region Rw of FIG. The control circuit 9 is mainly configured by a high voltage MIS transistor Qh formed in the high voltage MIS region Rh of FIG. 1 or FIG. The nonvolatile memory circuit 10 is mainly configured by a nonvolatile memory NVM having the memory unit MIS transistor Qnvm formed in the memory region Rnvm of FIG. 2 or FIG. As described above, the LCD driver DD includes a circuit having a low gate transistor (for example, an SRAM circuit 8 having a high speed MIS transistor Qw) and a circuit having a high gate transistor (for example, a high voltage MIS transistor Qh). The area of the control circuit 9) provided.

  Therefore, in the LCD driver DD of the second embodiment, the region of the SRAM circuit 8 is defined as the region of the control circuit 9 when the peripheral region Rp forming the dummy gate Gd described with reference to FIG. Place it at a position where it can be pinched. As a result, a region mainly composed of the low-speed high-speed MIS transistor Qw and a region mainly composed of the high-gate high-breakdown-voltage MIS transistor Qh and the dummy gate Gd are planarly sandwiched.

  With such an arrangement, in the process of polishing the interlayer insulating film IL as shown in FIG. 20, the high-voltage high-voltage gate G1 and the dummy gate arranged on both sides for the high-speed gate G4 having a low gate are arranged. Polishing stops at the upper surface with Gd. Therefore, the erosion phenomenon of the interlayer insulating film IL due to CMP is reduced, and it is possible to make it difficult to cause low gate shaving or the like. As a result, the reliability of the semiconductor device formed through the step of surface polishing the interlayer insulating film can be further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied, for example, to the semiconductor industry necessary for performing information processing in personal computers, mobile devices, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS It is a principal part top view of the semiconductor device which is Embodiment 1 of this invention, (a) is the top view which abbreviate | omitted the component on a silicon substrate, (b) is on a silicon substrate. It is the top view shown without omitting some components. It is another principal part top view of the semiconductor device which is Embodiment 1 of this invention. BRIEF DESCRIPTION OF THE DRAWINGS It is principal part sectional drawing of the semiconductor device which is Embodiment 1 of this invention, Comprising: The left of (a) is sectional drawing seen in the arrow direction along the AA line of FIG. 1, The right of (a) is Sectional drawing seen in the arrow direction along the BB line of FIG. 1, (b) is sectional drawing of another area | region. BRIEF DESCRIPTION OF THE DRAWINGS It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention, Comprising: The left of (a) is sectional drawing seen in the arrow direction along the AA of FIG. ) Is a cross-sectional view taken along the line BB in FIG. 1 in the direction of the arrow, and (b) is a cross-sectional view of another region. FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; FIG. 8 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 12; FIG. 8 is an essential part cross-sectional view during another manufacturing process of the semiconductor device according to the first embodiment of the present invention, which is subsequent to FIG. 7; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; It is principal part sectional drawing of the semiconductor device which is Embodiment 2 of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. FIG. 18 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 17; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; It is a block diagram of the semiconductor device which is Embodiment 2 of this invention.

Explanation of symbols

1 Silicon substrate (semiconductor substrate)
2 Separation part 3 Active region 4 Opening 5 High-concentration n-type region 6 Side wall spacer 7 Processing circuit 8 SRAM circuit 9 Control circuit 10 Non-volatile memory circuit CA Capacitance part CH Contact hole (connection hole)
CWE Data writing / erasing capacitor cp Contact plug DD LCD driver EG Gate conductor film EG1 High voltage gate electrode (gate electrode)
EG2 Memory gate electrode (gate electrode)
EG3 Medium voltage gate electrode (gate electrode)
EG4 High-speed gate electrode (gate electrode)
EGd dummy gate electrode ex1, ex2, ex3 extension region G1 high voltage gate (first gate)
G2 Memory gate (second gate)
G3 Medium voltage gate (second gate)
G4 High-speed gate (second gate)
Gd dummy gate IG gate insulating film IG1 high voltage gate insulating film (first gate insulating film)
IG2 Memory gate insulating film (second gate insulating film)
IG3 Medium voltage gate insulating film (second gate insulating film)
IG4 High-speed gate insulating film (second gate insulating film)
IGd dummy gate insulating film IL interlayer insulating film ILa first interlayer insulating film ILb second interlayer insulating film mw metal wiring NVM nonvolatile memory cell pw1, pw2, pw3, pw4 p well Qh high voltage MIS transistor Qm medium voltage MIS transistor Qnvm memory Part MIS transistor QR readout transistor QS selection transistor Qw high-speed MIS transistor Ra main circuit region (first region)
Rh High voltage MIS region Rm Medium voltage MIS region Rnvm Memory region Rp Peripheral region (second region)
Rw High-speed MIS region SAB Salicide block film (protective insulating film)
SAC etching stop film (nitride film for connection hole processing)
sc metal silicide layer sd1, sd2, sd3, sd4 source / drain region t1 protective oxide film t2 protective nitride film

Claims (19)

(A) forming a gate by sequentially forming a gate insulating film and a gate electrode on the main surface in the first region of the semiconductor substrate;
(B) forming a protective insulating film on the main surface of the semiconductor substrate;
(C) forming an interlayer insulating film on the main surface of the semiconductor substrate so as to cover the protective insulating film;
(D) polishing the interlayer insulating film by CMP,
In the step (b),
As the protective insulating film, a protective oxide film and a protective nitride film are formed in order from the lower layer,
An insulating film mainly composed of silicon oxide as the protective oxide film, and an insulating film mainly composed of silicon nitride as the protective nitride film;
In the step (d), the interlayer insulating film is polished until the protective insulating film on the upper surface of the gate is reached. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising:
(E) forming a dummy gate on the main surface in the second region on the semiconductor substrate;
In the step (e), the dummy gate is formed to have the same height as the gate by the same step as the step of forming the gate in the step (a). Method. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising:
(F) removing the part of the protective insulating film after the step (b) and before the step (c);
(G) After the step (f) and before the step (c), a metal silicide layer is self-aligned on the upper surface of the gate and the main surface of the semiconductor substrate in a portion not covered with the protective insulating film. And forming a process,
In the step (f), the protective insulating film in the region where the metal silicide layer is formed in the step (g) is removed. In the manufacturing method of the semiconductor device according to claim 3,
In the step (a),
Forming a first gate and a second gate having different heights as the gate;
A height of the first gate from the main surface of the semiconductor substrate is higher than that of the second gate;
In the step (e), the dummy gate is formed to have the same height as the first gate by the same step as the step of forming the first gate in the step (a).
In the step (f), a part of the protective insulating film is removed so that the protective insulating film remains on the first gate and a part on the dummy gate. Method. In the manufacturing method of the semiconductor device according to claim 4,
In the step (a),
By forming the first gate insulating film, which is the gate insulating film of the first gate, and the second gate insulating film, which is the gate insulating film of the second gate, with different film thicknesses, the heights are different from each other. Forming the first gate and the second gate;
The method of manufacturing a semiconductor device, wherein the first gate insulating film is formed to be thicker than the second gate insulating film. In the manufacturing method of the semiconductor device according to claim 5,
In the step (a), the second gate is formed so as to have the second gate for memory constituting the nonvolatile memory,
In the step (f), a part of the protective insulating film is removed so that the protective insulating film remains so as to cover the second gate for memory. The method of manufacturing a semiconductor device according to claim 6, further comprising:
(H) After the step (g) and before the step (c), a nitride film for processing connection holes is formed so as to cover the main surface of the semiconductor substrate,
(I) After the step (d), a contact plug that penetrates the interlayer insulating film and reaches the main surface or the gate of the semiconductor substrate, and an upper surface of the interlayer insulating film, And a step of forming a metal wiring so as to be connected electrically,
In the step (h), an insulating film mainly composed of silicon nitride is formed as the connection hole processing nitride film,
In the step (i), a connection hole for forming the contact plug is formed using the connection hole processing nitride film as an etching stop layer. The method of manufacturing a semiconductor device according to claim 7.
The method of manufacturing a semiconductor device, wherein the dummy gate is formed at a position sandwiching the second gate together with the first gate when the main surface of the semiconductor substrate is viewed in plan. 9. The method of manufacturing a semiconductor device according to claim 8, further comprising:
(J) A method of manufacturing a semiconductor device comprising a step of further stacking the interlayer insulating film on the interlayer insulating film after the step (d) and before the step (i). The method of manufacturing a semiconductor device according to claim 8.
In the step (b),
The protective oxide film is formed to have a thickness of 80 to 120 nm,
A method of manufacturing a semiconductor device, wherein the protective nitride film is formed to have a thickness of 20 to 30 nm. (A) a gate formed of a gate insulating film and a gate electrode, which is sequentially formed on the main surface in the first region of the semiconductor substrate;
(B) a dummy gate formed on the main surface in the second region of the semiconductor substrate;
(C) a protective insulating film formed on the main surface of the semiconductor substrate;
(D) having an interlayer insulating film formed on the main surface of the semiconductor substrate so as to cover the protective insulating film;
The protective insulating film has a protective oxide film and a protective nitride film in order from the lower layer,
The protective oxide film is an insulating film mainly composed of silicon oxide, and the protective nitride film is an insulating film mainly composed of silicon nitride,
The protective insulating film is formed so as to cover a part on the gate and the dummy gate,
The semiconductor device according to claim 1, wherein the gate in the first region and the dummy gate in the second region have the same height. 12. The semiconductor device according to claim 11, further comprising:
(E) having a metal silicide layer formed on a part of the upper surface of the gate or a part of the main surface of the semiconductor substrate;
The protective insulating film is formed so as not to cover a part of the gate or the semiconductor substrate,
The semiconductor device, wherein the metal silicide layer is formed on a portion of the upper surface of the gate and the main surface of the semiconductor substrate that is not covered with the protective insulating film. The semiconductor device according to claim 12, wherein
The gate of the first region has a first gate and a second gate having different heights,
The height of the first gate from the main surface of the semiconductor substrate is higher than that of the second gate,
The dummy gate of the second region is the same height as the first gate;
The semiconductor device, wherein the protective insulating film covers at least a part on the first gate and the dummy gate. The semiconductor device according to claim 13.
The first gate insulating film, which is the gate insulating film of the first gate, and the second gate insulating film, which is the gate insulating film of the second gate, have different thicknesses, so that the first gate And the second gate have different heights,
The semiconductor device according to claim 1, wherein the first gate insulating film is thicker than the second gate insulating film. The semiconductor device according to claim 14.
The second gate has a second gate for memory that constitutes a part of the nonvolatile memory,
The semiconductor device, wherein the protective insulating film is formed so as to cover the second gate for memory. 16. The semiconductor device according to claim 15, further comprising:
(F) a connection hole processing nitride film formed to cover the main surface of the semiconductor substrate and in a layer below the interlayer insulating film;
(G) a contact plug that penetrates the interlayer insulating film and reaches the main surface or the gate of the semiconductor substrate; and a metal that is disposed on the upper surface of the interlayer insulating film and is electrically connected to the contact plug Wiring and
The connection hole processing nitride film is formed above the protective insulating film at a location where the protective insulating film is formed on the main surface of the semiconductor substrate,
The connection hole processing nitride film is an insulating film mainly composed of silicon nitride. The semiconductor device according to claim 16.
The semiconductor device is characterized in that the dummy gate is disposed at a position sandwiching the second gate together with the first gate when the main surface of the semiconductor substrate is viewed in plan. The semiconductor device according to claim 17.
The semiconductor device according to claim 1, wherein the lower surface of the metal wiring and the upper surface of the first gate are separated by the interlayer insulating film by a distance larger than the film thickness of the protective insulating film. The semiconductor device according to claim 18.
The lower surface of the metal wiring and the upper surface of the protective insulating film are located at the same height,
Of the protective insulating film,
The protective oxide film has a thickness of 80 to 120 nm,
The semiconductor device according to claim 1, wherein the protective nitride film has a thickness of 20 to 30 nm.

Images