CN109840357B - Method and device for determining fatigue life of transistor module and computer equipment - Google Patents
Method and device for determining fatigue life of transistor module and computer equipment Download PDFInfo
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- CN109840357B CN109840357B CN201910015983.9A CN201910015983A CN109840357B CN 109840357 B CN109840357 B CN 109840357B CN 201910015983 A CN201910015983 A CN 201910015983A CN 109840357 B CN109840357 B CN 109840357B
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Abstract
The application relates to a transistor module fatigue life determining method, a transistor module fatigue life determining device, a computer device and a storage medium. The method comprises the following steps: acquiring the saturation voltage drop of the transistor module; inquiring a preset fatigue life prediction model corresponding to the transistor module, wherein the fatigue life prediction model is obtained according to the fitting fatigue life of the transistor module under different loads; and inputting the saturated voltage drop into a fatigue life prediction model to obtain the fatigue life of the transistor module. The method can accurately determine the fatigue life of the transistor module.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a method and an apparatus for determining a fatigue life of a transistor module, a computer device, and a storage medium.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a power switching device having many advantages such as high current carrying density and reduced saturation voltage, is a core device for energy conversion and transmission, and is widely applied in the fields of rail transit, smart grid, aerospace, electric vehicles, new energy equipment, and the like. However, with the increase of the power level, power density and switching frequency of the IGBT module, the losses generated by the power cycle of the IGBT and the continuous fluctuation of the internal junction temperature easily cause fatigue damage of the power device. By predicting the residual service life of the IGBT module, a maintenance strategy can be formulated, and the equipment fault can be effectively avoided.
At present, the traditional analytic method based on empirical data statistics has large data amount required by analysis and low accuracy of fatigue life prediction.
Disclosure of Invention
In view of the above, it is necessary to provide a transistor module fatigue life determining method, apparatus, computer device and storage medium capable of accurately determining the fatigue life of a transistor module.
A transistor module fatigue life determination method, the method comprising:
acquiring the saturation voltage drop of the transistor module;
inquiring a preset fatigue life prediction model corresponding to the transistor module, wherein the fatigue life prediction model is obtained according to the fitting fatigue life of the transistor module under different loads;
and inputting the saturated voltage drop into a fatigue life prediction model to obtain the fatigue life of the transistor module.
In one embodiment, before querying the transistor module corresponding to the preset fatigue life prediction model, the method further includes:
applying different loads to the transistor module to obtain stress-strain distributions respectively corresponding to the transistor module under different loads;
determining the stress-strain state of the transistor module according to the stress-strain distribution;
inquiring a stress-strain fatigue curve corresponding to the transistor module according to the stress-strain state to obtain the fitting fatigue life of the transistor module;
and obtaining a fatigue life prediction model according to the fitting fatigue lives.
In one embodiment, applying different loads to the transistor module to obtain stress-strain distributions of the transistor module corresponding to the different loads respectively comprises:
constructing a finite element model of the transistor module according to the geometric parameters of the transistor module;
different loads are applied to the transistor module, and stress-strain distribution corresponding to the transistor module under different loads is determined through electrothermal structure coupling calculation.
In one embodiment, determining the stress-strain state of the transistor module from the stress-strain distribution comprises:
determining the yield strength of the transistor module;
when the maximum stress of the transistor module is determined to be larger than the yield strength according to the stress-strain distribution, determining that the transistor module is in a strain fatigue state; otherwise, determining that the transistor module is in a stress fatigue state.
In one embodiment, the stress-strain-fatigue curves comprise a strain-fatigue curve and a stress-fatigue curve; according to the stress-strain state, inquiring a stress-strain fatigue curve corresponding to the transistor module, and obtaining the fitting fatigue life of the transistor module comprises the following steps:
when the transistor module is in a strain fatigue state, inquiring a strain fatigue curve, and determining the fitting strain fatigue life of the transistor module according to the strain fatigue curve, wherein the fitting strain fatigue life comprises the fitting strain fatigue life;
and when the transistor module is in a stress fatigue state, inquiring the stress fatigue curve, and determining the fitting stress fatigue life of the transistor module according to the stress fatigue curve, wherein the fitting stress fatigue life comprises the fitting stress fatigue life.
In one embodiment, before querying a stress-strain fatigue curve corresponding to the transistor module according to the stress-strain state to obtain a fitted fatigue life of the transistor module, the method further includes:
carrying out fatigue life test on the transistor module to obtain a test fatigue curve corresponding to the transistor module;
and adjusting the test fatigue curve according to preset process conditions to obtain a stress-strain fatigue curve.
In one embodiment, deriving the fatigue life prediction model from each of the fitted fatigue lives comprises:
determining saturation voltage drops corresponding to the transistor modules according to the loads;
and obtaining a fatigue life prediction model according to the corresponding relation between the saturation voltage drop of the transistor module and each fitting fatigue life.
A transistor module fatigue life determination apparatus, the apparatus comprising:
the saturated voltage drop acquisition module is used for acquiring the saturated voltage drop of the transistor module;
the prediction model query module is used for querying a corresponding preset fatigue life prediction model of the transistor module, and the fatigue life prediction model is obtained according to the fitting fatigue life of the transistor module under different loads;
and the fatigue life determining module is used for inputting the saturated voltage drop into the fatigue life prediction model to obtain the fatigue life of the transistor module.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the following steps when executing the computer program:
acquiring the saturation voltage drop of the transistor module;
inquiring a preset fatigue life prediction model corresponding to the transistor module, wherein the fatigue life prediction model is obtained according to the fitting fatigue life of the transistor module under different loads;
and inputting the saturated voltage drop into a fatigue life prediction model to obtain the fatigue life of the transistor module.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
acquiring the saturation voltage drop of the transistor module;
inquiring a preset fatigue life prediction model corresponding to the transistor module, wherein the fatigue life prediction model is obtained according to the fitting fatigue life of the transistor module under different loads;
and inputting the saturated voltage drop into a fatigue life prediction model to obtain the fatigue life of the transistor module.
According to the transistor module fatigue life determining method, the transistor module fatigue life determining device, the computer equipment and the storage medium, the saturated voltage drop of the transistor module is obtained, and the saturated voltage drop is input into the preset fatigue life prediction model to obtain the fatigue life of the transistor module. In the process of determining the fatigue life of the transistor module, the fatigue life of the transistor module is determined directly according to the saturation voltage drop of the transistor module by using a fatigue life prediction model obtained by fitting the fatigue life of the transistor module under different loads, so that the accuracy of determining the fatigue life of the transistor module is improved.
Drawings
FIG. 1 is a schematic flow chart of a method for determining fatigue life of a transistor module according to an embodiment;
FIG. 2 is a schematic flow chart illustrating the construction of a life prediction model in one embodiment;
FIG. 3 is an internal block diagram of a GD50HFL120C1S module in one embodiment;
FIG. 4 is a schematic diagram of a simulation model and a finite element model of the GD50HFL120C1S module in FIG. 3;
FIG. 5 is a temperature profile of the GD50HFL120C1S module of FIG. 3;
FIG. 6 is a graph of the potential distribution of the GD50HFL120C1S module of FIG. 3;
FIG. 7 is a thermal stress profile of the GD50HFL120C1S module of FIG. 3;
FIG. 8 is a schematic diagram of equivalent plastic deformation of the GD50HFL120C1S module of FIG. 3;
FIG. 9 is a schematic diagram of a fatigue life prediction model in one embodiment;
FIG. 10 is a block diagram showing the structure of a fatigue life determining apparatus for a transistor module according to an embodiment;
FIG. 11 is a diagram illustrating an internal structure of a computer device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, as shown in fig. 1, there is provided a transistor module fatigue life determining method, comprising the steps of:
step S101: and acquiring the saturation voltage drop of the transistor module.
The Transistor module may be an IGBT module, or may also be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a thyristor, a diode, or other Transistor modules that may be subjected to fatigue failure due to the influence of alternating thermal stress. The saturation voltage drop is the potential difference between the collector and emitter of a transistor when the transistor reaches saturation conduction. The saturation voltage drop of the transistor module can be obtained through a saturation voltage drop detection circuit, and the transistor module has different saturation voltage drops under different current loads.
Step S103: and inquiring a preset fatigue life prediction model corresponding to the transistor module, wherein the fatigue life prediction model is obtained according to the fitting fatigue life of the transistor module under different loads.
Among them, the number of stress cycles that a transistor module undergoes before fatigue failure is referred to as fatigue life. And inquiring a preset fatigue life prediction model corresponding to the transistor module, wherein the fatigue life prediction model is obtained according to the fitting fatigue life of the transistor module under different loads. Through the fatigue life prediction model, the corresponding fatigue life of the transistor module under different saturation voltage drops can be determined.
Step S105: and inputting the saturated voltage drop into a fatigue life prediction model to obtain the fatigue life of the transistor module.
And inputting the saturated voltage drop into a fatigue life prediction model to obtain the fatigue life of the transistor module. In a specific application, the fatigue life prediction model may include a fatigue life prediction curve, and then the corresponding fatigue life may be determined from the fatigue life prediction curve directly according to the saturation pressure drop.
In the method for determining the fatigue life of the transistor module, the saturated voltage drop of the transistor module is obtained, and the saturated voltage drop is input into a preset fatigue life prediction model to obtain the fatigue life of the transistor module. In the process of determining the fatigue life of the transistor module, the fatigue life of the transistor module is determined directly according to the saturation voltage drop of the transistor module by using a fatigue life prediction model obtained by fitting the fatigue life of the transistor module under different loads, so that the accuracy of determining the fatigue life of the transistor module is improved.
In an embodiment, as shown in fig. 2, before querying the preset fatigue life prediction model corresponding to the transistor module, the method further includes a step of building the life prediction model, specifically including:
step S201: and applying different loads to the transistor module to obtain stress-strain distributions respectively corresponding to the transistor module under different loads.
In the embodiment, the saturated voltage drop is selected as a prediction index, and a fatigue life prediction model is established by adopting a corresponding fatigue criterion, so that the fatigue life of the transistor module is rapidly and accurately predicted. Specifically, the fatigue life of the module is determined according to an electric-thermal-structure coupling calculation result and a material fatigue curve, then the load is changed to obtain the saturated pressure drop and the fatigue life under different working conditions, and the functional relation between the fatigue life and the saturated pressure drop is established by fitting data to obtain a fatigue life prediction model.
Specifically, different loads are applied to the transistor module, so that the transistor is in different saturation voltage drop states, and stress strain distributions respectively corresponding to the transistor module under different loads are obtained. For example, the thermal stress/strain profile generated by the transistor module can be calculated by electro-thermal-structural coupling.
Step S203: and determining the stress-strain state of the transistor module according to the stress-strain distribution.
The stress-strain state of the transistor module is determined according to the stress-strain distribution, and specifically, the stress-strain state of the transistor module can be determined according to the relationship between the maximum stress of the transistor module and the yield strength of the transistor module. The yield strength is the yield limit of the metal material when the yield phenomenon occurs, that is, the stress resisting micro plastic deformation.
Step S205: and inquiring a stress-strain fatigue curve corresponding to the transistor module according to the stress-strain state to obtain the fitting fatigue life of the transistor module.
After the stress-strain state of the transistor module is determined, a stress-strain fatigue curve corresponding to the transistor module is inquired, the stress-strain fatigue curve can be obtained by carrying out a fatigue life test on the IGBT module material and according to the relation between the alternating stress strain borne by the obtained part and the cycle frequency of fracture. From the stress-strain fatigue curve, the fitting fatigue life corresponding to the stress-strain state of the transistor module can be inquired and obtained.
Step S207: and obtaining a fatigue life prediction model according to the fitting fatigue lives.
And establishing a fatigue life prediction model of the transistor module under different loads according to the fitted fatigue life of the transistor module. Different loads correspond to different saturation voltage drops, and the fatigue life of the transistor module can be determined from the fatigue life prediction model through the saturation voltage drops of the transistor module.
In this embodiment, when determining the fatigue life of the transistor module by using the obtained fatigue life prediction model, the fatigue life prediction can be directly performed by combining the collector-emitter saturation voltage drop of the transistor module with the fatigue life prediction model, which is more direct and simple than a conventional method based on the internal junction temperature.
In one embodiment, applying different loads to the transistor module to obtain stress-strain distributions of the transistor module corresponding to the different loads respectively comprises: constructing a finite element model of the transistor module according to the geometric parameters of the transistor module; different loads are applied to the transistor module, and stress-strain distribution corresponding to the transistor module under different loads is determined through electrothermal structure coupling calculation.
Applying different loads to the transistor module, constructing a finite element model of the transistor module when calculating stress-strain distributions respectively corresponding to the transistor module under the different loads, and calculating the stress-strain distribution generated by the transistor module through electric-thermal-structure coupling based on the finite element model.
Specifically, a finite element model of the transistor module is constructed according to the geometric parameters of the transistor module. The geometric parameters include characteristic parameters such as length, width and height of the transistor. The finite element model is a model established by using a finite element analysis method, and is a group of unit combinations which are only connected at nodes, only transmit force by virtue of the nodes and are only restrained at the nodes. The transistor module can be subjected to network subdivision according to the geometric parameters of the transistor module to obtain a finite element model of the transistor module. Different loads are applied to the transistor module, stress-strain distribution corresponding to the transistor module under different loads is determined through electric heating structure coupling calculation, and the stress-strain distribution reflects the thermal stress and strain conditions of all parts of the transistor module.
In the embodiment, the boundary point of plastic strain and elastic strain in the module is determined through electric-thermal-structure coupling calculation, if the plastic strain occurs, the service life of the module is predicted by adopting the strain fatigue curve, and if only the elastic strain occurs, the service life of the module is predicted by adopting the stress fatigue curve, so that the accuracy of fatigue life prediction is improved.
In one embodiment, determining the stress-strain state of the transistor module from the stress-strain distribution comprises: determining the yield strength of the transistor module; when the maximum stress of the transistor module is determined to be larger than the yield strength according to the stress-strain distribution, determining that the transistor module is in a strain fatigue state; otherwise, determining that the transistor module is in a stress fatigue state.
And after stress strain distribution respectively corresponding to the transistor module under different loads is obtained, determining the stress strain state of the transistor by combining the yield strength of the transistor. Specifically, the yield strength of the transistor module is determined, which can be determined by graphic and index methods. Based on a finite element model of the transistor module, determining the maximum stress of the transistor module according to the stress-strain distribution, and comparing the maximum stress with the yield strength. When the maximum stress of the transistor module is greater than the yield strength, determining that the transistor module is in a strain fatigue state; otherwise, determining that the transistor module is in a stress fatigue state. Different stress-strain states can be used for life prediction through different life prediction models.
In one embodiment, the stress-strain fatigue curves comprise a strain fatigue curve and a stress fatigue curve; according to the stress-strain state, inquiring a stress-strain fatigue curve corresponding to the transistor module, and obtaining the fitting fatigue life of the transistor module comprises the following steps: when the transistor module is in a strain fatigue state, inquiring a strain fatigue curve, and determining the fitting strain fatigue life of the transistor module according to the strain fatigue curve, wherein the fitting strain fatigue life comprises the fitting strain fatigue life; and when the transistor module is in a stress fatigue state, inquiring the stress fatigue curve, and determining the fitting stress fatigue life of the transistor module according to the stress fatigue curve, wherein the fitting stress fatigue life comprises the fitting stress fatigue life.
The stress-strain-fatigue curves include strain-fatigue curves and stress-fatigue curves for fatigue life determination in a strained state and a stressed state, respectively. And when the fitted fatigue life of the transistor module is determined, determining the fitted strain fatigue life of the transistor module according to the strain fatigue curve (epsilon-N curve) when the transistor module is in a strain fatigue state. And when the transistor module is in a stress fatigue state, determining the fitting stress fatigue life of the transistor module according to the stress fatigue curve (S-N curve). The fitted fatigue life includes a fitted strain fatigue life and a fitted stress fatigue life.
In one embodiment, before querying a stress-strain fatigue curve corresponding to the transistor module according to the stress-strain state to obtain a fitted fatigue life of the transistor module, the method further includes: carrying out fatigue life test on the transistor module to obtain a test fatigue curve corresponding to the transistor module; and adjusting the test fatigue curve according to preset process conditions to obtain a stress-strain fatigue curve.
When the stress-strain fatigue curve is determined, the fatigue life of the transistor module can be tested, and a test fatigue curve corresponding to the transistor module is obtained. Specifically, the relationship between the alternating stress strain to which the component is subjected and the cycle number of fracture can be determined based on a fatigue life test, thereby obtaining a test fatigue curve. And (4) correcting the basic fatigue curve in consideration of the process treatment performed by actual processing, namely adjusting the test fatigue curve according to preset process conditions to obtain a stress-strain fatigue curve.
In one embodiment, deriving a fatigue life prediction model from each fitted fatigue life comprises: determining saturation voltage drops corresponding to the transistor modules according to the loads; and obtaining a fatigue life prediction model according to the corresponding relation between the saturation voltage drop of the transistor module and each fitting fatigue life.
Different loads correspond to different saturation voltage drops, and the fatigue life of the transistor module can be determined from the fatigue life prediction model through the saturation voltage drops of the transistor module. Specifically, according to each load, the saturation voltage drop corresponding to the transistor module is determined, the corresponding relation between the saturation voltage drop of the transistor module and each fitting fatigue life is further determined, and the fatigue life prediction model is obtained according to the corresponding relation. By changing the load, the fatigue life corresponding to the transistor module under different loads, namely under different saturation pressure drops, is repeatedly determined, and a fatigue life prediction model covering each saturation pressure drop and the corresponding fatigue life can be obtained. By adopting the electric-thermal-structure analysis, the fatigue failure mechanism in the module can be accurately researched, the test cost is reduced, the relation between the fatigue life and the saturated pressure drop is established according to the corresponding fatigue criterion, and the accuracy of life prediction is improved.
In one embodiment, a transistor module fatigue life determination method is provided, which is applied in the fatigue life determination of GD50HFL120C1S module. The internal structure of the GD50HFL120C1S module is shown in fig. 3, in which the terminal No. 1 is the collector of the tube 1, the terminal No. 2 is the emitter of the tube 1, and is also connected to the collector of the tube 2, 7 is the emitter voltage lead-out terminal of the tube 1, and 6 is the gate of the tube 1; terminal No. 3 is the emitter of tube 2, 5 is the emitter voltage terminal of tube 2, and 4 is the gate of tube 2, through which the electrical characteristics of the module can be measured. Considering that the module is of a double-tube structure, one IGBT chip is selected for analysis. Since the thermal conductivity of the encapsulant and the filled silicone is low, the heat is mainly dissipated downward through the copper substrate, and therefore, neglecting the silicone and the encapsulation above, the top of the module is considered to be in an adiabatic condition.
As shown in fig. 4, a finite element model of the IGBT module is established, a simulation model is established according to the physical model of the GD50HFL120C1S module, and the finite element model is obtained by meshing the simulation model. Applying a current load, selecting a current amplitude of 80A, a period of 6s and a duty ratio of 1/2, and calculating to obtain temperature, potential and thermal stress distribution through electro-thermal-structure coupling, wherein the temperature distribution, the potential distribution and the thermal stress distribution of the IGBT module are shown as 9s in FIGS. 5-7. By combining the yield strengths of the materials, as shown in fig. 8, which is an equivalent plastic deformation diagram of the IGBT module at 9s, it can be determined that the bonding wire has undergone plastic deformation, and the thermal stress on the other layers of materials is smaller than the yield strength thereof, and only elastic deformation occurs, so that the fatigue life of the IGBT module is longer than that of the bonding wire, and therefore the fatigue life of the IGBT module should be the number of cycles of strain fatigue failure of the bonding wire.
On the other hand, through fatigue test, stress and strain amplitude control is adopted, tension-compression symmetric fatigue is carried out (stress ratio R is equal to-1), the frequency is 50Hz, and a relation curve between the stress strain and the corresponding fracture cycle N is established. Considering the actual processing, the basic fatigue curve is corrected to obtain a stress fatigue curve (S-N curve) of the bonding wire without plastic strain, which can be expressed as the following formula (1):
Nf＝4.13e52·σ-32.06(1)
and the strain fatigue curve (epsilon-N curve) when the bonding wire is plastically strained can be expressed by the following formula (2):
Nf＝46.2·ε-1.09(2)
where σ represents the stress magnitude, ε represents the strain increment,N findicating the corresponding fatigue life.
The fatigue life of the IGBT module under the current load can be determined to be 8568 times according to the corrected epsilon-N curve and the calculation result of the electric-thermal-structure field.
The stress and equivalent plastic strain at different shell temperatures can be obtained by numerical calculation with varying applied load as shown in table 1 below, with a junction temperature of 51 ℃ being the demarcation point for elastic and plastic strain. A fatigue life prediction model of the IGBT module can be established by data fitting according to the data in table 1 as shown in fig. 9.
TABLE 1
According to the curve relation in fig. 9, the fatigue life of the bonding wire can be predicted only by measuring the saturation voltage drop at the external port without measuring the internal junction temperature first, so that the step of predicting the fatigue life of the bonding wire is simplified. The device is overhauled and replaced in advance according to the fatigue life under different saturation pressure drops, and equipment failure caused by fatigue failure can be avoided.
It should be understood that although the various steps in the flow charts of fig. 1-2 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-2 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, as shown in fig. 10, there is provided a transistor module fatigue life determining apparatus including: a saturation pressure drop obtaining module 601, a prediction model query module 603, and a fatigue life determining module 605, wherein:
a saturated voltage drop obtaining module 601, configured to obtain a saturated voltage drop of the transistor module;
the prediction model query module 603 is used for querying a corresponding preset fatigue life prediction model of the transistor module, and the fatigue life prediction model is obtained according to the fitting fatigue life of the transistor module under different loads;
and a fatigue life determining module 605, configured to input the saturated voltage drop into the fatigue life prediction model to obtain the fatigue life of the transistor module.
In one embodiment, further comprising a load application module, a transistor state module, a fitted fatigue life module, and a model building module, wherein: the load applying module is used for applying different loads to the transistor module to obtain stress-strain distributions respectively corresponding to the transistor module under different loads; the transistor state module is used for determining the stress-strain state of the transistor module according to the stress-strain distribution; the fitting fatigue life module is used for inquiring a stress-strain fatigue curve corresponding to the transistor module according to the stress-strain state to obtain the fitting fatigue life of the transistor module; and the model construction module is used for obtaining a fatigue life prediction model according to each fitting fatigue life.
In one embodiment, the load application module comprises a finite element model unit and a coupling calculation unit, wherein: the finite element model unit is used for constructing a finite element model of the transistor module according to the geometric parameters of the transistor module; and the coupling calculation unit is used for applying different loads to the transistor module, and determining stress strain distribution respectively corresponding to the transistor module under different loads through the coupling calculation of the electrothermal structure.
In one embodiment, a transistor status module includes a yield strength cell and a module status cell, wherein: the yield strength unit is used for determining the yield strength of the transistor module; the module state unit is used for determining that the transistor module is in a strain fatigue state when the maximum stress of the transistor module is determined to be greater than the yield strength according to the stress-strain distribution; otherwise, determining that the transistor module is in a stress fatigue state.
In one embodiment, the stress-strain fatigue curves comprise a strain fatigue curve and a stress fatigue curve; the fitting fatigue life module comprises a strain fatigue unit and a stress fatigue unit, wherein: the strain fatigue unit is used for inquiring a strain fatigue curve when the transistor module is in a strain fatigue state, and determining the fitting strain fatigue life of the transistor module according to the strain fatigue curve, wherein the fitting strain fatigue life comprises the fitting strain fatigue life; and the stress fatigue unit is used for inquiring the stress fatigue curve when the transistor module is in a stress fatigue state, and determining the fitting stress fatigue life of the transistor module according to the stress fatigue curve, wherein the fitting stress fatigue life comprises the fitting stress fatigue life.
In one embodiment, the system further comprises a fatigue testing module and a test curve adjustment module, wherein: the fatigue testing module is used for testing the fatigue life of the transistor module to obtain a testing fatigue curve corresponding to the transistor module; and the test curve adjusting module is used for adjusting the test fatigue curve according to preset process conditions to obtain a stress-strain fatigue curve.
In one embodiment, the model building module comprises a saturation pressure drop unit and a prediction model building unit, wherein: the saturation voltage drop unit is used for determining saturation voltage drops corresponding to the transistor modules according to the loads; and the prediction model construction unit is used for obtaining a fatigue life prediction model according to the corresponding relation between the saturation voltage drop of the transistor module and each fitting fatigue life.
For specific definition of the transistor module fatigue life determining device, reference may be made to the above definition of the transistor module fatigue life determining method, which is not described herein again. The above-mentioned transistor module fatigue life determination device may be implemented in whole or in part by software, hardware, or a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as shown in fig. 11. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a transistor module fatigue life determination method.
Those skilled in the art will appreciate that the architecture shown in fig. 11 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the following steps when executing the computer program:
acquiring the saturation voltage drop of the transistor module;
inquiring a preset fatigue life prediction model corresponding to the transistor module, wherein the fatigue life prediction model is obtained according to the fitting fatigue life of the transistor module under different loads;
and inputting the saturated voltage drop into a fatigue life prediction model to obtain the fatigue life of the transistor module.
In one embodiment, the processor, when executing the computer program, further performs the steps of: applying different loads to the transistor module to obtain stress-strain distributions respectively corresponding to the transistor module under different loads; determining the stress-strain state of the transistor module according to the stress-strain distribution; inquiring a stress-strain fatigue curve corresponding to the transistor module according to the stress-strain state to obtain the fitting fatigue life of the transistor module; and obtaining a fatigue life prediction model according to the fitting fatigue lives.
In one embodiment, the processor, when executing the computer program, further performs the steps of: constructing a finite element model of the transistor module according to the geometric parameters of the transistor module; different loads are applied to the transistor module, and stress-strain distribution corresponding to the transistor module under different loads is determined through electrothermal structure coupling calculation.
In one embodiment, the processor, when executing the computer program, further performs the steps of: determining the yield strength of the transistor module; when the maximum stress of the transistor module is determined to be larger than the yield strength according to the stress-strain distribution, determining that the transistor module is in a strain fatigue state; otherwise, determining that the transistor module is in a stress fatigue state.
In one embodiment, the stress-strain fatigue curves comprise a strain fatigue curve and a stress fatigue curve; the processor, when executing the computer program, further performs the steps of: when the transistor module is in a strain fatigue state, inquiring a strain fatigue curve, and determining the fitting strain fatigue life of the transistor module according to the strain fatigue curve, wherein the fitting strain fatigue life comprises the fitting strain fatigue life; and when the transistor module is in a stress fatigue state, inquiring the stress fatigue curve, and determining the fitting stress fatigue life of the transistor module according to the stress fatigue curve, wherein the fitting stress fatigue life comprises the fitting stress fatigue life.
In one embodiment, the processor, when executing the computer program, further performs the steps of: carrying out fatigue life test on the transistor module to obtain a test fatigue curve corresponding to the transistor module; and adjusting the test fatigue curve according to preset process conditions to obtain a stress-strain fatigue curve.
In one embodiment, the processor, when executing the computer program, further performs the steps of: determining saturation voltage drops corresponding to the transistor modules according to the loads; and obtaining a fatigue life prediction model according to the corresponding relation between the saturation voltage drop of the transistor module and each fitting fatigue life.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:
acquiring the saturation voltage drop of the transistor module;
inquiring a preset fatigue life prediction model corresponding to the transistor module, wherein the fatigue life prediction model is obtained according to the fitting fatigue life of the transistor module under different loads;
and inputting the saturated voltage drop into a fatigue life prediction model to obtain the fatigue life of the transistor module.
In one embodiment, the computer program when executed by the processor further performs the steps of: applying different loads to the transistor module to obtain stress-strain distributions respectively corresponding to the transistor module under different loads; determining the stress-strain state of the transistor module according to the stress-strain distribution; inquiring a stress-strain fatigue curve corresponding to the transistor module according to the stress-strain state to obtain the fitting fatigue life of the transistor module; and obtaining a fatigue life prediction model according to the fitting fatigue lives.
In one embodiment, the computer program when executed by the processor further performs the steps of: constructing a finite element model of the transistor module according to the geometric parameters of the transistor module; different loads are applied to the transistor module, and stress-strain distribution corresponding to the transistor module under different loads is determined through electrothermal structure coupling calculation.
In one embodiment, the computer program when executed by the processor further performs the steps of: determining the yield strength of the transistor module; when the maximum stress of the transistor module is determined to be larger than the yield strength according to the stress-strain distribution, determining that the transistor module is in a strain fatigue state; otherwise, determining that the transistor module is in a stress fatigue state.
In one embodiment, the stress-strain fatigue curves comprise a strain fatigue curve and a stress fatigue curve; the computer program when executed by the processor further realizes the steps of: when the transistor module is in a strain fatigue state, inquiring a strain fatigue curve, and determining the fitting strain fatigue life of the transistor module according to the strain fatigue curve, wherein the fitting strain fatigue life comprises the fitting strain fatigue life; and when the transistor module is in a stress fatigue state, inquiring the stress fatigue curve, and determining the fitting stress fatigue life of the transistor module according to the stress fatigue curve, wherein the fitting stress fatigue life comprises the fitting stress fatigue life.
In one embodiment, the computer program when executed by the processor further performs the steps of: carrying out fatigue life test on the transistor module to obtain a test fatigue curve corresponding to the transistor module; and adjusting the test fatigue curve according to preset process conditions to obtain a stress-strain fatigue curve.
In one embodiment, the computer program when executed by the processor further performs the steps of: determining saturation voltage drops corresponding to the transistor modules according to the loads; and obtaining a fatigue life prediction model according to the corresponding relation between the saturation voltage drop of the transistor module and each fitting fatigue life.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A transistor module fatigue life determination method, the method comprising:
acquiring saturation voltage drop of a transistor module, wherein the saturation voltage drop of the transistor module is acquired through a saturation voltage drop detection circuit, the transistor module has different saturation voltage drops under different current loads, and the saturation voltage drop is potential difference between a collector electrode and an emitter electrode of a transistor when the transistor is in saturated conduction;
inquiring a fatigue life prediction model which is preset corresponding to the transistor module and based on saturation voltage drop, wherein the fatigue life prediction model is obtained according to the fitting fatigue life of the transistor module under different loads and is used for determining the corresponding relation between the saturation voltage drop and the fatigue life of the module;
and inputting the saturated voltage drop into the fatigue life prediction model to obtain the fatigue life of the transistor module.
2. The method of claim 1, further comprising, prior to said querying the transistor module for a corresponding predetermined fatigue life prediction model:
applying different loads to the transistor module to obtain stress-strain distributions respectively corresponding to the transistor module under the different loads;
determining a stress-strain state of the transistor module according to the stress-strain distribution;
inquiring a stress-strain fatigue curve corresponding to the transistor module according to the stress-strain state to obtain the fitting fatigue life of the transistor module;
and obtaining the fatigue life prediction model according to each fitting fatigue life.
3. The method of claim 2, wherein the applying different loads to the transistor module to obtain stress-strain distributions of the transistor module corresponding to the different loads comprises:
constructing a finite element model of the transistor module according to the geometric parameters of the transistor module;
applying different loads to the transistor module, and determining stress-strain distributions respectively corresponding to the transistor module under different loads through electrothermal structure coupling calculation.
4. The method of claim 2, wherein determining a stress-strain state of the transistor module from the stress-strain profile comprises:
determining a yield strength of the transistor module;
when the maximum stress of the transistor module is determined to be larger than the yield strength according to the stress-strain distribution, determining that the transistor module is in a strain fatigue state; otherwise, determining that the transistor module is in a stress fatigue state.
5. The method of claim 2, wherein the stress-strain fatigue curves comprise a strain fatigue curve and a stress fatigue curve; the inquiring of the stress-strain fatigue curve corresponding to the transistor module according to the stress-strain state to obtain the fitting fatigue life of the transistor module comprises the following steps:
when the transistor module is in a strain fatigue state, inquiring the strain fatigue curve, and determining a fitting strain fatigue life of the transistor module according to the strain fatigue curve, wherein the fitting strain fatigue life comprises the fitting strain fatigue life;
and when the transistor module is in a stress fatigue state, inquiring the stress fatigue curve, and determining the fitting stress fatigue life of the transistor module according to the stress fatigue curve, wherein the fitting stress fatigue life comprises the fitting stress fatigue life.
6. The method according to claim 5, before said querying a stress-strain fatigue curve corresponding to the transistor module according to the stress-strain state to obtain a fitted fatigue life of the transistor module, further comprising:
carrying out fatigue life test on the transistor module to obtain a test fatigue curve corresponding to the transistor module;
and adjusting the test fatigue curve according to preset process conditions to obtain the stress-strain fatigue curve.
7. The method of any of claims 2 to 6, wherein said deriving said fatigue life prediction model from each of said fitted fatigue lives comprises:
determining saturation voltage drops respectively corresponding to the transistor modules according to the loads;
and obtaining the fatigue life prediction model according to the corresponding relation between the saturation pressure drop of the transistor module and the fitting fatigue life.
8. A transistor module fatigue life determining apparatus, characterized in that the apparatus comprises:
the transistor module has different saturation voltage drops under different current loads, and the saturation voltage drop is the potential difference between a collector electrode and an emitter electrode of the transistor when the transistor is in saturated conduction;
the prediction model query module is used for querying a preset fatigue life prediction model based on saturation voltage drop corresponding to the transistor module, the fatigue life prediction model is obtained according to the fitting fatigue life of the transistor module under different loads, and the fatigue life prediction model is used for determining the corresponding relation between the saturation voltage drop and the fatigue life of the module;
and the fatigue life determining module is used for inputting the saturated voltage drop into the fatigue life prediction model to obtain the fatigue life of the transistor module.
9. A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor implements the steps of the method of any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 7.
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| CN105550397A (en) * | 2015-12-03 | 2016-05-04 | 三峡大学 | IGBT module state evaluation method based on damage voltage |
| CN109143012A (en) * | 2017-06-28 | 2019-01-04 | 联合汽车电子有限公司 | IGBT remaining life predictor method |
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| CN109033709B (en) * | 2018-08-30 | 2020-03-31 | 电子科技大学 | Component fatigue life evaluation method based on nonlinear fatigue damage accumulation theory |
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| CN109143012A (en) * | 2017-06-28 | 2019-01-04 | 联合汽车电子有限公司 | IGBT remaining life predictor method |
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