CN109839982B

CN109839982B - Transceiver circuit with adjustable slew rate

Info

Publication number: CN109839982B
Application number: CN201711207011.7A
Authority: CN
Inventors: 许智勋; 赖俊豪
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2017-11-27
Filing date: 2017-11-27
Publication date: 2020-04-28
Anticipated expiration: 2037-11-27
Also published as: CN109839982A

Abstract

The present invention provides a transceiver circuit, comprising: the first capacitor and the first current pump circuit are used for charging or discharging the first capacitor so as to output a first voltage; a second capacitor; the second current pump circuit is used for charging or discharging the second capacitor to output a second voltage. The charging rate or the discharging rate of the first capacitor by the first current pump circuit respectively determines the rising rate of revolution or the falling rate of revolution of the first voltage; the charging rate or the discharging rate of the second capacitor by the second current pump circuit respectively determines the rising slew rate or the falling slew rate of the second voltage.

Description

Transceiver circuit with adjustable slew rate

Technical Field

The present invention relates to a transceiver circuit, and more particularly, to a transceiver circuit capable of adjusting slew rate.

Background

In the conventional transceiver circuit, voltage signals corresponding to different phases are provided according to input signals, and the voltage slew rate can be adjusted only by matching a complex circuit or providing a voltage source or a current source with adjustable output capability, which increases the circuit complexity, the process difficulty and the related cost for the design of the transceiver circuit.

Therefore, it is an important subject of the present industry to provide a transceiver circuit with a simple circuit and a controllable voltage slew rate.

Disclosure of Invention

In view of this, an embodiment of the present invention discloses a transceiver circuit, including: a first capacitor having a first end and a second end, the second end of the first capacitor being electrically connected to a ground potential; a first current pump circuit electrically connected to the first end of the first capacitor, for adjusting the operation according to a first input signal to charge or discharge the first capacitor, so that the first end of the first capacitor outputs a first voltage; a second capacitor having a first end and a second end, the second end of the second capacitor being electrically connected to the ground potential; a second current pump circuit, electrically connected to the first end of the second capacitor, for adjusting the operation according to a second input signal to charge or discharge the second capacitor, so that the first end of the second capacitor outputs a second voltage; a first voltage clamping circuit electrically connected to the first end of the first capacitor; a second voltage clamping circuit electrically connected to the first end of the first capacitor; a third voltage clamping circuit electrically connected to the first end of the second capacitor; and a fourth voltage clamping circuit electrically connected to the first end of the second capacitor; wherein, the charging rate or the discharging rate of the first capacitor by the first current pump circuit respectively determines the rising rate of revolution or the falling rate of revolution of the first voltage; the charging rate or the discharging rate of the second capacitor by the second current pump circuit respectively determines the rising rate of revolution or the falling rate of revolution of the second voltage; when the first current pump circuit charges or discharges the first capacitor, the first voltage of the first capacitor is between a low reference voltage of the first voltage clamp circuit and a high reference voltage of the second voltage clamp circuit; wherein when the second current pump circuit charges or discharges the second capacitor, the second voltage of the second capacitor is between the low reference voltage of the third voltage clamp circuit and the high reference voltage of the fourth voltage clamp circuit; when the first voltage reaches the low reference voltage or the high reference voltage, the first current pump circuit stops charging or discharging the first capacitor according to the voltage clamping action of the first voltage clamping circuit or the second voltage clamping circuit; when the second voltage reaches the low reference voltage or the high reference voltage, the second current pump circuit stops charging or discharging the second capacitor according to the voltage clamping action of the third voltage clamping circuit or the fourth voltage clamping circuit.

In view of this, an embodiment of the present invention discloses a transceiver circuit, including: a first capacitor having a first end and a second end, the second end of the first capacitor being electrically connected to a ground potential; a first current pump circuit electrically connected to the first end of the first capacitor for charging or discharging the first capacitor according to a first input signal; a first voltage clamping circuit electrically connected to the first end of the first capacitor; a second voltage clamping circuit electrically connected to the first end of the first capacitor; when the first current pump circuit charges the first capacitor according to the first input signal, the first end of the first capacitor outputs a first voltage, the second voltage clamp circuit performs voltage clamp operation, and when the first voltage rises to a high reference voltage, the first voltage is maintained at the high reference voltage; when the first current pump circuit discharges the first capacitor according to the first input signal, the first end of the first capacitor outputs the first voltage, the first voltage clamp circuit performs voltage clamp operation, and when the first voltage is reduced to a low reference voltage, the first voltage is maintained at the low reference voltage. Wherein, the charging rate or the discharging rate of the first capacitor by the first current pump circuit respectively determines the rising rate of revolution or the falling rate of revolution of the first voltage; when the first voltage reaches the low reference voltage or the high reference voltage, the first current pump circuit stops charging or discharging the first capacitor according to the voltage clamping action of the first voltage clamping circuit or the second voltage clamping circuit.

In summary, the transceiver circuit of the embodiment of the invention has a simple structure and a circuit architecture capable of adjusting and controlling the voltage slew rate, and the circuit for adjusting the slew rate can be effectively controlled by the voltage clamping circuit, so that the circuit control manner tends to be simple. The circuit can be effectively simplified and the cost can be reduced.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic diagram of a transceiver circuit according to an embodiment of the invention.

Fig. 2 is another schematic diagram of a transceiver circuit according to an embodiment of the invention.

Description of reference numerals:

1. 1': transceiver circuit

CP1, CP 1': first current pump circuit

CP2, CP 2': second current pump circuit

VC1, VC 1': first voltage clamping circuit

VC2, VC 2': second voltage clamping circuit

VC3, VC 3': third voltage clamping circuit

VC4, VC 4': fourth voltage clamping circuit

BU 1: first voltage buffer

BU 2: second voltage buffer

DOP: differential output circuit

VS: reference voltage

INP: a first signal input terminal

INN: second signal input terminal

IS1, IS 1': a first current source

IS2、

: a second current source

IS 3: a third current source

IS 4: a fourth current source

IS5, IS 5': a fifth current source

IS6, IS 6': a sixth current source

IS 7: a seventh current source

IS 8: eighth current source

SW 1: first switch

SW 2: second switch

SW 3: third switch

SW 4: the fourth switch

SW 5: fifth switch

SW 6: sixth switch

SW 7: seventh switch

SW 8: eighth switch

C1: first capacitor

C2: second capacitor

C3: third capacitor

C4: fourth capacitor

M1: first switching unit

M2: second switching unit

M3: third switching unit

M4: fourth switching unit

M5: fifth switching unit

M6: sixth switching unit

M7: seventh switching unit

M8: eighth switching unit

VL: low reference voltage

VH: high reference voltage

VDD: reference potential

P1, P2: positive input end

N1, N2: negative input terminal

O1, O2: output end

T1: a first input terminal

T2: second input terminal

V1: first voltage

V2: second voltage

R1: first impedance

R2: second impedance

R3: third impedance

R4: fourth impedance

R5: fifth impedance

R6: sixth impedance

R7: the seventh impedance

R8: eighth impedance

OPP: positive output terminal

OPN: negative output end

COM 1: first comparator

COM 2: second comparator

COM 3: third comparator

COM 4: fourth comparator

Detailed Description

Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present concepts. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The transceiver circuit will be described in at least one embodiment with reference to the drawings, however, the following embodiments are not intended to limit the disclosure.

In the following description, an electronic component having two terminals has a left terminal as a first terminal and a right terminal as a second terminal if the electronic component is horizontally disposed, and has an upper terminal as a first terminal and a lower terminal as a second terminal if the electronic component is vertically disposed. If the electronic device has more than three terminals, the mark of each terminal is used as the main mark.

[ embodiments of the transceiver circuit of the present invention ]

Referring to fig. 1, fig. 1 is a schematic diagram of a transceiver circuit according to an embodiment of the invention.

The transceiver circuit 1 includes a first current pump circuit CP1, a second current pump circuit CP2, a first capacitor C1, a second capacitor C2, a first voltage clamp VC1, a second voltage clamp VC2, a third voltage clamp VC3, a ground-four voltage clamp VC4, a first voltage buffer BU1, a second voltage buffer BU2, and a differential output circuit DOP.

The first current pump circuit CP1, the first capacitor C1, the first voltage clamp circuit VC, the second voltage clamp circuit VC2, and the first voltage buffer BU1 can be regarded as one side of a differential circuit. In contrast, the second current pump circuit CP2, the second capacitor C2, the third voltage clamp circuit VC3, the fourth voltage clamp circuit VC4, and the second voltage buffer BU2 are the other circuits of the differential circuit. That is, in other embodiments, the circuit on any side may be used alone to output voltage, and the design may be performed according to actual requirements, which is not limited in the present invention.

The first current pump circuit CP1 includes a first signal input INP, and the second current pump circuit CP2 includes a second signal input INN. The first signal input terminal INP of the first current pump circuit CP1 and the second signal input terminal INN of the second current pump circuit CP2 respectively receive an input signal to adjust the charging or discharging operations of the first current pump circuit CP1 and the second current pump circuit CP2, respectively, so as to charge or discharge the first capacitor C1 or the second capacitor C2, respectively. Respectively outputting a first voltage V1 and a second voltage V2. In the present embodiment, the input signals received by the first signal input terminal INP and the second signal input terminal INN are continuous signals with High Voltage (High Voltage) and Low Voltage (Low Voltage) or digital signals, which can be adjusted according to actual requirements, and the invention is not limited thereto.

In the present embodiment, the first current pump circuit CP1 is electrically connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is electrically connected to a ground potential. The first voltage clamp circuit VC1 and the second voltage clamp circuit VC2 are electrically connected to the first end of the first capacitor C1, respectively. The first voltage buffer BU1 has a positive input terminal P1, a negative input terminal N1, and an output terminal O1. The positive input terminal P1 of the first voltage buffer BU1 is electrically connected to the first terminal of the first capacitor C1, so as to receive the first voltage V1 and output a stable first voltage V1. The output terminal O1 of the first voltage buffer BU1 is electrically connected to the negative input terminal N1 of the first voltage buffer BU 1.

The second current pump circuit CP2 is electrically connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is electrically connected to a ground potential. The third voltage clamp circuit VC3 and the fourth voltage clamp circuit VC4 are electrically connected to the first end of the second capacitor C2, respectively. The second voltage buffer BU2 has a positive input terminal P2, a negative input terminal N2, and an output terminal O2. The positive input terminal P2 of the second voltage buffer BU2 is electrically connected to the first terminal of the second capacitor C2, so as to receive the second voltage V2 and output a stable second voltage V2. The output terminal O2 of the second voltage buffer BU2 is electrically connected to the negative input terminal N2 of the second voltage buffer BU 2.

The differential output circuit DOP includes a first input terminal T1, a second input terminal T2, a positive output terminal OPP and a negative output terminal OPN. The first input terminal T1 of the differential output circuit DOP is electrically connected to the output terminal O1 of the first voltage buffer BU 1. The second input terminal T2 of the differential output circuit DOP is electrically connected to the output terminal O2 of the second voltage buffer BU 2.

In the present embodiment, when the first current pump circuit CP1 charges the first capacitor C1, that is, the first voltage V1 at the first end of the first capacitor C1 continuously increases to a high reference voltage VH, the second voltage clamp circuit VC2 also operates simultaneously with the first current pump circuit CP1, so that the first voltage V1 is maintained at the high reference voltage VH. In addition, when the first voltage clamp circuit VC1 clamps the first voltage V1, the first current pump circuit CP1 correspondingly stops charging the first capacitor C1.

When the first current pump circuit CP1 discharges the first capacitor C1, that is, the first voltage V1 at the first end of the first capacitor C1 continuously drops to the low reference voltage VL, the first voltage clamp circuit VC1 operates with the first current pump circuit CP1 at the same time, so that the first voltage V1 is maintained at the low reference voltage VL. In addition, when the first voltage clamp circuit VC1 clamps the first voltage V1, the first current pump circuit CP1 correspondingly stops discharging the first capacitor C1.

In the present embodiment, when the second current pump circuit CP2 charges the second capacitor C2, that is, the second voltage V2 at the first end of the second capacitor C2 continuously rises to the high reference voltage VH, the fourth voltage clamp circuit VC4 also operates with the second current pump circuit CP2 at the same time, so that the second voltage V2 is maintained at the high reference voltage VH. In addition, when the second voltage clamp circuit VC2 clamps the second voltage V2, the second current pump circuit CP2 correspondingly stops charging the second capacitor C2.

When the second current pump circuit CP2 discharges the second capacitor C2, i.e., the second voltage V2 at the first end of the second capacitor C2 continuously drops to the low reference voltage VL, the third voltage clamp circuit VC3 also operates simultaneously with the second current pump circuit CP2, so that the second voltage V2 is maintained at the low reference voltage VL. In addition, when the third voltage clamp circuit VC3 clamps the second voltage V2, the second current pump circuit CP2 stops discharging the second capacitor C2 accordingly.

In the present embodiment, the voltage Slew Rate (Slew Rate) of the first voltage V1 is adjusted by the magnitude of the charging current or the magnitude of the discharging current supplied from the first current pump circuit CP 1. That is, the rising slew rate or the falling slew rate of the first voltage V1 is adjusted by the magnitude of the charging current or the magnitude of the discharging current supplied from the first current pump circuit CP 1. Similarly, the Rising Slew Rate (Rising Slew Rate) or the Falling Slew Rate (Falling Slew Rate) of the second voltage V2 is adjusted by the magnitude of the charging current or the magnitude of the discharging current provided by the second current pump circuit CP 2. That is, the rising slew rate and the falling slew rate of the first voltage V1 are determined according to the charging rate or the discharging rate of the first capacitor C1 by the first current pump circuit CP 1. The rising slew rate and the falling slew rate of the second voltage V2 are determined according to the charging rate or the discharging rate of the second capacitor C2 by the second current pump circuit CP 2.

In the embodiment, the first current pump circuit CP1 includes a first current source IS1, a second current source IS2, a first switch SW1 and a second switch SW 2.

The first current source IS1, the first switch SW1, the second switch SW2 and the second current source IS2 are connected in series.

In the embodiment, the first current source IS1 and the second current source IS2 are connected in series through the first switch SW1 and the second switch SW2, and the first switch SW1 and the second switch SW2 are respectively controlled by the first signal input terminal INP. In the embodiment, the first switch SW1 and the second switch SW2 are not turned on at the same time, but only one of the first switch SW1 and the second switch SW2 IS turned on according to the input signal of the first signal input terminal INP, so that the first current source IS1 or the second current source IS2 charges or discharges the first capacitor C1.

Similarly, the second current pump circuit CP2 includes a third switch SW3, a fourth switch SW4, a fifth current source IS5 and a sixth current source IS 6.

In the embodiment, the fifth current source IS5 and the sixth current source IS6 are connected in series through the third switch SW3 and the fourth switch SW4, and the third switch SW3 and the fourth switch SW4 are respectively controlled by the second signal input terminal INN. In the embodiment, the third switch SW3 and the fourth switch SW4 are not turned on at the same time, but only one of the third switch SW3 and the fourth switch SW4 IS turned on according to the input signal of the second signal input terminal INN, so that the fifth current source IS5 or the sixth current source IS6 charges or discharges the second capacitor C2.

In addition, the first terminals of the first current source IS1 and the fifth current source IS5 are electrically connected to a reference voltage VS. The second terminals of the second current source IS2 and the sixth current source IS6 are electrically connected to a ground potential.

The first voltage clamp circuit VC1 includes a first switching unit M1, a second switching unit M2, and a third current source IS 3. The first switching unit M1 and the second switching unit M2 respectively have a first terminal, a second terminal and a third terminal. The first terminal of the first switching unit M1 is electrically connected to a reference potential VDD. The second terminal of the first switch unit M1 is electrically connected to the second terminal and the first terminal of the second switch unit M2. The third terminal of the first switching unit M1 is electrically connected to the first terminal of the first capacitor C1. The first terminal of the second switching unit M2 IS electrically connected to the third current source IS 3. The third terminal of the second switching unit M2 is electrically connected to a low reference voltage VL.

The second voltage clamp circuit VC2 includes a third switching unit M3, a fourth switching unit M4, and a fourth current source IS 4. The third switch M3 and the fourth switch M4 have a first terminal, a second terminal and a third terminal, respectively. The first end of the third switch unit M3 is electrically connected to the first end of the first capacitor C1. The second terminal of the third switch M3 is electrically connected to the second terminal and the third terminal of the fourth switch M4. The third terminal of the third switching unit M3 is electrically connected to a ground potential. The first terminal of the fourth switching unit M4 is electrically connected to a high reference voltage VH. The third terminal of the fourth switching unit M4 IS electrically connected to a fourth current source IS 3.

In the embodiment, the second current pump circuit CP2 includes a fifth current source IS5, a sixth current source IS6, a third switch SW3 and a fourth switch SW 4.

The third voltage clamp circuit VC3 includes a fifth switching unit M5, a sixth switching unit M6, and a seventh current source IS 7. The fifth switch M5 and the sixth switch M6 respectively have a first terminal, a second terminal and a third terminal. The first terminal of the fifth switching unit M5 is electrically connected to the reference potential VDD. The second terminal of the fifth switch M5 is electrically connected to the second terminal and the first terminal of the sixth switch M6. The third terminal of the fifth switch unit M5 is electrically connected to the first terminal of the second capacitor C2. The first end of the sixth switching unit M6 IS electrically connected to the seventh current source IS 7. The third terminal of the sixth switching unit M6 is electrically connected to the low reference voltage VL. In this embodiment, the design of each voltage level can be adjusted according to actual requirements, and is not limited in the present invention.

The fourth voltage clamp circuit VC4 includes a seventh switching unit M7, an eighth switching unit M8, and an eighth current source IS 8. The seventh switch M7 and the eighth switch M8 respectively have a first terminal, a second terminal and a third terminal. The first end of the seventh switch unit M7 is electrically connected to the first end of the second capacitor C2. The second terminal of the seventh switching unit M3 is electrically connected to the second terminal and the third terminal of the eighth switching unit M8. The third terminal of the seventh switching unit M7 is electrically connected to the ground potential. The first terminal of the eighth switching unit M8 is electrically connected to the high reference voltage VH. The third terminal of the eighth switching unit M8 IS electrically connected to the eighth current source IS 8.

In the present embodiment, when the first current source IS1 of the first current pump circuit CP1 charges the first capacitor C1, the fourth current source IS4 of the second voltage clamp VC2 IS also activated, and when the current flowing through the current mirror circuit of the second voltage clamp VC2 IS equal to the current charged to the first capacitor C1 by the first current source IS1, the first voltage V1 of the first capacitor C1 IS clamped at the high reference voltage VH.

Similarly, when the second current source IS2 of the first current pump circuit CP1 discharges the first capacitor C1, the third current source IS3 of the first voltage clamp VC1 also operates simultaneously, and when the current flowing through the current mirror circuit of the first voltage clamp VC1 IS equal to the current discharged from the second current source IS2 to the first capacitor C1, the first voltage V1 of the first capacitor C1 IS clamped at the low reference voltage VL.

Similarly, in the present embodiment, when the fifth current source IS5 of the second current pump circuit CP1 charges the second capacitor C1, the current mirror circuit of the third voltage clamp VC3 also operates simultaneously, and when the current flowing through the current mirror circuit of the fourth voltage clamp VC4 IS equal to the current magnitude charged by the fifth current source IS5 to the second capacitor C2, the second voltage V2 of the second capacitor C2 IS clamped at the high reference voltage VH.

Similarly, when the sixth current source IS6 of the second current pump circuit CP1 discharges the second capacitor C2, the current mirror circuit of the fourth voltage clamp circuit VC4 also operates simultaneously, and when the current flowing through the current mirror circuit of the fourth voltage clamp circuit VC4 IS equal to the current discharged from the sixth current source IS6 to the second capacitor C2, the second voltage V2 of the second capacitor C2 IS clamped at the low reference voltage VL.

In the present embodiment, the differential output circuit DOP includes a first impedance R1, a second impedance R2, a third impedance R3, a fourth impedance R4, a fifth impedance R5, a sixth impedance R6, a seventh impedance R7, an eighth impedance R8, a third capacitor C3, and a fourth capacitor C4. The first resistor R1, the third capacitor C3 and the seventh resistor R7 are connected in series, and the first end of the third resistor R3 is electrically connected between the second end of the first resistor R1 and the first end of the third capacitor C3. The second end of the third impedance R3 is electrically connected to the ground potential. The first end of the fifth impedance R5 is electrically connected to a reference voltage VS. The second terminal of the fifth resistor R5 is electrically connected between the second terminal of the first resistor R1 and the first terminal of the third capacitor C3, and is electrically connected to the first terminal of the third resistor R3. Similarly, the second resistor R2, the fourth capacitor C4 and the eighth resistor R8 are also connected in series. The first end of the fourth resistor R4 is electrically connected between the second end of the second resistor R2 and the first end of the fourth capacitor C4. The second end of the fourth impedance R4 is electrically connected to the ground potential. The first end of the sixth impedance R6 is electrically connected to the reference voltage VS. The second terminal of the sixth resistor R6 is electrically connected between the second terminal of the second resistor R2 and the first terminal of the fourth capacitor C4, and is electrically connected to the first terminal of the fourth resistor R4. The seventh resistor R7 and the eighth resistor R8 are connected in series.

In the present embodiment, the first terminal of the first impedance R1 is the first input terminal T1 of the differential output circuit DOP, and the first terminal of the second impedance R2 is the second input terminal T2 of the differential output circuit DOP. The second terminal of the third capacitor C3 is the positive output terminal OPP of the differential output circuit DOP, and the second terminal of the fourth capacitor C4 is the negative output terminal OPN of the differential output circuit DOP. In the present embodiment, the differential output circuit DOP is used for receiving the stable first voltage V1 and the second voltage V2 to output two differential output signals. Therefore, the actual circuit is not limited to this embodiment, and can be adjusted according to actual requirements, and is not limited in the present invention.

[ Another embodiment of the transceiver circuit of the present invention ]

Referring to fig. 2, fig. 2 is a schematic diagram of a transceiver circuit according to an embodiment of the invention.

In the present embodiment, the transceiver circuit 1 ' has a structure similar to that of the transceiver circuit 1 in the previous embodiment, however, the first current pump circuit CP1 ', the second current pump circuit CP2 ', the first voltage clamp circuit VC1 ', the second voltage clamp circuit VC2 ', the third voltage clamp circuit VC3 ', and the fourth voltage clamp circuit VC4 ' of the transceiver circuit 1 of the present embodiment are partially different from the first current pump circuit CP1, the second current pump circuit CP2, the first voltage clamp circuit VC1, the second voltage clamp circuit VC2, the third voltage clamp circuit VC3, and the fourth voltage clamp circuit VC4 of the transceiver circuit 1 in internal structure, which will be described in detail in the following paragraphs.

The transceiver circuit 1 ' includes a first current pump circuit CP1 ', a second current pump circuit CP2 ', a first capacitor C1, a second capacitor C2, a first voltage clamp circuit VC1 ', a second voltage clamp circuit VC2 ', a third voltage clamp circuit VC3 ', a fourth voltage clamp circuit VC4 ', a first voltage buffer BU1, a second voltage buffer BU2, and a differential output circuit DOP.

The first current pump circuit CP1 ', the first capacitor C1, the first voltage clamp circuit VC1 ', the second voltage clamp circuit VC2 ' and the first voltage buffer BU1 can be regarded as a circuit on one side of the differential output. In contrast, the second current pump circuit CP2 ', the second capacitor C2, the third voltage clamp circuit VC3 ', the fourth voltage clamp circuit VC4 ' and the second voltage buffer BU2 are the other side of the differential output.

The first current pump circuit CP1 'includes a first signal input INP, and the second current pump circuit CP 2' includes a second signal input INN. The first signal input terminal INP of the first current pump circuit CP1 'and the second signal input terminal INN of the second current pump circuit CP 2' respectively receive an input signal to adjust operations of the first current pump circuit CP1 'and the second current pump circuit CP 2', respectively, so as to charge or discharge the first capacitor C1 or the second capacitor C2, respectively. Respectively outputting a first voltage V1 and a second voltage V2.

In the present embodiment, the first current pump circuit CP 1' is electrically connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is electrically connected to a ground potential. The first voltage clamp circuit VC1 'and the second voltage clamp circuit VC 2' are electrically connected to the first end of the first capacitor C1, respectively. The first voltage buffer BU1 has a positive input terminal P1, a negative input terminal N1, and an output terminal O1. The positive input terminal P1 of the first voltage buffer BU1 is electrically connected to the first terminal of the first capacitor C1, so as to receive the first voltage V1 and output a stable first voltage V1. The output terminal O1 of the first voltage buffer BU1 is electrically connected to the negative input terminal N1 of the first voltage buffer BU 1.

The second current pump circuit CP 2' is electrically connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is electrically connected to a ground potential. The third voltage clamp circuit VC3 'and the fourth voltage clamp circuit VC 4' are electrically connected to the first end of the second capacitor C2, respectively. The second voltage buffer BU2 has a positive input terminal P2, a negative input terminal N2, and an output terminal O2. The positive input terminal P2 of the second voltage buffer BU2 is electrically connected to the first terminal of the second capacitor C2, so as to receive the second voltage V2 and output a stable second voltage V2. The output terminal O2 of the second voltage buffer BU2 is electrically connected to the negative input terminal N2 of the second voltage buffer BU 2.

In the present embodiment, when the first current pump circuit CP1 'charges the first capacitor C1, that is, the first voltage V1 at the first end of the first capacitor C1 continuously increases to a high reference voltage VH, the second voltage clamp circuit VC 2' is activated to maintain the first voltage V1 at the high reference voltage VH. When the first current pump circuit CP1 'discharges the first capacitor C1, that is, the first voltage V1 at the first end of the first capacitor C1 continuously drops to the low reference voltage VL, the first voltage clamp circuit VC 1' is activated to maintain the first voltage V1 at the low reference voltage VL.

In the present embodiment, when the second current pump circuit CP2 'charges the second capacitor C2, that is, the second voltage V2 at the first end of the second capacitor C2 continuously increases to the high reference voltage VH, the fourth voltage clamp circuit VC 4' is activated to maintain the second voltage V2 at the high reference voltage VH. When the second current pump circuit CP2 'discharges the second capacitor C2, i.e., the second voltage V2 at the first end of the second capacitor C2 continuously drops to the low reference voltage VL, the third voltage clamp circuit VC 3' is activated to maintain the second voltage V2 at the low reference voltage VL.

In the present embodiment, the voltage Slew Rate (Slew Rate) of the first voltage V1 is adjusted by the magnitude of the charging current or the magnitude of the discharging current provided by the first current pump circuit CP 1'. That is, the rising slew rate or the falling slew rate of the first voltage V1 is adjusted by the magnitude of the charging current or the magnitude of the discharging current supplied from the first current pump circuit CP 1'. Similarly, the Rising Slew Rate (Rising Slew Rate) or the Falling Slew Rate (Falling Slew Rate) of the second voltage V2 is adjusted by the magnitude of the charging current or the magnitude of the discharging current provided by the second current pump circuit CP 2'. That is, the rising slew rate and the falling slew rate of the first voltage V1 are determined according to the charging rate or the discharging rate of the first capacitor C1 by the first current pump circuit CP 1'. The rising slew rate and the falling slew rate of the second voltage V2 are determined according to the charging rate or the discharging rate of the second capacitor C2 by the second current pump circuit CP 2'.

The first current pump circuit CP1 ' includes a first switch SW1, a second switch SW2, a first current source IS1 ' and a second current source IS2 '.

In the embodiment, the first current source IS1 'and the second current source IS 2' are connected in series through the first switch SW1 and the second switch SW2, and the first switch SW1 and the second switch SW2 are respectively controlled by the first signal input terminal INP. In the embodiment, the first switch SW1 and the second switch SW2 are not turned on at the same time, but only one of the first switch SW1 and the second switch SW2 IS turned on according to the input signal of the first signal input terminal INP, so that the first current source IS1 'or the second current source IS 2' charges or discharges the first capacitor C1.

Similarly, the second current pump circuit CP2 ' includes a third switch SW3, a fourth switch SW4, a fifth current source IS5 ' and a sixth current source IS6 '.

In the embodiment, the fifth current source IS5 'and the sixth current source IS 6' are connected in series through the third switch SW3 and the fourth switch SW4, and the third switch SW3 and the fourth switch SW4 are respectively controlled by the second signal input terminal INN. In the present embodiment, the third switch SW3 and the fourth switch SW4 are not turned on at the same time, but only one of the third switch SW3 and the fourth switch SW4 IS turned on according to the input signal of the second signal input terminal INN, so that the fifth current source IS5 'or the sixth current source IS 6' charges or discharges the second capacitor C2.

In the embodiment, the first current pump circuit CP 1' further includes a fifth switch SW5 and a sixth switch SW6 connected in series with the first switch SW1 and the second switch SW 2. The fifth switch SW5 is electrically connected to the second voltage clamp circuit VC 2'. The sixth switch SW6 is electrically connected to the first voltage clamp circuit VC 1'. That is, the fifth switch SW5 is controlled by the second voltage clamp VC2 ', and the sixth switch SW6 is controlled by the first voltage clamp VC 1'.

In addition, the first terminals of the first current source IS1 'and the fifth current source IS 5' are electrically connected to a reference voltage VS. The second terminals of the second current source IS2 'and the sixth current source IS 6' are electrically connected to a ground potential.

In the present embodiment, the first voltage clamp circuit VC1 'includes a first comparator COM1, and the second voltage clamp circuit VC 2' includes a second comparator COM 2. The negative input terminal of the first comparator COM1 IS electrically connected to the first terminal of the first capacitor C1, the positive input terminal of the first comparator COM1 IS electrically connected to the low reference voltage VL, and the output terminal of the first comparator COM1 outputs a control signal for controlling the sixth switch SW6 to be turned on and off, that IS, controlling the discharging operation of the second current source IS 2' on the first capacitor. The negative input terminal of the second comparator COM2 IS electrically connected to the first terminal of the first capacitor C1, the positive input terminal of the second comparator COM2 IS electrically connected to the high reference voltage VH, and the output terminal of the second comparator COM2 outputs a control signal for controlling the on and off of the fifth switch SW5, that IS, controlling the charging operation of the first current source IS 1'.

Similarly, the second current pump circuit CP 2' further includes a seventh switch SW7 and an eighth switch SW8 connected in series with the third switch SW3 and the fourth switch SW 4. The seventh switch SW7 is electrically connected to the fourth voltage clamp circuit VC 4'. The eighth switch SW8 is electrically connected to the third voltage clamp circuit VC 3'. That is, the seventh switch SW7 is controlled by the fourth voltage clamp circuit VC4 ', and the eighth switch SW8 is controlled by the third voltage clamp circuit VC 3'.

In the present embodiment, the third voltage clamp circuit VC3 'includes a third comparator COM3, and the fourth voltage clamp circuit VC 4' includes a fourth comparator COM 4. The negative input terminal of the third comparator COM3 is electrically connected to the first terminal of the second capacitor C2, the positive input terminal of the third comparator COM3 is electrically connected to the low reference voltage VL, and the output terminal of the third comparator COM3 outputs a control signal for controlling the on and off of the eighth switch SW 8. The negative input terminal of the fourth comparator COM4 is electrically connected to the first terminal of the first capacitor C1, the positive input terminal of the fourth comparator COM4 is electrically connected to the high reference voltage VH, and the output terminal of the fourth comparator COM4 outputs a control signal for controlling the seventh switch SW7 to be turned on or off.

In the present embodiment, the differential output circuit DOP of the transceiver circuit 1' has the same circuit structure as the differential output circuit DOP of the transceiver circuit 1 of the previous embodiment, and is not described herein again.

[ possible technical effects of the embodiment ]

The above description is only an example of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A transceiver circuit, comprising:

a first capacitor having a first end and a second end, the second end of the first capacitor being electrically connected to a ground potential;

a first current pump circuit electrically connected to the first end of the first capacitor, for adjusting the operation according to a first input signal to charge or discharge the first capacitor, so that the first end of the first capacitor outputs a first voltage;

a second capacitor having a first end and a second end, the second end of the second capacitor being electrically connected to the ground potential;

a second current pump circuit, electrically connected to the first end of the second capacitor, for adjusting the operation according to a second input signal to charge or discharge the second capacitor, so that the first end of the second capacitor outputs a second voltage;

a first voltage clamping circuit electrically connected to the first end of the first capacitor;

a second voltage clamping circuit electrically connected to the first end of the first capacitor;

a third voltage clamping circuit electrically connected to the first end of the second capacitor; and

a fourth voltage clamping circuit electrically connected to the first end of the second capacitor;

the charging rate and the discharging rate of the first capacitor by the first current pump circuit determine the voltage slew rate of the first voltage, and the charging rate and the discharging rate of the second capacitor by the second current pump circuit determine the voltage slew rate of the second voltage;

wherein the first voltage and the second voltage are between a low reference voltage of the first voltage clamp circuit and the third voltage clamp circuit and a high reference voltage of the second voltage clamp circuit and the fourth voltage clamp circuit;

when the first voltage or the second voltage reaches the low reference voltage or the high reference voltage, the first current pump circuit stops charging or discharging the first capacitor corresponding to the voltage clamping action of the first voltage clamping circuit or the second voltage clamping circuit, and when the second voltage reaches the low reference voltage or the high reference voltage, the second current pump circuit stops charging or discharging the second capacitor according to the voltage clamping action of the third voltage clamping circuit or the fourth voltage clamping circuit.

2. The transceiver circuit of claim 1,

the first current pump circuit includes:

a first current source; and

a second current source;

the first current source and the second current source are respectively electrically connected with the first capacitor and respectively charge or discharge the first capacitor, and the first current source and the second current source correspond to the voltage clamping action of the first voltage clamping circuit and the second voltage clamping circuit and stop charging or discharging the first capacitor;

the second current pump circuit includes:

a fifth current source; and

a sixth current source;

the fifth current source and the sixth current source are respectively electrically connected to the second capacitor and respectively charge or discharge the second capacitor, and the fifth current source and the sixth current source stop charging or discharging the second capacitor in response to the voltage clamping operation of the third voltage clamping circuit and the fourth voltage clamping circuit.

3. The transceiver circuit of claim 1, further comprising:

a first voltage buffer electrically connected to the first end of the first capacitor for receiving the first voltage to stably output the first voltage; and

and the second voltage buffer is electrically connected with the first end of the second capacitor and used for receiving the second voltage so as to stably output the second voltage.

4. The transceiver circuit of claim 2, further comprising:

a differential output circuit, including a first input terminal and a second input terminal, the first input terminal being electrically connected to an output terminal of the first voltage buffer for receiving the first voltage, the second input terminal being electrically connected to an output terminal of the second voltage buffer for receiving the second voltage;

the transceiver circuit outputs two differential output signals through the differential output circuit.

5. A transceiver circuit, comprising:

a first current pump circuit electrically connected to the first end of the first capacitor for charging or discharging the first capacitor according to a first input signal;

a first voltage clamping circuit electrically connected to the first end of the first capacitor; and

when the first voltage rises to a high reference voltage, the second voltage clamping circuit performs a voltage clamping action to maintain the first voltage at the high reference voltage;

when the first voltage drops to a low reference voltage, the first voltage clamp circuit performs a voltage clamp operation to maintain the first voltage at the low reference voltage;

wherein, the charging rate or the discharging rate of the first capacitor by the first current pump circuit respectively determines the rising rate of revolution or the falling rate of revolution of the first voltage;

when the first voltage reaches the low reference voltage or the high reference voltage, the first current pump circuit stops charging or discharging the first capacitor according to the voltage clamping action of the first voltage clamping circuit or the second voltage clamping circuit.

6. The transceiver circuit of claim 5, wherein the first current pump circuit comprises: a first current source and a second current source, which charge or discharge the first capacitor according to the adjustment action of a first input signal.

7. The transceiver circuit of claim 5, further comprising:

a first voltage buffer, electrically connected to the first end of the first capacitor, for receiving the first voltage to stably output the first voltage.

8. A transceiver circuit, comprising:

a first current pump circuit, electrically connected to the first end of the first capacitor, for adjusting the operation according to a first input signal to charge or discharge the first capacitor, so that the first end of the first capacitor outputs a first voltage, wherein the first voltage is between a low reference voltage and a high reference voltage;

a second capacitor having a first end and a second end, the second end of the second capacitor being electrically connected to the ground potential; and

a second current pump circuit, electrically connected to the first end of the second capacitor, for adjusting the operation according to a second input signal to charge or discharge the second capacitor, so that the first end of the second capacitor outputs a second voltage, wherein the second voltage is between the low reference voltage and the high reference voltage;

the charging rate or the discharging rate of the second capacitor by the second current pump circuit respectively determines the rising slew rate or the falling slew rate of the second voltage.

9. The transceiver circuit of claim 8, wherein the first current pump circuit stops charging or discharging the first capacitor according to a voltage clamping action of a first voltage clamp circuit or a second voltage clamp circuit when the first voltage reaches the low reference voltage or the high reference voltage;

when the second voltage reaches the low reference voltage or the high reference voltage, the second current pump circuit stops charging or discharging the second capacitor according to a voltage clamping action of a third voltage clamping circuit or a fourth voltage clamping circuit.