CN101783671A - Turnover rate control circuit - Google Patents
Turnover rate control circuit Download PDFInfo
- Publication number
- CN101783671A CN101783671A CN200910002711A CN200910002711A CN101783671A CN 101783671 A CN101783671 A CN 101783671A CN 200910002711 A CN200910002711 A CN 200910002711A CN 200910002711 A CN200910002711 A CN 200910002711A CN 101783671 A CN101783671 A CN 101783671A
- Authority
- CN
- China
- Prior art keywords
- buffer
- output impedance
- control circuit
- revolution rate
- rate control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007306 turnover Effects 0.000 title claims abstract description 48
- 230000000630 rising effect Effects 0.000 claims description 12
- 230000005526 G1 to G0 transition Effects 0.000 claims description 9
- 230000001174 ascending effect Effects 0.000 claims description 6
- 230000007704 transition Effects 0.000 claims description 6
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000006641 stabilisation Effects 0.000 abstract 1
- 238000011105 stabilization Methods 0.000 abstract 1
- 230000004913 activation Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 101100400452 Caenorhabditis elegans map-2 gene Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The invention relates to a turnover rate control circuit. An output impedance buffer and a turnover rate buffer are mutually connected in parallel. An edge detector detects input signals for controlling the output impedance buffer and the turnover rate buffer. In the increasing or decreasing period, the input signals mainly pass through the turnover rate buffer; and in the stabilization period, the input signals only pass through the output impedance buffer, thereby simultaneously meeting the specifications of the turnover rate and the output impedance.
Description
Technical field
The present invention relates to the output stage of circuit, particularly relate to a kind of revolution rate (slew rate) control circuit that is used for high-speed, low-power conveyer (transmitter).
Background technology
Mobile industry processor interface (Mobile Industry Processor Interface, MIPI) be a kind of high-speed, low-power sequence transceiver (transceiver) interface, be used to provide the communication between the mobile device (for example digital camera, display or other portable apparatus) of high-speed, low-power.Its physical layer transmission standard (D-PHY) further defines physical layer, and device comes transmitting high speed data by the link between conveyer end and the receiver end (link).
The revolution rate (slew rate, SR) and output impedance (R
Out) be two kinds in the middle of the numerous standards of MIPI.The revolution rate is the maximum change rate of signal in the circuit.Low revolution rate can cause the distortion of signal.On the other hand, the output impedance of conveyer (Tx) must be big as much as possible, just can make the operation of conveyer (Tx) can not be subjected to the influence of external loading.In general, in order to design a practical circuit (for example above-mentioned MIPI low-power conveyer), revolution rate and output impedance must be compromised between the two.According to the MIPI standard, for the conveyer (Tx) of tool external load capacitance value 0-70 picofarad (pF), its revolution rate must be in a particular range, and its output impedance must be not less than a particular value.In order to meet the standard of revolution rate and output impedance simultaneously, can allow the design of MIPI low-power conveyer become complexity and cost height usually.
Fig. 1 shows the output-stage circuit of traditional MIPI conveyer (Tx).Electric capacity 10 and resistance 12 in graphic are connected between output and the input, are used for obtaining acceptable revolution rate and output impedance with compromising.Yet when external loading increased, the design of conveyer must increase its output to keep the revolution rate, so tends to reduce simultaneously its output impedance.In other words, revolution rate and output impedance can form adverse influence mutually usually, cause the difficulty of design.
In view of traditional circuit (for example MIPI conveyer) in when design, can't use ball bearing made using and can reach compromise between revolution rate and the output impedance effectively, therefore need badly and propose a kind of high-speed interface circuit, be used for taking into account simultaneously revolution rate and output impedance.
Summary of the invention
In view of above-mentioned, one of purpose of the present invention makes the output stage of circuit (for example low-power conveyer) can meet the standard of revolution rate and output impedance simultaneously for a kind of uncomplicated and not expensive interface circuit is provided.
According to the embodiment of the invention, output impedance buffer and revolution rate buffer are in parallel mutually, and after the output addition of the output of output impedance buffer and revolution rate buffer, as the output signal of whole turnover rate control circuit.Edge finder is surveyed input signal, is used to control output impedance buffer and revolution rate buffer.Therefore, when be in rise or decrement phase between, input signal is mainly by revolution rate buffer, at this moment, the output signal of turnover rate control circuit can rise or descend and trend towards the proper proportion of an expectancy wave; When being between stationary phase, input signal is then only by the output impedance buffer, and at this moment, the output signal of turnover rate control circuit can be maintained at a high or low current potential.The standard (for example MIPI standard) that can meet thus, revolution rate and output impedance simultaneously.
Description of drawings
Fig. 1 shows the output-stage circuit of traditional MIPI conveyer (Tx);
Fig. 2 shows the block diagram of the turnover rate control circuit of the embodiment of the invention;
Each signal waveform of the turnover rate control circuit of Fig. 3 displayed map 2;
The circuit diagram of the turnover rate control circuit of Fig. 4 example embodiment of the invention;
Each signal waveform of the turnover rate control circuit of Fig. 5 displayed map 4.
Embodiment
Fig. 2 shows the block diagram of the turnover rate control circuit 20 of the embodiment of the invention, and Fig. 3 then shows each signal waveform of turnover rate control circuit 20.Though the input signal of present embodiment (in) is example with the square wave, yet other kind waveform (for example sinusoidal wave) is also applicable.Turnover rate control circuit 20 can make the output stage of circuit (for example low-power conveyer) can meet the standard of revolution rate and output impedance simultaneously.Though present embodiment is an example with mobile industry processor interface (MIPI) standard, it is a kind of high-speed, low-power sequence transceiver (transceiver) interface, so that the communication between the high-speed, low-power mobile device to be provided, yet, the present invention is also applicable to other transceiver, and is applicable to the output stage of general circuit.
In the present embodiment, turnover rate control circuit 20 comprises output impedance (R
Out) buffer 202, it meets the output impedance (R of MIPI standard
Out) requirement.Turnover rate control circuit 20 also comprises revolution rate buffer 204, and it meets revolution rate (SR) requirement of MIPI standard.Output impedance buffer 202 and revolution rate buffer 204 are in parallel each other, and its input is coupled in together with receiving inputted signal (in).The output SR addition of the output R of output impedance buffer 202 and revolution rate buffer 204 is as the output signal (out) of turnover rate control circuit 20.In the practice, the output of output impedance buffer 202 and the output of revolution rate buffer 204 can be coupled in together, can reach the addition function of output R and output SR, need not use real adder 206.
Turnover rate control circuit 20 also comprises edge finder 208, is used to survey rising edge and falling the transition of edge of input signal (in).In the present embodiment, edge finder 208 produces output impedance activation (enable) signal EN_R and revolution rate enable signal EN_SR according to the ascending, descending edge.Output impedance enable signal EN_R is used for activation and starts output impedance buffer 202, and revolution rate enable signal EN_SR is used for activation to start revolution rate buffer 204.As shown in Figure 3, when input signal (in) during in the transition of ascending, descending edge (for example between time t1 to t2), revolution rate enable signal EN_SR becomes work (active) or high potential in can be between one section given period.Length between this given period is the significant proportion (for example 80%) of selecting a period of time to be enough to allow output signal (out) rise or dropping to expectancy wave.As input signal (in) (for example between time t2 to t3) when stablizing, output impedance enable signal EN_R can become work (active) or high potential.When input signal (in) during in the transition of ascending, descending edge (for example between time t1 to t2), output impedance enable signal EN_R can or be inoperative (inactive) state for the state that works.In one embodiment, output impedance enable signal EN_R is the state (shown in the label in the accompanying drawing 30) that works forever.In another embodiment, only when revolution rate enable signal EN_SR was inoperative (inactive) state or electronegative potential, output impedance enable signal EN_R just can become work (active) or high potential (shown in the label in the accompanying drawing 32).
According to shown in Figure 3, when detecting (for example time t1) when rising edge, revolution rate buffer 204 worked signal EN_SR start, make input signal (in) mainly by revolution rate buffer 204, at this moment, the revolution rate that revolution rate buffer 204 is provided is much larger than output impedance buffer 202.In one embodiment, input signal (in) in time t1 simultaneously by revolution rate buffer 204 and output impedance buffer 202.In another embodiment, input signal (in) in time t1 only by revolution rate buffer 204.At this moment, the output SR of revolution rate buffer 204 can be drawn high (pull high), makes output signal (out) also and then be drawn high, and this increases its revolution rate, thereby is met the standard of MIPI.
Next, in time t2, signal EN_SR becomes inoperative, thereby closes revolution rate buffer 204, makes the output SR of revolution rate buffer 204 close or is high impedance (Hi-Z).At this moment, output signal (in) is only by output impedance buffer 202, and therefore, output signal (out) will be maintained at high potential, and its output impedance is enough big, and is met the standard of MIPI.
When detecting (for example time t3) when falling edge, revolution rate buffer 204 worked signal EN_SR start once more, make input signal (in) mainly by revolution rate buffer 204.At this moment, the output SR of revolution rate buffer 204 is dragged down (pull low), makes output signal (out) also and then be dragged down, and this increases its revolution rate, thereby is met the standard of MIPI.
Next, in time t4, signal EN_SR becomes inoperative once more, thereby closes revolution rate buffer 204, makes the output SR of revolution rate buffer 204 close or is high impedance (Hi-Z).At this moment, output signal (in) is only by output impedance buffer 202, and therefore, output signal (out) will be maintained at electronegative potential, and its output impedance is enough big, and is met the standard of MIPI.
According to the foregoing description, input signal (in) mainly can be by revolution rate buffer 204 in (for example between time t1 to t2) between rising/decrement phase, thereby can meet the standard of MIPI for the revolution rate.Next, input signal (in) only by output impedance buffer 202, thereby can meet the standard of MIPI for output impedance in (for example between time t2 to t3) between stationary phase.
The circuit diagram of the turnover rate control circuit 20A of Fig. 4 example embodiment of the invention, Fig. 5 then show each signal waveform of turnover rate control circuit 20A.In the present embodiment, turnover rate control circuit 20A comprises output impedance (R
Out) buffer 202A, it meets the output impedance (R of MIPI standard
Out) requirement.Output impedance buffer 202A comprises p transistor npn npn Rp and n transistor npn npn Rn, and it is series at positive supply V
DDWith negative supply V
SSBetween.Turnover rate control circuit 20A also comprises revolution rate buffer 204A, and it meets revolution rate (SR) requirement of MIPI standard.Revolution rate buffer 204A comprises p transistor npn npn SRp and n transistor npn npn SRn, and it is series at positive supply V
DDWith negative supply V
SSBetween.Output impedance buffer 202A and revolution rate buffer 204A are parallel with one another in positive supply V
DDWith negative supply V
SSBetween.The contact of the contact of transistor SRp and SRn and transistor Rp and Rn is coupled in together, as output signal (out).
Turnover rate control circuit 20A also comprises edge finder 208A, is used to survey rising edge and falling the transition of edge of input signal (in).In the present embodiment, edge finder 208A produces output impedance activation (enable) signal EN_R_H and EN_R_L (both are connected to transistor Rp and Rn respectively) and produces revolution rate enable signal EN_SR_H and EN_SR_L (both are connected to transistor SRp and SRn respectively) according to the ascending, descending edge.Output impedance enable signal EN_R_H, EN_R_L are used for activation jointly and start output impedance buffer 202A, and revolution rate enable signal EN_SR_H, EN_SR_L then are used for activation jointly and start revolution rate buffer 204A.
According to shown in Figure 5, when detecting (for example time t1) when rising edge, revolution rate buffer 204A is started by revolution rate enable signal EN_SR_H, the EN_SR_L of low (0) current potential, makes that output signal (out) is drawn high.In other words, input signal (in) is via revolution rate buffer 204A regenerate (regenerate).At this moment, output impedance buffer 202A is closed by output impedance enable signal EN_R_H (shown in the label in the accompanying drawing 50) of high (1) current potential and the signal EN_R_L of low (0) current potential.In another embodiment, output impedance buffer 202A is started by the output impedance enable signal EN_R_H (shown in the label in the accompanying drawing 52) and the EN_R_L of low (0) current potential.
Next, in time t2, revolution rate buffer 204A is closed by revolution rate enable signal EN_SR_H of high (1) current potential and the signal EN_SR_L of low (0) current potential, makes that revolution rate buffer 204A is high impedance (Hi-Z).At this moment, output impedance buffer 202A is started by the output impedance enable signal EN_R_H and the EN_R_L of low (0) current potential, thereby makes that output signal (out) continues to be drawn high.In other words, input signal (in) is via output impedance buffer 202A regenerate (regenerate).
When detecting (for example time t3) when falling edge, revolution rate buffer 204A is started once more by the revolution rate enable signal EN_SR_H and the signal EN_SR_L of high (1) current potential, makes output signal (out) be dragged down (pull low).At this moment, output impedance buffer 202A is closed by output impedance enable signal EN_R_H (shown in the label in the accompanying drawing 50) and low (0) current potential EN_R_L of high (1) current potential.In another embodiment, output impedance buffer 202A is started by the output impedance enable signal EN_R_H (shown in the label in the accompanying drawing 52) and the EN_R_L of low (0) current potential.
Next, in time t4, revolution rate buffer 204A is closed by revolution rate enable signal EN_SR_H of high (1) current potential and the signal EN_SR_L of low (0) current potential, makes that revolution rate buffer 204A is high impedance (Hi-Z).At this moment, output impedance buffer 202A is started by the output impedance enable signal EN_R_H and the EN_R_L of high (1) current potential, thereby makes that output signal (out) continues to be dragged down.
In the present embodiment, must avoid revolution rate buffer 204A to receive the revolution rate enable signal EN_SR_H of low (0) current potential and the signal EN_SR_L of height (1) current potential simultaneously, thereby cause V
DDWith V
SSBetween short circuit.In addition, also must avoid output impedance buffer 202A to receive the output impedance enable signal EN_R_H of low (0) current potential and the signal EN_R_L of height (1) current potential simultaneously, thereby cause V
DDWith V
SSBetween short circuit.
Following table one is done one with input signal (in), output signal (out), each enable signal, output impedance buffer 202A and revolution rate buffer 204A in the state of each time and is summed up.
Table one
| ??t1 | ??t2 | ??t3 | ??t4 | |
| ??in | Rise edge | High potential | Edge falls | Electronegative potential |
| ??R outBuffer | Close, Hi-Z or startup are drawn high | Start, draw high | Close, Hi-Z or startup drag down | Start, drag down |
| ??EN_R_H | ??1/0 | ??0 | ??1 | ??1 |
| ??EN_R_L | ??0/0 | ??0 | ??0 | ??1 |
| The SR buffer | Start, draw high | Close Hi-Z | Start, drag down | Close Hi-Z |
| ??EN_SR_H | ??0 | ??1 | ??1 | ??1 |
| ??EN_SR_L | ??0 | ??0 | ??1 | ??0 |
| ??out | Rise | High potential | Reduce | Electronegative potential |
According to the foregoing description, input signal (in) mainly can be by revolution rate buffer 204A in (for example between time t1 to t2) between rising/decrement phase, thereby can meet the standard of MIPI for the revolution rate.Next, input signal (in) only by output impedance buffer 202A, thereby can meet the standard of MIPI for output impedance in (for example between time t2 to t3) between stationary phase.
The above is the preferred embodiments of the present invention only, is not the scope that is used to limit claim of the present invention; All other do not break away from the equivalence of being finished under the spirit that invention discloses and changes or modify, and all should be included in the scope of following claim.
Claims (15)
1. turnover rate control circuit comprises:
The output impedance buffer;
Revolution rate buffer, in parallel with described output impedance buffer; And
Edge finder, it surveys input signal, is used to control described output impedance buffer and described revolution rate buffer;
Thus, when being between rising or decrement phase, described input signal is mainly by described revolution rate buffer; When being between stationary phase, described input signal is only by described output impedance buffer.
2. turnover rate control circuit as claimed in claim 1 is after the output addition of the output of wherein above-mentioned output impedance buffer and revolution rate buffer, as the output signal of described turnover rate control circuit.
3. turnover rate control circuit as claimed in claim 2, when be in rise or decrement phase between the time, the output signal of above-mentioned turnover rate control circuit can rise or descend and trend towards the proper proportion of expectancy wave; When being between stationary phase, the output signal of above-mentioned turnover rate control circuit can be maintained at high or low current potential.
4. turnover rate control circuit as claimed in claim 1, when being between rising or decrement phase, above-mentioned input signal is also by described output impedance buffer.
5. turnover rate control circuit as claimed in claim 1, wherein the output impedance of above-mentioned turnover rate control circuit and revolution rate meet mobile industry processor interface specification.
6. turnover rate control circuit as claimed in claim 1, the output impedance of wherein above-mentioned output impedance buffer are greater than the output impedance of described revolution rate buffer, and the revolution rate of described revolution rate buffer is greater than the revolution rate of described output impedance buffer.
7. turnover rate control circuit as claimed in claim 1, wherein above-mentioned edge finder is according to the ascending, descending edge transition of described input signal, produce at least one output impedance enable signal starting described output impedance buffer, and produce at least one revolution rate enable signal to start described revolution rate buffer.
8. turnover rate control circuit as claimed in claim 7, when being between stationary phase, above-mentioned output impedance enable signal starts described output impedance buffer; When being between rising or decrement phase, above-mentioned revolution rate enable signal starts described revolution rate buffer, and above-mentioned output impedance enable signal also starts described output impedance buffer.
9. turnover rate control circuit comprises:
The output impedance buffer, it comprises p transistor npn npn and n transistor npn npn, and it is series between positive supply and the negative supply;
Revolution rate buffer, in parallel with described output impedance buffer, described revolution rate buffer comprises p transistor npn npn and n transistor npn npn, and it is series between described positive supply and the described negative supply; And
Edge finder, it surveys input signal, is used to control described output impedance buffer and described revolution rate buffer;
Thus, when being between rising or decrement phase, described input signal is regenerated by described revolution rate buffer; When being between stationary phase, described input signal is only regenerated by described output impedance buffer.
10. turnover rate control circuit as claimed in claim 9, when be in rise or decrement phase between the time, the output signal of above-mentioned turnover rate control circuit can be drawn high or be dragged down and be trended towards the proper proportion of expectancy wave; When being between stationary phase, the output signal of above-mentioned turnover rate control circuit can be maintained at high or low current potential.
11. turnover rate control circuit as claimed in claim 9, when being between rising or decrement phase, above-mentioned input signal is also regenerated by described output impedance buffer.
12. turnover rate control circuit as claimed in claim 9, wherein the output impedance of above-mentioned turnover rate control circuit and revolution rate meet mobile industry processor interface specification.
13. turnover rate control circuit as claimed in claim 9, the output impedance of wherein above-mentioned output impedance buffer are greater than the output impedance of described revolution rate buffer, and the revolution rate of described revolution rate buffer is greater than the revolution rate of described output impedance buffer.
14. turnover rate control circuit as claimed in claim 9, wherein above-mentioned edge finder produces p transistor npn npn and the n transistor npn npn of at least two output impedance enable signals to start described output impedance buffer respectively according to the ascending, descending edge transition of described input signal; And produce p transistor npn npn and the n transistor npn npn of two-revolution rate enable signal to start described revolution rate buffer respectively at least.
15. turnover rate control circuit as claimed in claim 14, when being between stationary phase, above-mentioned output impedance enable signal starts described output impedance buffer; When being between rising or decrement phase, above-mentioned revolution rate enable signal starts described revolution rate buffer, and above-mentioned output impedance enable signal also starts described output impedance buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100027111A CN101783671B (en) | 2009-01-19 | 2009-01-19 | Turnover rate control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100027111A CN101783671B (en) | 2009-01-19 | 2009-01-19 | Turnover rate control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101783671A true CN101783671A (en) | 2010-07-21 |
| CN101783671B CN101783671B (en) | 2012-05-30 |
Family
ID=42523511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100027111A Expired - Fee Related CN101783671B (en) | 2009-01-19 | 2009-01-19 | Turnover rate control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101783671B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109839982A (en) * | 2017-11-27 | 2019-06-04 | 瑞昱半导体股份有限公司 | The transceiver circuit of adjustable revolution rate |
-
2009
- 2009-01-19 CN CN2009100027111A patent/CN101783671B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109839982A (en) * | 2017-11-27 | 2019-06-04 | 瑞昱半导体股份有限公司 | The transceiver circuit of adjustable revolution rate |
| CN109839982B (en) * | 2017-11-27 | 2020-04-28 | 瑞昱半导体股份有限公司 | Transceiver circuit with adjustable slew rate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101783671B (en) | 2012-05-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3734430B1 (en) | Method for copying multiple text segments and mobile terminal | |
| CN104142789A (en) | Content selection method, content selection device and terminal | |
| EP2869191A1 (en) | Window displaying method of mobile terminal and mobile terminal | |
| CN108470571B (en) | Audio detection method and device and storage medium | |
| CN103823626B (en) | Method and device for regulating display contents and electronic equipment | |
| CN103543913A (en) | Terminal device operation method and device, and terminal device | |
| CN104657105A (en) | Method and device for starting voice input function of terminal | |
| US20220086114A1 (en) | Message sending method and terminal | |
| CN104156406A (en) | Method and device for displaying embedded pages of application programs | |
| CN103677564A (en) | Sliding operation response method and device and terminal equipment | |
| CN103683437A (en) | Charger and terminal equipment | |
| US20190191296A1 (en) | Method for Data Migration and Terminal | |
| CN103631502A (en) | Display content adjusting method and device and electronic equipment | |
| CN105245432B (en) | Unread message counting method and device and terminal | |
| CN106657641A (en) | Method and device for optimizing sharing mode and mobile terminal | |
| CN108009116B (en) | MicroUSB interface circuit and mobile terminal thereof | |
| US10101894B2 (en) | Information input user interface | |
| US20130009920A1 (en) | Image display method and apparatus | |
| CN101783671B (en) | Turnover rate control circuit | |
| US10176123B2 (en) | Communication method and mobile terminal | |
| CN110225106B (en) | Data transmission method, device and storage medium | |
| WO2022127790A1 (en) | Channel configuration method and apparatus, electronic device, and readable storage medium | |
| CN106933975A (en) | A kind of display methods of media file, device and mobile terminal | |
| WO2018210082A1 (en) | Data transmission method, data loading device, data analyzing device, and data transmission system | |
| US7772901B2 (en) | Slew rate control circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120530 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |