CN110350778B - Negative voltage generator and negative voltage detector thereof - Google Patents
Negative voltage generator and negative voltage detector thereof Download PDFInfo
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- CN110350778B CN110350778B CN201810889125.2A CN201810889125A CN110350778B CN 110350778 B CN110350778 B CN 110350778B CN 201810889125 A CN201810889125 A CN 201810889125A CN 110350778 B CN110350778 B CN 110350778B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B11/00—Measuring arrangements characterised by the use of optical techniques
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- G—PHYSICS
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B27/00—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
- G02B27/28—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00 for polarising
- G02B27/281—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00 for polarising used for attenuating light intensity, e.g. comprising rotatable polarising elements
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B5/00—Optical elements other than lenses
- G02B5/30—Polarising elements
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B5/00—Optical elements other than lenses
- G02B5/30—Polarising elements
- G02B5/3083—Birefringent or phase retarding elements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/10—Image acquisition
- G06V10/12—Details of acquisition arrangements; Constructional details thereof
- G06V10/14—Optical characteristics of the device performing the acquisition or on the illumination arrangements
- G06V10/147—Details of sensors, e.g. sensor lenses
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- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
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- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/071—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate a negative voltage output from a positive voltage source
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Abstract
The invention provides a negative voltage generator and a negative voltage detector thereof. The negative voltage generator is used for providing a negative reference voltage. The negative voltage generator includes a negative voltage detector and a voltage pump circuit. The negative voltage detector includes a first circuit, a second circuit, and a comparison circuit. The first circuit is used for receiving a negative reference voltage and generating a first voltage according to the negative reference voltage. The second circuit is used for generating a second voltage. The comparison circuit is coupled to the first circuit to receive the first voltage, coupled to the second circuit to receive the second voltage, and configured to compare the first voltage and the second voltage to generate the control signal. The voltage pump circuit is coupled to the negative voltage detector to receive the control signal and generate a negative reference voltage according to the control signal.
Description
Technical Field
The present invention relates to a voltage generator, and more particularly, to a negative voltage generator and a negative voltage detector thereof.
Background
A common negative voltage generator first generates a positive set voltage, and then converts the positive set voltage into a negative reference voltage through a negative pump circuit thereof to provide a negative reference voltage at an output terminal thereof, wherein an absolute voltage value of the negative reference voltage is equal to a voltage value of the set voltage. However, the settling time (settling time) of the negative reference voltage generated by the negative voltage generator is long. In addition, even after the settling time, a spike current (spike current) still exists in the negative voltage generator.
Disclosure of Invention
Accordingly, the present invention provides a negative voltage generator and a negative voltage detector thereof, which can reduce the settling time of a negative reference voltage to rapidly provide a stable negative reference voltage, and after the negative reference voltage reaches a set value, there is no inrush current in the negative voltage generator.
The negative voltage generator of the invention is used for providing a negative reference voltage. The negative voltage generator includes a negative voltage detector and a voltage pump circuit. The negative voltage detector includes a first circuit, a second circuit, and a comparison circuit. The first circuit is used for receiving a negative reference voltage and generating a first voltage according to the negative reference voltage. The second circuit is used for generating a second voltage. The comparison circuit is coupled to the first circuit to receive the first voltage, coupled to the second circuit to receive the second voltage, and configured to compare the first voltage and the second voltage to generate the control signal. The voltage pump circuit is coupled to the negative voltage detector to receive the control signal and generate a negative reference voltage according to the control signal.
In an embodiment of the invention, the first circuit includes a first P-type transistor, a first resistor, and a first current source. The first end of the first P-type transistor is coupled to a grounding voltage, and the control end of the first P-type transistor receives a negative reference voltage. The first end of the first resistor is coupled to the second end of the first P-type transistor. The first current source is coupled to the second end of the first resistor to provide a first voltage. The second circuit includes a second P-type transistor and a second current source. The first terminal and the control terminal of the second P-type transistor are coupled to a ground voltage, and the second terminal of the second P-type transistor provides a second voltage. The second current source is coupled to the second end of the second P-type transistor.
In an embodiment of the invention, the body of the first P-type transistor is coupled to the second end of the first resistor. The second circuit also includes a second resistor. The first end of the second resistor is coupled to the second end of the second P-type transistor, and the second end of the second resistor is coupled to the second current source and the substrate of the second P-type transistor.
In an embodiment of the invention, the second circuit further comprises a third resistor. The first terminal of the third resistor is coupled to the ground voltage, and the second terminal of the third resistor is coupled to the first terminal of the second P-type transistor.
In an embodiment of the invention, when the first voltage is greater than the second voltage, the comparison circuit generates the control signal to enable the voltage pump circuit, so that the voltage pump circuit increases the absolute value of the negative reference voltage according to the power voltage.
In an embodiment of the invention, when the first voltage is equal to the second voltage, the comparison circuit generates a control signal to disable the voltage pump circuit, so that the voltage pump circuit maintains the voltage absolute value of the negative reference voltage at a set voltage value, wherein the set voltage value is smaller than the voltage absolute value of the power voltage.
In an embodiment of the invention, the voltage pump circuit includes a clock signal generating circuit and a negative pump circuit. The clock signal generating circuit is used for generating a clock signal group according to the control signal. The negative pump circuit is coupled to the clock signal generating circuit to receive the clock signal group and generate a negative reference voltage according to the clock signal group and the power voltage, wherein the voltage absolute value of the negative reference voltage is smaller than the voltage absolute value of the power voltage.
The negative voltage detector of the invention is used for detecting the negative reference voltage. The negative voltage detector includes a first circuit, a second circuit, and a comparison circuit. The first circuit is used for receiving a negative reference voltage and generating a first voltage according to the negative reference voltage. The second circuit is used for generating a second voltage. The comparison circuit is coupled to the first circuit to receive the first voltage, coupled to the second circuit to receive the second voltage, and compares the first voltage and the second voltage to determine whether the absolute value of the negative reference voltage is equal to the predetermined voltage value.
Based on the above, the negative voltage generator according to the embodiment of the invention generates the negative reference voltage by using the power supply voltage, and the voltage absolute value of the negative reference voltage can quickly reach the set voltage value based on the fact that the voltage absolute value of the power supply voltage is greater than the voltage absolute value of the negative reference voltage. In addition, the negative voltage detector of the embodiment of the present invention does not obtain current from the negative reference voltage. Therefore, after the absolute value of the negative reference voltage reaches the set voltage value, the voltage pump circuit in the negative voltage generator can stop the pump operation to avoid generating the surge current, and the absolute value of the negative reference voltage can still be maintained at the set voltage value.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a block diagram of a negative voltage generator according to an embodiment of the invention.
FIG. 2 is a block diagram of a voltage pump circuit according to an embodiment of the present invention.
Fig. 3 is a schematic circuit diagram of a negative pump circuit according to an embodiment of the invention.
FIG. 4 is a signal waveform diagram of a clock signal group according to an embodiment of the present invention.
Fig. 5A is a circuit diagram illustrating a first circuit and a second circuit of a negative voltage detector according to an embodiment of the invention.
Fig. 5B is a circuit diagram illustrating a first circuit and a second circuit of a negative voltage detector according to another embodiment of the invention.
Fig. 5C is a circuit diagram illustrating a first circuit and a second circuit of a negative voltage detector according to another embodiment of the invention.
Fig. 5D is a circuit diagram illustrating a first circuit and a second circuit of a negative voltage detector according to another embodiment of the invention.
[ notation ] to show
100: negative voltage generator
120: negative voltage detector
121. 521A, 521B, 521C, 521D: first circuit
122. 522A, 522B, 522C, 522D: second circuit
123: comparison circuit
140: voltage pump circuit
142: clock signal generating circuit
144: negative pump circuit
C1, CL: capacitor with a capacitor element
CS: control signal
GND: ground voltage
I1, I2: current source
M1, M2: p-type transistor
NVref: negative reference voltage
R1, R2, R3: resistor with a resistor element
S _ PH: clock signal group
S _ PH1, S _ PH 2: clock signal
SW 1-SW 4: switch with a switch body
TP1, TP 2: time interval
V1: first voltage
V2: second voltage
VDD: supply voltage
VR 3: over pressure
Vsg: voltage difference
Vset: set voltage value
Detailed Description
In order that the present disclosure may be more readily understood, the following specific examples are given as illustrative of the invention which may be practiced in various ways. Further, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1 is a block diagram of a negative voltage generator according to an embodiment of the invention. Referring to fig. 1, the negative voltage generator 100 is used for providing a negative reference voltage NVref, i.e., the voltage of the negative reference voltage NVref is lower than zero volts. The negative voltage generator 100 includes a negative voltage detector 120 and a voltage pump circuit 140. The negative voltage detector 120 may include a first circuit 121, a second circuit 122, and a comparison circuit 123, but the present invention is not limited thereto. The first circuit 121 is configured to receive a negative reference voltage NVref and generate a first voltage V1 according to the negative reference voltage NVref. The second circuit 122 is used for generating a second voltage V2. The comparison circuit 123 is coupled to the first circuit 121 to receive the first voltage V1, and coupled to the second circuit 122 to receive the second voltage V2. The comparison circuit 123 compares the first voltage V1 and the second voltage V2 to determine whether the absolute value of the negative reference voltage NVref is equal to the set voltage Vset, and accordingly generates a control signal CS. The voltage pump circuit 140 is coupled to the negative voltage detector 120 to receive the control signal CS and generate the negative reference voltage NVref according to the control signal CS.
In an embodiment of the invention, when the first voltage V1 is greater than the second voltage V2, the comparison circuit 123 determines that the absolute value of the negative reference voltage NVref is less than the set voltage Vset, so the comparison circuit 123 can generate the control signal CS of a first level (e.g., a logic high level) to enable the voltage pump circuit 140, so that the voltage pump circuit 140 performs a pumping operation according to the power voltage VDD to increase the absolute value of the negative reference voltage NVref by an increment, wherein the power voltage VDD is a positive voltage, and the set voltage Vset is less than the voltage of the power voltage VDD. On the other hand, when the first voltage V1 is equal to the second voltage V2, the comparison circuit 123 determines that the absolute value of the negative reference voltage NVref is equal to the set voltage Vset, so the comparison circuit 123 can generate the control signal CS at a second level (e.g., a logic low level) to disable the voltage pump circuit 140, so that the voltage pump circuit 140 stops pumping to maintain the absolute value of the negative reference voltage NVref at the set voltage Vset, wherein the first level is complementary to the second level. It is understood that the voltage absolute value of the negative reference voltage NVref is smaller than the voltage value of the power supply voltage VDD.
Incidentally, the relationship between the logic high level and the logic low level of the control signal CS and the enabling or disabling of the voltage pump circuit 140 is only an example. As is well known in the art, the relationship between the logic level of the control signal CS and the enabling or disabling of the voltage pump circuit 140 can be defined by the designer according to the actual requirement.
FIG. 2 is a block diagram of a voltage pump circuit according to an embodiment of the present invention. Referring to fig. 2, the voltage pump circuit 140 may include a clock signal generating circuit 142 and a negative pump circuit 144, but the invention is not limited thereto. The clock signal generating circuit 142 can generate the clock signal set S _ PH according to the control signal CS. The negative pump circuit 144 is coupled to the clock signal generating circuit 142 for receiving the clock signal set S _ PH and generating the negative reference voltage NVref according to the clock signal set S _ PH and the power voltage VDD.
In an embodiment of the present invention, the clock signal generating circuit 142 can be implemented by a conventional clock signal generating circuit. In an embodiment of the present invention, the negative pump circuit 144 can be implemented by a two-phase negative pump circuit as shown in fig. 3. Referring to fig. 2 and 3, the negative pump circuit 144 may include capacitors C1 and CL and switches SW1 SW4, but the invention is not limited thereto. A first terminal of the switch SW1 is coupled to the supply voltage VDD. A second terminal of the switch SW1 is coupled to a first terminal of a capacitor C1. The first terminal of the switch SW2 is coupled to the ground voltage GND. A second terminal of the switch SW2 is coupled to a second terminal of the capacitor C1. A first terminal of the switch SW3 is coupled to a first terminal of the capacitor C1. The second terminal of the switch SW3 is coupled to the ground voltage GND. A first terminal of the switch SW4 is coupled to a second terminal of the capacitor C1. The first terminal of the capacitor CL is coupled to the ground voltage GND. A second terminal of the capacitor CL is coupled to a second terminal of the switch SW4 to provide the negative reference voltage NVref. In addition, the clock signal set S _ PH (shown in fig. 2) may include, for example, the clock signals S _ PH1 and S _ PH2 shown in fig. 4, wherein a time interval in which the clock signal S _ PH1 is at a logic high level does not overlap a time interval in which the clock signal S _ PH2 is at a logic high level, the switches SW1 and SW2 shown in fig. 3 are controlled by the clock signal S _ PH1, and the switches SW3 and SW4 are controlled by the clock signal S _ PH2, but the invention is not limited thereto. In another embodiment of the present invention, the switches SW1 and SW2 can be controlled by the clock signal S _ PH2, and the switches SW3 and SW4 can be controlled by the clock signal S _ PH 1.
Referring to fig. 3 and 4, it is assumed that switches SW1 and SW2 are turned on in response to a logic high clock signal S _ PH1, switches SW1 and SW2 are turned off in response to a logic low clock signal S _ PH1, switches SW3 and SW4 are turned on in response to a logic high clock signal S _ PH2, and switches SW3 and SW4 are turned off in response to a logic low clock signal S _ PH 2. Therefore, during the time interval TP1 shown in FIG. 4, switches SW1 and SW2 are turned on and switches SW3 and SW4 are turned off, so that the power voltage VDD charges the capacitor C1. Then, during the time interval TP2 shown in fig. 4, switches SW1 and SW2 are turned off and switches SW3 and SW4 are turned on, so that capacitor C1 transfers the stored charge to capacitor CL (i.e., capacitor C1 charges capacitor CL) to decrease the negative reference voltage NVref (i.e., increase the absolute voltage of the negative reference voltage NVref). By repeatedly switching the logic level of the clock signal S _ PH1 and the logic level of the clock signal S _ PH2, the capacitor C1 is repeatedly charged and the capacitor CL is charged to gradually decrease the negative reference voltage NVref (i.e., gradually increase the absolute voltage of the negative reference voltage NVref) until the absolute voltage of the negative reference voltage NVref is equal to the set voltage Vset.
Since the voltage value of the power voltage VDD is greater than the set voltage value Vset, compared to the conventional method of charging the capacitor C1 with a voltage source having the set voltage value Vset, the present embodiment of charging the capacitor C1 with the power voltage VDD can effectively increase the amount of charge stored in the capacitor C1 and the amount of charge transferred from the capacitor C1 to the capacitor CL, so as to increase the falling speed of the negative reference voltage NVref (i.e., increase the rising speed of the absolute voltage of the negative reference voltage NVref), thereby reducing the settling time of the negative reference voltage NVref. In addition, after the absolute value of the negative reference voltage NVref is equal to the set voltage Vset, the clock signal generating circuit 142 of fig. 2 stops switching the logic level of the clock signal S _ PH1 and the logic level of the clock signal S _ PH2 (i.e., the logic levels of the clock signals S _ PH1 and S _ PH2 will not transition) in response to the control signal CS, so that the negative pump circuit 144 stops pumping (described in detail later). Therefore, the surge current generated by the on-off switching of the switches SW 1-SW 4 can be avoided.
Fig. 5A is a circuit diagram illustrating a first circuit and a second circuit of a negative voltage detector according to an embodiment of the invention. Referring to fig. 5A, the first circuit 521A may include a P-type transistor M1, a resistor R1, and a current source I1. The first terminal of the P-type transistor M1 is coupled to the ground voltage GND. The control terminal of the P-type transistor M1 receives the negative reference voltage NVref. A first terminal of the resistor R1 is coupled to a second terminal of the P-type transistor M1. The current source I1 is coupled to the second terminal of the resistor R1 to provide the first voltage V1. The second circuit 522A includes a P-type transistor M2 and a current source I2. The first terminal and the control terminal of the P-type transistor M2 are coupled to the ground voltage GND. The second terminal of the P-type transistor M2 provides a second voltage V2. The current source I2 is coupled to the second terminal of the P-type transistor M2.
In an embodiment of the invention, the P-type transistors M1 and M2 may be P-type mosfets of the same size, and thus the first voltage V1 and the second voltage V2 may be represented by formulas (1) and (2), respectively, where Vref is the absolute value of the negative reference voltage NVref, Vsg is the voltage difference between the second terminal and the control terminal of the P-type transistor M1 (or the P-type transistor PM2), I is the output current value of the current source I1, and R is the resistance value of the resistor R1.
V1 ═ Vref + Vsg + Vset ═ Vref + Vsg + I × R formula (1)
Vsg formula (2) ═ V2
When the absolute voltage Vref of the negative reference voltage NVref is equal to the set voltage
Since the first voltage V1 is equal to the second voltage V2 when Vset (i.e., I × R) is detected, it can be determined whether the absolute value Vref of the negative reference voltage NVref is equal to the set voltage Vset according to the comparison result between the first voltage V1 and the second voltage V2. The set voltage value Vset can be adjusted by adjusting the resistance value R of the resistor R1.
Please refer to fig. 3 and fig. 5A together. It should be noted that since the negative reference voltage NVref is coupled to the control terminal of the P-type transistor M1 (i.e., the gate terminal of the pmos), no current flows from the capacitor CL of fig. 3 to the P-type transistor M1 of fig. 5A. In other words, the negative voltage detector of the embodiment of fig. 5A does not draw current from the capacitor CL of fig. 3. Therefore, after the absolute value Vref of the negative reference voltage NVref is equal to the set voltage value Vset, the absolute value Vref of the negative reference voltage NVref can be maintained at the set voltage value Vset even though the pump circuit 144 of fig. 3 stops the pumping operation.
It should be noted that in fig. 5A, the voltage at the second terminal of the P-type transistor M1 (Vref + Vsg) must be greater than the voltage at the first terminal of the P-type transistor M1 (ground voltage GND), so that the absolute value Vref of the negative reference voltage NVref must be less than the voltage difference Vsg. Therefore, in other embodiments of the present invention, the threshold voltage (threshold voltage) of the P-type transistors M1 and M2 can be increased by increasing the body effect (body effect) of the P-type transistors M1 and M2, so as to increase the upper limit of the absolute voltage value Vref of the voltage difference Vsg and the negative reference voltage NVref.
Fig. 5B is a circuit diagram illustrating a first circuit and a second circuit of a negative voltage detector according to another embodiment of the invention. Referring to fig. 5A and 5B, the first circuit 521B of fig. 5B is similar to the first circuit 521A of fig. 5A, and the difference therebetween is: the body of the P-type transistor M1 of the first circuit 521B is coupled to the second terminal of the resistor R1 to increase the body effect of the P-type transistor M1 of the first circuit 521B to raise the threshold voltage of the P-type transistor M1, thereby raising the upper limit of the absolute value of the negative reference voltage NVref. In addition, the second circuit 522B of fig. 5B is similar to the second circuit 522A of fig. 5A, with the only difference being: the second circuit 522B also includes a resistor R2.
In detail, as shown in fig. 5B, a first terminal of the resistor R2 is coupled to the second terminal of the P-type transistor M2, and a second terminal of the resistor R2 is coupled to the current source I2, wherein the body of the P-type transistor M2 is coupled to the second terminal of the resistor R2 to increase the body effect of the P-type transistor M2. By increasing the body effect of the P-type transistor M2 of the second circuit 522B, the threshold voltage of the P-type transistor M2 of the second circuit 522B may be correspondingly increased, such that the characteristics of the P-type transistor M2 of the second circuit 522B match the characteristics of the P-type transistor M1 of the first circuit 521B.
Referring to FIG. 5A again, the voltage difference between the second terminal and the first terminal of the P-type transistor M1 is-Vref + Vsg, and the voltage difference between the second terminal and the first terminal of the P-type transistor M2 is Vsg. Since the voltage difference between the second terminal and the first terminal of the P-type transistor M1 is not equal to the voltage difference between the second terminal and the first terminal of the P-type transistor M2, the characteristics of the P-type transistors M1 and M2 are mismatched.
Fig. 5C is a circuit diagram illustrating a first circuit and a second circuit of a negative voltage detector according to another embodiment of the invention. Referring to fig. 5A and fig. 5C together, the first circuit 521C of fig. 5C is similar to the first circuit 521A of fig. 5A, so that the related description above can be referred to, and is not repeated herein. In addition, the second circuit 522C of fig. 5C is similar to the second circuit 522A of fig. 5A, with the only difference being: the second circuit 522C also includes a resistor R3.
In detail, as shown in fig. 5C, a first end of the resistor R3 is coupled to the ground voltage GND. A second terminal of the resistor R3 is coupled to a first terminal of a P-type transistor M2. Since the first terminal of the P-type transistor M2 of the second circuit 522C is coupled to the ground voltage GND through the resistor R3, the voltage of the first terminal of the P-type transistor M2 of the second circuit 522C is the voltage VR3 across the resistor R3, and the voltage difference between the second terminal and the first terminal of the P-type transistor M2 of the second circuit 522C is Vsg-VR 3. In addition, the voltage difference between the second terminal and the first terminal of the P-type transistor M1 of the second circuit 521C is-Vref + Vsg, so that the voltage difference between the second terminal and the first terminal of the P-type transistor M1 is equal to the voltage absolute value Vref of the negative reference voltage NVref by adjusting the resistance of the resistor R3, and the characteristics of the P-type transistors M1 and M2 are matched.
Similarly, the design of resistor R3 in the second circuit 522C of FIG. 5C may also be used in the second circuit 522B of FIG. 5B, as shown in the second circuit 522D of FIG. 5D. The details and operation of the second circuit 522D can refer to the related descriptions above, and are not described herein again. In addition, the first circuit 521D of fig. 5D is similar to the first circuit 521B of fig. 5B, so that the related description can be referred to and will not be repeated herein.
In summary, the negative voltage generator according to the embodiment of the invention charges the capacitor with the power voltage to generate and provide the negative reference voltage, and the voltage absolute value of the negative reference voltage can rapidly reach the set voltage value based on the fact that the voltage absolute value of the power voltage is greater than the voltage absolute value of the negative reference voltage. In addition, the negative voltage detector of the embodiment of the present invention does not draw current from the capacitor. Therefore, after the absolute value of the negative reference voltage reaches the set voltage value, the voltage pump circuit in the negative voltage generator can stop the pump operation to avoid generating the surge current, and the absolute value of the negative reference voltage can still be maintained at the set voltage value.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (15)
1. A negative voltage generator for providing a negative reference voltage, the negative voltage generator comprising:
a negative voltage detector, comprising:
a first circuit comprising a first P-type transistor, a first terminal of the first P-type transistor being coupled to a ground voltage, and a control terminal of the first P-type transistor receiving the negative reference voltage, wherein the first circuit generates a first voltage at a second terminal of the first P-type transistor according to the negative reference voltage;
a second circuit for generating a second voltage; and
a comparison circuit coupled to the first circuit to receive the first voltage, coupled to the second circuit to receive the second voltage, and comparing the first voltage and the second voltage to generate a control signal; and
the voltage pump circuit is coupled with the negative voltage detector to receive the control signal and generates the negative reference voltage according to the control signal.
2. The negative voltage generator of claim 1:
wherein the first circuit further comprises:
a first resistor having a first end coupled to the second end of the first P-type transistor; and
a first current source coupled to a second terminal of the first resistor to provide the first voltage,
wherein the second circuit comprises:
a second P-type transistor, a first terminal of the second P-type transistor and a control terminal of the second P-type transistor being coupled to the ground voltage, and a second terminal of the second P-type transistor providing the second voltage; and
a second current source coupled to the second terminal of the second P-type transistor.
3. The negative voltage generator of claim 2, wherein a body of the first P-type transistor is coupled to the second end of the first resistor, and the second circuit further comprises:
a second resistor having a first end coupled to the second end of the second P-type transistor and a second end coupled to the second current source and a body of the second P-type transistor.
4. The negative voltage generator of claim 3, wherein the second circuit further comprises:
a third resistor, a first end of the third resistor coupled to the ground voltage, and a second end of the third resistor coupled to the first end of the second P-type transistor.
5. The negative voltage generator of claim 2, wherein the second circuit further comprises:
a second resistor having a first end coupled to the ground voltage and a second end coupled to the first end of the second P-type transistor.
6. The negative voltage generator of claim 1, wherein when the first voltage is greater than the second voltage, the comparison circuit generates the control signal to enable the voltage pump circuit to cause the voltage pump circuit to increment a voltage absolute value of the negative reference voltage according to a supply voltage.
7. The negative voltage generator of claim 6, wherein when the first voltage is equal to the second voltage, the comparison circuit generates the control signal to disable the voltage pump circuit to cause the voltage pump circuit to maintain a voltage absolute value of the negative reference voltage at a set voltage value, wherein the set voltage value is less than a voltage absolute value of the supply voltage.
8. The negative voltage generator of claim 1, wherein the voltage pump circuit comprises:
a clock signal generating circuit for generating a clock signal group according to the control signal; and
the negative pump circuit is coupled with the clock signal generating circuit to receive the clock signal group and generates the negative reference voltage according to the clock signal group and the power voltage, wherein the voltage absolute value of the negative reference voltage is smaller than that of the power voltage.
9. The negative voltage generator of claim 8, wherein the set of clock signals is a two-phase clock signal, and the negative pump circuit comprises:
a first capacitor;
a first switch having a first terminal coupled to the supply voltage and a second terminal coupled to a first terminal of the first capacitor;
a second switch, a first terminal of the second switch being coupled to the ground voltage, and a second terminal of the second switch being coupled to a second terminal of the first capacitor;
a third switch having a first terminal coupled to the first terminal of the first capacitor and a second terminal coupled to the ground voltage;
a fourth switch having a first terminal coupled to the second terminal of the first capacitor; and
an output capacitor having a first terminal coupled to the ground voltage and a second terminal coupled to a second terminal of the fourth switch to provide the negative reference voltage,
the first switch and the second switch are controlled by one of the two phase clock signals, and the third switch and the fourth switch are controlled by the other of the two phase clock signals.
10. A negative voltage detector for detecting a negative reference voltage, the negative voltage detector comprising:
a first circuit comprising a first P-type transistor, a first terminal of the first P-type transistor being coupled to a ground voltage, and a control terminal of the first P-type transistor receiving the negative reference voltage, wherein the first circuit generates a first voltage at a second terminal of the first P-type transistor according to the negative reference voltage;
a second circuit for generating a second voltage; and
the comparison circuit is coupled to the first circuit to receive the first voltage, coupled to the second circuit to receive the second voltage, and configured to compare the first voltage and the second voltage to determine whether the absolute value of the negative reference voltage is equal to a predetermined voltage value.
11. The negative voltage detector of claim 10:
wherein the first circuit further comprises:
a first resistor having a first end coupled to the second end of the first P-type transistor; and
a first current source coupled to a second terminal of the first resistor to provide the first voltage,
wherein the second circuit comprises:
a second P-type transistor, a first terminal of the second P-type transistor and a control terminal of the second P-type transistor being coupled to the ground voltage, and a second terminal of the second P-type transistor providing the second voltage; and
a second current source coupled to the second terminal of the second P-type transistor.
12. The negative voltage detector of claim 11, wherein a body of the first P-type transistor is coupled to the second end of the first resistor, and the second circuit further comprises:
a second resistor having a first end coupled to the second end of the second P-type transistor and a second end coupled to the second current source and a body of the second P-type transistor.
13. The negative voltage detector of claim 12, wherein the second circuit further comprises:
a third resistor, a first end of the third resistor coupled to the ground voltage, and a second end of the third resistor coupled to the first end of the second P-type transistor.
14. The negative voltage detector of claim 11, wherein the second circuit further comprises:
a second resistor having a first end coupled to the ground voltage and a second end coupled to the first end of the second P-type transistor.
15. The negative voltage detector of claim 10, wherein the comparison circuit generates a control signal at a first level when the first voltage is greater than the second voltage; the comparison circuit generates the control signal at a second level when the first voltage is equal to the second voltage, wherein the first level is complementary to the second level.
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|---|---|---|---|
| US201862651205P | 2018-04-01 | 2018-04-01 | |
| US62/651,205 | 2018-04-01 |
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| CN110350778A CN110350778A (en) | 2019-10-18 |
| CN110350778B true CN110350778B (en) | 2020-08-11 |
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| CN201821107808.XU Expired - Fee Related CN208477552U (en) | 2018-04-01 | 2018-07-13 | Optical recognition module |
| CN201810889125.2A Active CN110350778B (en) | 2018-04-01 | 2018-08-07 | Negative voltage generator and negative voltage detector thereof |
| CN201811124339.7A Pending CN110345864A (en) | 2018-04-01 | 2018-09-26 | Three-dimensional sensing module |
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| CN201810767443.1A Withdrawn CN110348432A (en) | 2018-04-01 | 2018-07-13 | Optical recognition module |
| CN201821107808.XU Expired - Fee Related CN208477552U (en) | 2018-04-01 | 2018-07-13 | Optical recognition module |
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| CN201811124339.7A Pending CN110345864A (en) | 2018-04-01 | 2018-09-26 | Three-dimensional sensing module |
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| TW (4) | TW201942604A (en) |
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| TWI739431B (en) * | 2019-12-09 | 2021-09-11 | 大陸商廣州印芯半導體技術有限公司 | Data transmission system and data transmission method thereof |
| TWI730540B (en) * | 2019-12-11 | 2021-06-11 | 精準基因生物科技股份有限公司 | A time-of-flight sensing system and light emitter thereof |
| CN113126104A (en) * | 2019-12-27 | 2021-07-16 | 精准基因生物科技股份有限公司 | Time-of-flight polarization light sensing system and light emitter thereof |
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| TWI706616B (en) * | 2020-02-12 | 2020-10-01 | 新唐科技股份有限公司 | Glitch detection circuit |
| CN112306143B (en) * | 2020-11-16 | 2022-05-13 | 江苏万邦微电子有限公司 | Simple negative voltage reference circuit |
| TWI780921B (en) * | 2020-11-19 | 2022-10-11 | 仁寶電腦工業股份有限公司 | Notebook computer |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI741206B (en) | 2021-10-01 |
| CN110350778A (en) | 2019-10-18 |
| TW201942604A (en) | 2019-11-01 |
| TWI693373B (en) | 2020-05-11 |
| CN110348432A (en) | 2019-10-18 |
| TW201942611A (en) | 2019-11-01 |
| CN110345864A (en) | 2019-10-18 |
| TWI695247B (en) | 2020-06-01 |
| TW201945881A (en) | 2019-12-01 |
| CN208477552U (en) | 2019-02-05 |
| TW201942541A (en) | 2019-11-01 |
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