1278170 九、發明說明： 【發明所屬之技術領域】 本發明提供一^種具有負電壓穩壓電路(negative voltage regulator)之半導體元件，尤指一種具有一使用三重井 (triple-well) 金屬 氧化物 半導體 (Metal-Oxide-Semiconductor，M0S)電晶體、以用來將一負 電壓穩壓後輸出之負電壓穩壓電路之半導體元件。 【先前技術】 目前市面上之各種電子產品中，常常會使用到穩壓電路 來執行電壓調整的工作，並提供穩定的電壓予設置於穩壓 電路外部之元件。為了提供穩定的電壓，增加電路元件之 穩定性及確保電子裝置之性能，各界皆提出許多不同的穩 壓電路之設計，例如Tanzawa等人提出的US Patent 6,600,692，“Semiconductor Device with a Voltage Regulator”。 一般說來，大部份的電路皆需要將電壓升壓或偏壓在一 較高之正電壓（positive voltage)以使得電路有較好之效 能。然而，仍然有部份電路需要使用負電壓（negative 1278170 voltage)，例如像是現代資訊產品中極重要的非揮發性記憶 裝置·電性可抹除唯謂自己憶體（electrical erasable programmable read only memory，EEPROM)及快閃記憶體 (flash memory)，當快閃記憶體於清除所寫入的資料時，即 需要用到負電壓。然而，目前各界對於穩壓電路之研究與 發明皆集中專注在正電壓之穩壓方面，關於負電壓之穩壓 技術則並無充足之演進，如上述US Patent 6,600,692, “Semiconductor Device with a Voltage Regulator，，所提出之 穩壓電路即不適用於負電壓之穩壓。一般來說，電路中常 以一負電充電電路(negative pump)來產生一負電壓。請參考 第1圖。第1圖為一習知負電壓產生電路1〇〇之示意圖。 110為一振盪器，120為一負電充電電路。振盪器110將其 輸出輸入負電充電電路120,再由負電充電電路12〇輸出 一負電壓V0UT1。請參見第2圖。第2圖為一習知負電壓穩 壓電路200之示意圖。負電壓穩壓電路200中包括一及閘 _ 230，一分壓單元240以及一比較器250。Vref21與Vref22為 二參考電壓，R21與R22為二分壓電阻。相較於第1圖中 Vouti之未經穩壓，分壓單元240以分壓電阻R21與R22 將負電充電電路220之輸出V〇UT2與Vref21分壓，再將此分 ’ 壓產生之電壓VFEBK2迴授輪入比較器250與參考電壓vref22 相比較；比較器250之輸出與振盪器210之输出一起輸入 及閘230，及閘230之輸出再輸入負電充電電路220，如此 形成一穩壓迴路，V〇UT2即為一經穩壓之負電壓輸出 1278170 (regulated negative output voltage ) 〇 對於要求高效能的電路來說，第2圖中之習知負電壓穩 壓電路200之穩壓效果並不夠理想。第2圖中習知負電壓 穩壓電路200運作的情形可描述如下。當ν〇υΤ2之位準低 於目標位準時，迴授電壓Vfebk會被拉低而使得比較器25〇1278170 IX. Description of the Invention: [Technical Field] The present invention provides a semiconductor component having a negative voltage regulator, and more particularly to a metal oxide having a triple-well A semiconductor (Metal-Oxide-Semiconductor, M0S) transistor, a semiconductor component of a negative voltage regulator circuit for regulating a negative voltage. [Prior Art] In various electronic products currently on the market, a voltage stabilizing circuit is often used to perform voltage adjustment, and a stable voltage is supplied to components external to the voltage stabilizing circuit. In order to provide a stable voltage, increase the stability of circuit components, and ensure the performance of electronic devices, various different voltage stabilization circuits have been proposed, such as U.S. Patent 6,600,692, "Semiconductor Device with a Voltage Regulator" by Tanzawa et al. In general, most circuits need to boost or bias the voltage to a higher positive voltage to make the circuit more efficient. However, there are still some circuits that need to use a negative voltage (negative 1278170 voltage), such as a very important non-volatile memory device in modern information products. Electrical erasable programmable read only memory , EEPROM) and flash memory, when the flash memory is used to clear the written data, a negative voltage is needed. However, at present, the research and invention of the voltage regulator circuit focus on the voltage regulation of the positive voltage, and the voltage regulation technology of the negative voltage does not have sufficient evolution, such as the above-mentioned US Patent 6,600,692, "Semiconductor Device with a Voltage Regulator The proposed voltage regulator circuit is not suitable for voltage regulation of negative voltage. Generally speaking, a negative voltage is often generated by a negative charge circuit in the circuit. Please refer to Figure 1. Figure 1 is a diagram A schematic diagram of a conventional negative voltage generating circuit 1 is shown in Fig. 110. An oscillator 120 is a negative charging circuit. The oscillator 110 outputs its output to the negative charging circuit 120, and a negative voltage charging circuit 12 outputs a negative voltage VOUT1. Please refer to Fig. 2. Fig. 2 is a schematic diagram of a conventional negative voltage regulator circuit 200. The negative voltage regulator circuit 200 includes a gate _230, a voltage dividing unit 240 and a comparator 250. Vref21 and Vref22 For the two reference voltages, R21 and R22 are two-divided resistors. Compared with the unregulated Vouti in Fig. 1, the voltage dividing unit 240 uses the voltage dividing resistors R21 and R22 to output the negative charging circuit 220. 2 and Vref21 partial pressure, and then the voltage generated by the voltage VFEBK2 is returned to the comparator 250 and compared with the reference voltage vref22; the output of the comparator 250 is input to the gate 230 together with the output of the oscillator 210, and the gate 230 The output is then input to the negative charging circuit 220, thus forming a voltage stabilizing circuit, and V〇UT2 is a regulated negative output voltage 1278170 (regulated negative output voltage). For a circuit requiring high performance, in FIG. The voltage regulation effect of the conventional negative voltage regulator circuit 200 is not ideal. The operation of the conventional negative voltage regulator circuit 200 in FIG. 2 can be described as follows. When the level of ν〇υΤ2 is lower than the target level, feedback is given. The voltage Vfebk will be pulled low to make the comparator 25〇
之輪出為數位0 (低位準），如此將使得及閘23〇之輸出為 數位0,亦即使得負電充電電路停止隨著振盪器21〇充電 而拉高v〇UT2之位準。反之，t ν〇υτ2之位準高於目標位準 夺’迴授電壓VFEBK會被拉高而使得比較器25〇之輸出為 數位1 (高位準）’如此將使得及閘23〇之輸出為數位卜 亦即使得貞電充電電路隨著㈣器21G充電崎低 之位準。如上所述之迴授穩壓方式受限於比較器250以及 _ 3 230之比#乂範1| ’類似為—數位式之迴授穩壓，使得The round is 0 (low level), which will cause the output of the gate 23 to be digit 0, which causes the negative charging circuit to stop raising the level of v〇UT2 as the oscillator 21 is charged. Conversely, the level of t ν 〇υ τ2 is higher than the target level. The feedback voltage VFEBK is pulled high so that the output of the comparator 25 为 is a bit 1 (high level). This will cause the output of the gate 23 为 to be The digital position also makes the electric charging circuit with the level of the (4) 21G charging low. The feedback voltage regulation method as described above is limited by the ratio of the comparator 250 and the _ 3 230, which is similar to the digital feedback regulation.
經穩壓後之VGUT2仍有偏大之辦起伏，無絲份滿足需 要使用負電壓之電路。 【發明内容】 因此本發明之主要目的在於提供一種具有負電壓穩壓 電路之半導體元件，以改善上述問題。 本發明係揭露一種具有食雷厭捏 住-、3貝冤Μ穩壓電路（negative 1278170 voltage regulator)之半導體元件，其包括一負電壓穩壓電 路，用來將一負輸入電壓(Negative Input voltage)穩壓後於 一輸出節點（Output Node)輸出一負輸出電壓（Negative Output Voltage)。該負電壓穩壓電路包含一驅動單元 (driver)、一第一操作放大器（operational amplifier)、一第 二操作放大器、一電流源 (current source )、以及一分壓單 元。該驅動單元用來調整該負輸出電壓，該驅動單元包含 φ 一第一電晶體、一第二電晶體、一第一節點、一第二節點、 以及一第三節點，其中該第三節點係電連於一第一電壓 源’而該第一節點係電連於該負電壓穩壓電路之輸出節 點；該第一操作放大器包含一第一接收端、一第二接收端、 以及一輸出端，分別電連於一迴授電壓（Feedback V〇ltage)、一 第二參考電壓（Reference Voltage)、以及該第一 電晶體’該第一操作放大器係依據該迴授電壓及該第二參 _ 考電壓以於該輸出端輸出一第一驅動電壓，並據以控制流 經該第一電晶體之第一電流；該第二操作放大器包含一第 一接收端、一第二接收端、以及一輸出端，分別電連於一 第二參考電壓、該迴授電壓、以及該第二電晶體，該第二 操作放大器係依據該第二參考電壓及該迴授電壓以於該輸 出端輸出一第二驅動電壓、並據以控制流經該第二電晶體 之第二電流；該電流源用來提供該驅動單元於運作時所需 之電流；該電流源包含二η型通道三重井(triple-well)金屬 乳化物半導體(Metal-Oxide-Semiconductor，M0S ,金氧半） 1278170 電晶體，其中該二η型通道三重井金氧半電晶體之汲極八 別於該第一節點與該第二節點電連於該第一 /玉刀 、立斗松—； 电曰曰體之汲極 以及該第一電晶體之没極，而該二η型通道三 —里开金氧丰 電晶體之源極(Source)電連接於該負輸入電壓；該第一八曰、 單元，包含—第—端點、—第二端點、以及壓 該第一端點電連於該輸出節點，該第一端點電連於該第 電壓源，而該迴授節點電連於該第一操作放大器之第一接 收端及該第二操作放大器之第二接收端，該第—分壓單元 用來將該第一電壓源之位準以及該負輸出電壓分壓以 該迴授電壓、並繼而將該迴授電壓於一迴授節點輪出至該 第一操作放大器及該第二操作放大器，以調整流經該第一 電晶體及該第二電晶體之電流。 【實施方式】 請參閱第3圖。第3圖為本發明之較佳實施例中具有一 負電壓穩壓電路30之半導體元件300之示意圖。負電壓穩 壓電路30係由一電壓源穩壓電路31〇、一電流源電路320、 一分壓單元340、一驅動單元(driver)350、一第一操作放大 器361、以及一第二操作放大器362所組成。需經穩壓之 負輸入電壓（Negative Input Voltage)VIN3經由輸入節點 (Input Node)NIN輸入至負電壓穩壓電路30、並繼而經負電 壓穩壓電路30穩壓後於輸出節點（Output Node)NOUT輸 1278170 出，以形成一經穩壓之負輸出電壓（Regulated Negative Output Voltage)VOUT3。半導體元件300另包含一參考電壓 產生器（Band Gap Circuit)330，用來產生元件300中各個電 路所需之參考電壓(Reference Voltage)，例如像是第3圖中 所示之一第一參考電壓Vref31與一第二參考電壓Vref32。 以下依序說明第3圖中本發明之具有負電壓穩壓電路After the voltage regulation, the VGUT2 still has a large fluctuation, and the wire does not satisfy the circuit that needs to use a negative voltage. SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a semiconductor device having a negative voltage regulator circuit to improve the above problems. The invention discloses a semiconductor component with a negative 1278170 voltage regulator, which comprises a negative voltage regulator circuit for using a negative input voltage (Negative Input Voltage) After the voltage is regulated, a negative output voltage is outputted to an output node (Negative Output Voltage). The negative voltage regulator circuit includes a driver, a first operational amplifier, a second operational amplifier, a current source, and a voltage dividing unit. The driving unit is configured to adjust the negative output voltage, the driving unit includes φ a first transistor, a second transistor, a first node, a second node, and a third node, wherein the third node is Electrically connected to a first voltage source' and the first node is electrically connected to an output node of the negative voltage regulator circuit; the first operational amplifier includes a first receiving end, a second receiving end, and an output end Connected to a feedback voltage (Feedback V〇ltage), a second reference voltage (Reference Voltage), and the first transistor 'the first operational amplifier according to the feedback voltage and the second parameter _ The test voltage outputs a first driving voltage at the output end, and accordingly controls a first current flowing through the first transistor; the second operational amplifier includes a first receiving end, a second receiving end, and a The output terminal is electrically connected to a second reference voltage, the feedback voltage, and the second transistor, and the second operational amplifier outputs a first output according to the second reference voltage and the feedback voltage Second drive a voltage, and a second current flowing through the second transistor; the current source is used to provide a current required for operation of the driving unit; the current source includes a triple-well triple-well a metal-emulsion semiconductor (Metal-Oxide-Semiconductor, MOS, gold oxide half) 1278170 transistor, wherein the two n-type channel triple well MOS semi-transistor has a bungee of the first node and the second node Connected to the first / jade knife, Lidou pine -; the electrode of the electric body and the pole of the first transistor, and the source of the two n-type channel three - Likai gold oxide crystal ( Source) electrically connected to the negative input voltage; the first octet, the unit, including the -th endpoint, the second endpoint, and the first endpoint electrically connected to the output node, the first endpoint Electrically connected to the first voltage source, and the feedback node is electrically connected to the first receiving end of the first operational amplifier and the second receiving end of the second operational amplifier, the first voltage dividing unit is used to The level of the voltage source and the negative output voltage are divided by the feedback voltage, and then the The feedback voltage to a feedback node to the first round of the operational amplifier and the second operational amplifier to adjust the first electrical and the second electrical current flowing through the crystal of the crystal. [Embodiment] Please refer to Figure 3. Figure 3 is a schematic illustration of a semiconductor component 300 having a negative voltage regulator circuit 30 in accordance with a preferred embodiment of the present invention. The negative voltage regulator circuit 30 is composed of a voltage source voltage regulator circuit 31, a current source circuit 320, a voltage dividing unit 340, a driver 350, a first operational amplifier 361, and a second operational amplifier. 362 components. The negative input voltage (VIN3) to be regulated is input to the negative voltage regulator circuit 30 via the input node NIN, and then regulated by the negative voltage regulator circuit 30 to the output node. NOUT loses 1278170 out to form a regulated negative output voltage (VOUT3). The semiconductor device 300 further includes a reference voltage generator (Band Gap Circuit) 330 for generating a reference voltage required for each circuit in the component 300, such as a first reference voltage as shown in FIG. Vref31 and a second reference voltage Vref32. Hereinafter, the negative voltage regulator circuit of the present invention in FIG. 3 will be sequentially described.
30之半導體元件300中各部份電路之結構與功能。電壓源 穩壓電路310於一第三節點ns產生一穩定之一第一電壓源 Vs。電壓源穩壓電路310包括一第三p型通道金屬氧化物 半導體(Metal-Oxide-Semiconductor，M0S，金氧半）電晶體 p3 以及一苐二操作放大器（〇perati〇nai ampiifier)363。電 曰曰體p3以其源極（source)與元件3〇〇之一第二電麗源，例 如為整個電路之高位準電源vDD相連，以及以其汲極(drain) 電連於第二節點Ns;第三操作放大器363則如第3圖所 不，以其二接收端分別電連於電晶體p3之汲極(drain)與參 考電壓產生器330所提供之—第—參考電壓v瘍，以及以 其輸出端電連於電晶體p3之閘極(_)。f壓源穩壓電路 310可將電晶冑P3之汲極之電壓位準固定在第一參考電壓 vref31之位準而獨立於非穩定之第二電源Vdd之影響之外， 提t、私疋之第壓源Vs。電流源電路似包含一第一 η型通道三重井(tri♦，金氧半(m〇s)電晶體Μ與一第 二η型通道三重井金氧半電晶體 η2，第一 η型通道金氧半 1278170 電晶體nl所通過之第一電流II與第二n型通道金氧半電 晶體n2上所通過之第二電流12呈固定之比例關係。電晶 體nl與n2之源極與輸入節點Nin相連，而因為電晶體二 與n2為三重井(triple-well)金氧半電晶體，因此可以於其汲 極與源極連接負電Μ，負輸人電壓VlN3㈣電晶體μ'與 η2之源極輸入負電壓穩壓電路3〇。分壓單元34〇係用來將 負輸出電壓VOUT3分壓後迴授輸入本發明之負電壓穩壓電 路30’可有許多不同之實施方法，第3圖所示為最簡易之 -實施例。如第3圖所示，分壓單元34()包含兩分壓電阻 R31與R32、一第一端點、一第二端點、以及一迴授節點 nFEBK3 ’若該第—端點電連於第三節點Ns，則該第一端點 電壓係為第-電壓源電壓Vs’該第二端點係電連於輸出節 點Ν0_υτ_ ’即第二端點的端點電壓係為負輸出電壓ν〇υτ3， 刀壓單7L340將第-電壓源Vs與負輸出電壓ν_分壓後 於迴f節it nFEBK3迴授輸人貞電壓魏電路3()。再來介紹 P，單元350。驅動單元350包含—第—p型通道金氧半 電晶體Pl與—第二P魏道金氧半電晶體P2，電晶體pi ” p之源極電連於第二節點接收穩定之第—電壓源 V S ’電晶體P1與P 2之閘極則分別電連於第-操作放大器 361與第二操作放大器⑹之輸出端，第—p型通道金氧 ==之沒極與第一 n型通道金氧半電晶體^之汲 P2之、及t ^第—節點NX卜第二P型通道金氧半電晶體 …Η弟二n型通道金氧半電晶體n2之汲極係電連 12 1278170 於"第二節 ϋ ΧΓ ν ο 大哭‘ 由第一操作放大器361與第二操作放 二之輪出之第—驅動電壓與第二驅動電壓分別控制 第ρ型通道金氧半電晶體pi之第-電流I】與第二 型通道金氧半電晶體p2上之第二電流12。第—操作放大器 361與第二操作放大器362各自以其一接收端接收參考電 壓產生器330所產生之第二參考電壓v如2,而以其另一接 收端電連於迴授節點Nfebk3接收迴授電壓VFEBK3。 根據第3圖所示以及以上所述，本發明之負電壓穩壓電 路運作的情形可描述如下。首先，電壓源穩壓電路31〇以 及分壓單元340係經妥善設計，第一參考電壓⑴與第二 參考電壓Vref32之值也係妥善加以配合選取以相配合。當負 輸出電壓Vmrn高於目標位準時，迴授電壓Vfebk3會跟著 上升而高於第二參考電壓Vref32 ;此時第一操作放大器361 之輸出第一驅動電壓為高位準而第二操作放大器之輸 • 出第二驅動電壓為低位準，導致第一 p型通道金氧半電晶 體pi上所流之弟一電流I!變小而第二P型通道金氧半電晶 體p2上所流之弟一電流變大。然而，第一 η型通道金氧 ' 半電晶體η1與第二η型通道金氧半電晶體η2上所流之電 '流互呈比例’因此在第一 Ρ型通道金氡半電晶體ρ1上所流 之第-電mh而第二P型通道金氧半電晶體p2上所流 之第二電流I2變大的情況下’必須有電流從分壓電路34〇 經輸出節點Νουτ流入第一 η型通道金氧半電晶體ni以補30 The structure and function of each part of the circuit in the semiconductor component 300. The voltage source voltage stabilizing circuit 310 generates a stable first voltage source Vs at a third node ns. The voltage source voltage stabilizing circuit 310 includes a third p-type channel metal oxide semiconductor (Metal-Oxide-Semiconductor, MOS, MOS) transistor p3 and a second operational amplifier (363perati〇nai ampiifier) 363. The electrical body p3 is connected to the second electrical source of the component 3, such as the source, and is connected to the high-level power supply vDD of the entire circuit, and is electrically connected to the second node by its drain. Ns; the third operational amplifier 363 is as shown in FIG. 3, and the two receiving ends are respectively electrically connected to the drain of the transistor p3 and the reference voltage generator 330 to provide the first reference voltage. And a gate (_) electrically connected to the transistor p3 at its output. The f voltage regulator circuit 310 can fix the voltage level of the drain of the transistor 3P3 at the level of the first reference voltage vref31 and is independent of the influence of the unstable second power source Vdd. The first source of voltage Vs. The current source circuit seems to comprise a first n-channel triple well (tri ♦, gold oxy-half (m 〇s) transistor Μ and a second n-channel triple well MOS η 2, first n-channel gold The first current II passed by the oxygen half 1278170 transistor nl is fixedly proportional to the second current 12 passed through the second n-type channel MOS transistor n2. The source and input node of the transistors nl and n2 Nin is connected, and since transistor 2 and n2 are triple-well gold-oxygen semi-transistors, it is possible to connect a negative electrode to its drain and source, and a negative input voltage VlN3 (four) source of transistor μ' and η2 The pole input negative voltage regulator circuit is 3. The voltage dividing unit 34 is used to divide the negative output voltage VOUT3 and then input it to the negative voltage regulator circuit 30' of the present invention. There are many different implementation methods, FIG. The simplest embodiment is shown. As shown in FIG. 3, the voltage dividing unit 34() includes two voltage dividing resistors R31 and R32, a first end point, a second end point, and a feedback node nFEBK3. 'If the first terminal is electrically connected to the third node Ns, the first terminal voltage is the first voltage source voltage Vs 'The second end point is electrically connected to the output node Ν0_υτ_', that is, the end point voltage of the second end point is a negative output voltage ν 〇υ τ3, and the squeezing unit 7L340 divides the first voltage source Vs and the negative output voltage ν_ After returning to the f-section it nFEBK3 feedback input voltage 魏Wei circuit 3 (). Then introduce P, unit 350. The drive unit 350 includes - the -p-type channel MOS semi-transistor Pl and - the second P Weidao gold oxygen The semi-transistor P2, the source of the transistor pi ” p is electrically connected to the second node, and receives the stable first voltage source VS. The gates of the transistors P1 and P2 are electrically connected to the first operational amplifier 361 and the second, respectively. Operate the output of the amplifier (6), the -p-type channel gold oxygen == the pole and the first n-channel gold oxide half-electrode ^ 汲 P2, and t ^ the first node NX 卜 second P-channel gold Oxygen semi-transistor... Η二二 n-channel gold-oxygen semi-transistor n2 汲 系 电 12 12 1278170 in "Second section ϋ ΧΓ ν ο 大哭' by the first operational amplifier 361 and the second operation two The first-out drive voltage and the second drive voltage respectively control the first current I of the p-channel MOS MOS pi and the second a second current 12 on the channel MOS transistor p2. The first operational amplifier 361 and the second operational amplifier 362 each receive a second reference voltage v generated by the reference voltage generator 330, such as 2, at a receiving end thereof. The other receiving end is electrically connected to the feedback node Nfebk3 to receive the feedback voltage VFEBK3. According to the third figure and the above, the operation of the negative voltage voltage stabilizing circuit of the present invention can be described as follows. First, the voltage source voltage regulator The circuit 31A and the voltage dividing unit 340 are properly designed, and the values of the first reference voltage (1) and the second reference voltage Vref32 are also properly matched to match. When the negative output voltage Vmrn is higher than the target level, the feedback voltage Vfebk3 will rise higher than the second reference voltage Vref32; at this time, the output first driving voltage of the first operational amplifier 361 is high and the second operational amplifier is output. • The second driving voltage is low, causing the current flowing in the first p-channel MOS transistor pi to become smaller and the second P-channel MOS transistor A current becomes larger. However, the first n-type channel gold oxide 'semiconductor η1 and the second n-type channel MOS semi-transistor η2 flow in the electrical flow are proportional to each other, thus in the first Ρ-type channel 氡 氡 semi-transistor ρ1 When the second current I2 flowing on the second P-channel MOS transistor p2 becomes larger, the current must flow from the voltage dividing circuit 34 through the output node Νουτ into the first An n-type channel MOS semi-transistor
13 1278170 第—電流Ιι之不足；此電流將使得迴授電壓vFEBK3與負輪 出電壓VOUT3皆被拉低，即透過負電壓穩壓電路30之超 授’將原本高於目標位準之負輸出電壓V0UT3調低回目標 位準。反之，若負輸出電壓V〇UT3低於目標位準時，迴授 電壓vFEBK3會跟著下降而低於Vref32;此時第一操作放大器 361之輸出第一驅動電壓為低位準而第二操作放大器362 之輪出第二驅動電壓為高位準，導致第一 p型通道金氧半 • 電晶體pl上所流之第一電流I!變大而第二P型通道金氧半 電晶體p2上所流之第二電流l變小。同理，在第一 p型通 道金氧半電晶體pi上所流之第一電流L變大而第二p型通 C金氧半電晶體p2上所流之第二電流變小的情況下，第 電"IL 11之部份電流將從輸出節點Νουτ流出至分壓單元 Π此1流將使得迴授電壓Vfebk3與負輸出電壓V〇· 皆^提高，即透過負電壓穩壓電路3G之迴授，將原本低於 目標位準之負輸出電壓v_調高回目標位準。 彳述本發明係將貞輸出電壓vQUT3之分壓vFEI 义艾至負電壓穩壓電路30中以控制驅動單元350之第一 半電晶體P1與第二p型通道金氧半電晶體 第二：：之第一電流11與第二電流12，再藉第-電流11 髓於變化以調整負輸出電壓VOUT3之位準，將 型通、酋：Γ °其中，本發明之—特徵在於使用二 井金氧半電晶體η1與η2。如眾所知，電晶 14 1278170 - 之源極與基極以偏壓在同一電壓位準為佳，因此在本發明 中採用η型通道三重井金氧半電晶體nl與n2組成一電流 源電路，使得電晶體nl與n2之源極與汲極皆可接受負電 壓，而以電晶體nl與n2之源極作為本發明之負電壓穩壓 電路之輸入節點，以及以電晶體nl之汲極作為本發明之負 電壓穩壓電路之輸出節點，以適用於負輸入電壓，實現負 電壓之穩壓功能。 * 總結來說，本發明利用三重井金氧半電晶體之特性，提 供了一簡潔而有效之負電壓穩壓電路，使得需要使用負電 壓之電路能得到穩定之負電壓而提高效能。且根據實際驗 證，若所輸入之負輸入電壓為一負7伏特（-7V)且其上有 200毫伏(mV)擾動之電壓時，經本發明之負電壓穩壓電路 穩壓後，可輸出一-7V而其上僅有小於50mV擾動之穩定 電壓，足證本發明之負電壓穩壓電路可大幅降低負電壓上 # 之雜訊而提供一良好之穩壓效果，支援了快閃記憶體於操 作上之需求。 請再參閱第3圖，除了負電壓穩壓電路30及參考電壓 •產生器330外，半導體元件300另包含一負電充電電路 120、一時脈產生器12、振盪器110、以及一電壓偵測器 14。振盪器110輸出一振盪訊號OSC ;時脈產生器12在接 收到電壓偵測器14所產生之時脈致能訊號CLKEN時、依 15 1278170 據振盪訊號OSC產生—時脈訊號CLK;負電充電電路12〇 依據其所接收到之時脈訊號CLK負充電負輪人電壓VIN3; 電麗偵測器14依據負輸人電壓ViN3之位準、輪出一時脈致 能訊號CLKEN。 、電壓伯測器14包含一比較器16、及複數級串接之P型 通道金屬氧化物半導體電晶體phi至Ph5，其中，比較器 16之正輸入端18電連接於電晶體pM之閘極，電晶體 之閑極即為—偵測迴授節點、負輸人端2G係電連於一比較 電壓，在本實施射該比較電壓係為接地電壓、而輸出端 22用來輸出時脈致能訊號CLKen，電晶體phi及pm之基 極於第五即點Nx5電連接於—參考電壓源，該參考電壓 ?:以是第一電壓源Vs，也可以是第二電壓源VDD、而電 二二h3:Ph4、及ph5之基極均電連接於第二電壓源VDD， ^體ph5之祕與閘極均電連至—第四節點制，第四 =NX4係電連至負輸人電壓ViN3，電晶 =均電連至該偵測迴授節點，在該偵測迴授節點所Μ 之債測迴授電壓即輸入至比較器16之正輪入端18。 電之運作棘朗如下：當負電充電電路 (例如^ 輸人電壓I尚未低於_—預定電壓 〇伏特，特）時’由於電晶體_閑極上之電壓會仍高於 寺’因此’比較器16產生時脈致能訊號clKen，相應 1278170 ‘地’時脈產生n 12依據振盪訊號⑽產生時脈訊號clk、 而負電充電電路120依據其所接收到之時脈訊號clk負充 電負輸人電壓VlN3;當負電充電電路12()所輪^之負輸入 電壓VIW低於該預定電壓時，由於電晶體phi閘極上之電 壓會低於0伏特’因此’比較n 16停止產生時脈致能訊號 clken，相應地，時脈產生器12停止產生時脈訊號CLK、 而負電充電電路120在沒有接收到任何時脈訊號CLK之情 況下’停止負充電負輸入電壓Vm3。如此一來，負電充電 電路120便不會因過低之負輸入電壓Vin3(舉例來說’低於 -13伏特）而發生接面崩潰(junction breakdown)。 請參閱第4圖，第4圖所舉為本發明之具有負電壓穩壓 電路40之半導體元件400之一另一較佳實施例。與第3圖 前述實施例比較，第4圖實施例中，參考電麗產生器330 另產生一第二參考電壓Vref33，而分壓單元340之該第二端 # 點仍與輸出節點Ν〇υτ相連以外，第一端點即可電連於一不 同於第一電壓源Vs之參考電壓產生器330的第三參考電壓 Vref33，也就是說，第一端點電壓即為第三參考電壓Vref33， 所以迴授電壓VFEBK3即是由負輸出電壓v〇UT3與第三參考 電壓Vref33在兩分壓電阻R31與R32之分壓節點NFEBK3所 產生之電壓。此外，參考電壓產生器330另輸出一第四參 考電壓Vrem，而比較器16之負輸入端20係電連至第四參 考電壓Vref34，也就是說，在本實施例中，該比較電壓為第 17 1278170 四參考電壓Vref34，所以，在前述電壓偵測器14之運作說 明過程中，受負輸入電壓VlN3影響之電晶體phl閘極上之 該摘測迴授電壓係和第四參考電壓Vref34比較，用以決定是 否產生時脈致能訊號CLKEN，進而控制負電充電電路120 對負輸入電壓VIN3之負充電程序。其也部份之電路均同於 第3圖前述實施例，所以相關類似說明不再重述，但分壓 單元冰）所包含之元件及其結構亦可有所變化，只要能妥 善使得於迴授節點Nfebk3所產生 < 迴授電壓可 以與弟一參考電壓Vref32相配合以控制楚 雄—如 第—操作放大器361 與第一操作放大器362即可。而電壓;κ 你穩壓電路310亦可 省略或以其他穩壓電路代替，只要能扒 检t、弟三節點Ns提供一 穩疋之苐一電壓源V s即可。關於驅動男一 7乎疋350的部份，第 3圖和第4圖中所舉為結構最簡單之脊 相異但能在控制分壓電路上之電流 ]亦可以、、、口構 V_上達同樣效果之其他電路替代。@整負輸出電壓 在前述本發明之二較佳實施例中， #、 t日日體ph3至+ 基極係電連接至第二電壓源Vdd，然而， & 一 之 VDD其位準通常會擺動於2.5至3.7伏 於弟二電壓源 .. 寻之間，為了倍Φ两、 偵測器14能更精轉地偵測負輸入電壓 垒 1奶’電晶體Dhl方13 1278170 The first-current Ιι is insufficient; this current will cause the feedback voltage vFEBK3 and the negative wheel-out voltage VOUT3 to be pulled low, that is, the over-voltage of the negative voltage regulator circuit 30 will be the negative output that is originally higher than the target level. Voltage V0UT3 is turned down to the target level. On the other hand, if the negative output voltage V〇UT3 is lower than the target level, the feedback voltage vFEBK3 will fall below Vref32; at this time, the output first driving voltage of the first operational amplifier 361 is a low level and the second operational amplifier 362 The second driving voltage is turned to a high level, so that the first current I! flowing on the first p-type channel MOS transistor pl becomes larger and the second P-channel MOS transistor p2 flows. The second current l becomes smaller. Similarly, when the first current L flowing on the first p-type channel MOS semi-transistor pi becomes larger and the second current flowing on the second p-type C-oxide MOS transistor p2 becomes smaller, The current of the first electric current "IL 11 will flow out from the output node Νουτ to the voltage dividing unit. This 1 stream will increase the feedback voltage Vfebk3 and the negative output voltage V〇·, ie, through the negative voltage regulator circuit 3G. The feedback returns the negative output voltage v_ which is lower than the target level back to the target level. The present invention is to divide the output voltage vQUT3 into a voltage divider vFEI to the negative voltage regulator circuit 30 to control the first half transistor P1 of the driving unit 350 and the second p-channel gold oxide half transistor second: The first current 11 and the second current 12 are further changed by the first current 11 to adjust the level of the negative output voltage VOUT3, which will be typed, emirate: Γ °, wherein the present invention is characterized by the use of Erjing Gold Oxygen semiconductors η1 and η2. As is known, it is preferred that the source and the base of the transistor 14 1278170 are biased at the same voltage level. Therefore, in the present invention, the n-channel triple well MOS and n2 form a current source. The circuit is such that the source and the drain of the transistors n1 and n2 can accept a negative voltage, and the sources of the transistors n1 and n2 serve as input nodes of the negative voltage regulator circuit of the present invention, and after the transistor nl As the output node of the negative voltage regulator circuit of the present invention, it is suitable for the negative input voltage and realizes the voltage regulation function of the negative voltage. * In summary, the present invention utilizes the characteristics of a triple well MOS semi-transistor to provide a simple and effective negative voltage regulator circuit that allows a circuit that uses a negative voltage to achieve a stable negative voltage and improve performance. According to the actual verification, if the input negative input voltage is a negative 7 volt (-7V) and there is a voltage of 200 millivolts (mV) perturbation, the negative voltage regulator circuit of the present invention can be output after being regulated by the negative voltage regulator circuit. A -7V with a stable voltage of less than 50mV perturbation, which proves that the negative voltage regulator circuit of the present invention can greatly reduce the noise on the negative voltage and provide a good voltage regulation effect, and supports the flash memory. The operational requirements. Referring to FIG. 3, in addition to the negative voltage regulator circuit 30 and the reference voltage generator 330, the semiconductor component 300 further includes a negative charging circuit 120, a clock generator 12, an oscillator 110, and a voltage detector. 14. The oscillator 110 outputs an oscillation signal OSC. The clock generator 12 generates the clock signal CLKEN according to the oscillation signal OSC when receiving the clock enable signal CLKEN generated by the voltage detector 14; the negative voltage charging circuit 12〇 according to the received clock signal CLK negative charging negative wheel human voltage VIN3; the battery detector 14 according to the level of the negative input voltage ViN3, a clock enable signal CLKEN. The voltage detector 14 includes a comparator 16 and a plurality of cascaded P-channel metal oxide semiconductor transistors phi to Ph5, wherein the positive input terminal 18 of the comparator 16 is electrically connected to the gate of the transistor pM. The idle pole of the transistor is - detecting the feedback node, and the negative input terminal 2G is electrically connected to a comparison voltage. In the present embodiment, the comparison voltage is grounded, and the output terminal 22 is used to output the clock. The signal signal CLKEN, the base of the transistor phi and pm is electrically connected to the reference voltage source at the fifth point Nx5, and the reference voltage is: the first voltage source Vs, or the second voltage source VDD, and the electricity 22h3: The bases of Ph4 and ph5 are electrically connected to the second voltage source VDD, the secret of the body ph5 and the gate are electrically connected to the fourth node system, and the fourth=NX4 system is connected to the negative input. The voltage ViN3, the electric crystal = is connected to the detection feedback node, and the debt feedback voltage of the detection feedback node is input to the positive wheel input terminal 18 of the comparator 16. The operation of electricity is as follows: when the negative charging circuit (for example, ^ input voltage I has not been lower than _ - predetermined voltage 〇 volt, special) 'because the voltage on the transistor _ idle pole will still be higher than the temple 'so the comparator 16 generates a clock enable signal clKen, corresponding to 1278170 'ground' clock generates n 12 according to the oscillation signal (10) generates a clock signal clk, and the negative charging circuit 120 according to the received clock signal clk negative charge negative input voltage VlN3; when the negative input voltage VIW of the negative charging circuit 12() is lower than the predetermined voltage, since the voltage on the gate of the transistor phi will be lower than 0 volts, 'n' compares n 16 to stop generating the clock enable signal Clken, accordingly, the clock generator 12 stops generating the clock signal CLK, and the negative charging circuit 120 stops the negative charging negative input voltage Vm3 without receiving any clock signal CLK. As such, the negative charging circuit 120 does not suffer from junction breakdown due to the low negative input voltage Vin3 (e.g., below -13 volts). Referring to Fig. 4, a fourth preferred embodiment of the semiconductor device 400 having the negative voltage regulator circuit 40 of the present invention is shown. Compared with the foregoing embodiment in FIG. 3, in the embodiment of FIG. 4, the reference voltage generator 330 generates a second reference voltage Vref33, and the second terminal # of the voltage dividing unit 340 is still connected to the output node Ν〇υτ. The first terminal can be electrically connected to a third reference voltage Vref33 different from the reference voltage generator 330 of the first voltage source Vs, that is, the first terminal voltage is the third reference voltage Vref33. Therefore, the feedback voltage VFEBK3 is the voltage generated by the negative output voltage v〇UT3 and the third reference voltage Vref33 at the voltage dividing node NFEB3 of the two voltage dividing resistors R31 and R32. In addition, the reference voltage generator 330 further outputs a fourth reference voltage Vrem, and the negative input terminal 20 of the comparator 16 is electrically connected to the fourth reference voltage Vref34, that is, in the embodiment, the comparison voltage is 17 1278170 four reference voltage Vref34, therefore, during the operation description of the voltage detector 14, the comparison feedback voltage on the gate of the transistor ph1 affected by the negative input voltage VlN3 is compared with the fourth reference voltage Vref34, It is used to determine whether to generate the clock enable signal CLKEN, thereby controlling the negative charging process of the negative charging circuit 120 to the negative input voltage VIN3. The circuit is also the same as the previous embodiment in FIG. 3, so the related description will not be repeated, but the components and structures of the voltage dividing unit ice may also be changed, as long as it can be properly The feedback voltage generated by the node Nfebk3 can be matched with the reference voltage Vref32 to control the Chuxiong-like operational amplifier 361 and the first operational amplifier 362. The voltage; κ, your voltage regulator circuit 310 can also be omitted or replaced by other voltage regulator circuits, as long as it can detect t, the three nodes Ns provide a stable voltage source V s. Regarding the part that drives the male one and the seven, the third and fourth figures are the simplest ridges of the structure but can control the current on the divided piezoelectric circuit. Replace other circuits with the same effect. @整负输出电压 In the second preferred embodiment of the present invention, the #, t 日 日 ph3 to + base is electrically connected to the second voltage source Vdd, however, the VDD level is usually Swinging from 2.5 to 3.7 volts to the second voltage source.. Between the seeks, in order to double Φ two, the detector 14 can more accurately detect the negative input voltage barrier 1 milk 'transistor Dhl square
Ph5之基極也可全部電連接至穩定 至The base of Ph5 can also be electrically connected to stabilize to
不〜電壓源 V 外，在電壓偵測器14中，電晶體ρΜ至 / 此 一分壓器，因此，該分壓器也可以二串 等、丈上係作為 甲接之電阻表示之， 1278170 如分壓單元340中所包含之兩分壓電阻R31與R32。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知一負電壓產生電路之示意圖。 φ 第2圖為習知一負電壓穩壓電路之示意圖。 第3圖為本發明之較佳實施例中一具有負電壓穩壓電路之 半導體元件之示意圖。 第4圖為本發明之另一較佳實施例中一具有負電壓穩壓電 路之半導體元件之示意圖。 【主要元件符號說明】 12 時脈產生器 14 電壓偵測器 Τό ' 比較器 18 正輸入端 *20 負輸入端 22 輸出端 30、200 負電壓穩壓電路 100 負電壓產生 電路 110 ν210 振盪器 120 、 220 負電充電電 路 1278170 230 及閘 240 、 340 分壓單元 250 比較器 300 半導體元件 310 電壓源穩壓電路 320 電流源 330 參考電壓產生器 350 驅動單元 361 、 362 、 363 操作放大器 R21 、 電阻 R22 、 R3 卜 R32 V〇UTl ' V〇uT2 ' 電壓 Nin 、 節點 VfEBK2 ' Vref21 ' Ν〇υτ 、 Vref22 、VS 、 NfeBK3 " VfEBK3 Vref31、 Νχι 、 Vref32 ' Vref33 ' ΝΧ2、Ns、 ViN3 ' Vref34 Νχ4、Νχ5 phi、ph2、ph3、 電晶體 11、12 電流 ph4、ph5、pi、 p2、nl、n2 20In addition to the voltage source V, in the voltage detector 14, the transistor ρ Μ to / this voltage divider, therefore, the voltage divider can also be two strings, etc., as the resistance of the joint is expressed, 1278170 For example, the two voltage dividing resistors R31 and R32 included in the voltage dividing unit 340. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. [Simple Description of the Drawing] Fig. 1 is a schematic diagram of a conventional negative voltage generating circuit. φ Figure 2 is a schematic diagram of a conventional negative voltage regulator circuit. Figure 3 is a schematic illustration of a semiconductor component having a negative voltage regulator circuit in accordance with a preferred embodiment of the present invention. Figure 4 is a schematic illustration of a semiconductor component having a negative voltage regulator circuit in accordance with another preferred embodiment of the present invention. [Main component symbol description] 12 clock generator 14 voltage detector Τό ' Comparator 18 positive input terminal *20 negative input terminal 22 output terminal 30, 200 negative voltage regulator circuit 100 negative voltage generating circuit 110 ν210 oscillator 120 220 negative charging circuit 1278170 230 and gate 240, 340 voltage dividing unit 250 comparator 300 semiconductor element 310 voltage source voltage stabilizing circuit 320 current source 330 reference voltage generator 350 driving unit 361, 362, 363 operating amplifier R21, resistor R22, R3 卜 R32 V〇UTl ' V〇uT2 ' Voltage Nin, node VfEBK2 ' Vref21 ' Ν〇υτ , Vref22 , VS , NfeBK3 " VfEBK3 Vref31 , Νχι , Vref32 ' Vref33 ' ΝΧ 2 , Ns , ViN3 ' Vref34 Νχ 4 , Νχ 5 phi , ph2, ph3, transistor 11, 12 current ph4, ph5, pi, p2, nl, n2 20