CN109830522A

CN109830522A - A kind of Transient Voltage Suppressor and preparation method thereof

Info

Publication number: CN109830522A
Application number: CN201811530030.8A
Authority: CN
Inventors: 不公告发明人
Original assignee: Quanzhou Intelligent Technology Co Ltd
Current assignee: Quanzhou Intelligent Technology Co Ltd
Priority date: 2018-12-14
Filing date: 2018-12-14
Publication date: 2019-05-31

Abstract

The present invention provides a kind of Transient Voltage Suppressor and preparation method thereof, comprising: provides the substrate of the first conduction type and the epitaxial layer of the second conduction type；The first buried layer and the second buried layer of the first conduction type are formed in the epitaxial layer；Form the first medium layer that the substrate is extended to through the epitaxial layer；Form the second dielectric layer and third dielectric layer extended in the epitaxial layer from the epitaxial layer upper surface；The first injection region of the second conduction type is formed in the upside of first buried layer and second buried layer；Form the second injection region of the second conduction type between the second groove and the third groove respectively in the first groove；The third injection region of the first conduction type is formed between the second groove and the third groove；Surface forms the first metal layer and second metal layer on said epitaxial layer there；It is respectively formed front electrode and rear electrode, by surge voltage clamper in reduced levels, while there is ultra-low capacitance again.

Description

A kind of Transient Voltage Suppressor and preparation method thereof

Technical field

The present invention relates to technical field of semiconductors, and in particular to a kind of Transient Voltage Suppressor and preparation method thereof.

Background technique

TVS (TransientVoltage Suppressor, i.e. Transient Voltage Suppressor) device is a kind of clamper over-voltage guarantor Device is protected, surge voltage can be fixed on a relatively low voltage level in a short period of time, exempt from back-end circuit by it By excessive pressure damages, main application is as a large amount of in having in mobile phone, plate, television set, host computer in all kinds of interface circuits TVS protects device.

Now with the continuous development of electronic product, TVS device is in such as HDMI (High Definition Multimedia Interface, i.e. high-definition multimedia interface), USB (Universal Serial Bus, i.e. universal serial bus), MIPI Make in signal transmission interfaces such as (Mobile Industry Processor Interface, i.e. mobile industry processor interface) Further frequently, while with the continuous promotion of application end transmission rate, accordingly to the electrology characteristic requirement of TVS device It is higher and higher, it especially requires TVS device that there is especially small capacitor, to avoid the interference to high frequency transmission signal, uses Often capacitor is larger for the TVS device of the prior art, frequently results in signal transmission abnormality.

Summary of the invention

The present invention is based on the above problems, proposes a kind of Transient Voltage Suppressor and preparation method thereof, can will be unrestrained Voltage clamping is gushed in a reduced levels, while it is lossless that there is ultra-low capacitance to transmit to signal again.

In view of this, on the one hand the embodiment of the present invention proposes a kind of Transient Voltage Suppressor, the Transient Voltage Suppressor Include:

The substrate of first conduction type；

The epitaxial layer of second conduction type is grown on the upper surface of substrate；

The first buried layer and the second buried layer of first conduction type, first buried layer and second buried layer are located at institute State the two sides of epitaxial layer；

First medium layer extends through the epitaxial layer and extends to the substrate, and is respectively formed in described first and buries The two sides of layer and second buried layer；

Second dielectric layer and third dielectric layer extend in the epitaxial layer from the epitaxial layer upper surface respectively；

First injection region of the second conduction type is respectively formed in the upside of first buried layer and second buried layer； Second injection region of the second conduction type is respectively formed between the first medium layer and the second dielectric layer, Yi Jisuo It states between first medium layer and the third dielectric layer；The third injection region of first conduction type, is formed in the second medium Between layer and the third dielectric layer；

The first metal layer and second metal layer, be respectively formed in the epitaxial layer upper surface and with first injection region and The second injection region connection；

First electrode is formed in the epitaxial layer upper surface and connect with the third injection region；

Second electrode is formed in the substrate lower surface and connect with the substrate.

Further, first injection region is connect with first buried layer and second buried layer respectively.

Further, second injection region and the third injection region are connect with the epitaxial layer respectively.

Further, first buried layer and second buried layer are symmetrical arranged, and the first medium layer is symmetrical arranged, institute It states second dielectric layer and the third dielectric layer is symmetrical arranged.

Further, the lower surface of first buried layer and second buried layer is connect with the substrate respectively.

On the other hand the embodiment of the present invention provides a kind of production method of Transient Voltage Suppressor, this method comprises:

The substrate of first conduction type is provided；

The epitaxial layer of two conduction type of surface growth regulation over the substrate；

Form the first buried layer and the second buried layer of the first conduction type in the epitaxial layer, first buried layer and described Second buried layer is located at the two sides of the epitaxial layer；

The first groove of the substrate is formed through the epitaxial layer and extends to, the first groove is located at described The two sides of first buried layer and second buried layer, and first medium layer is formed in the first groove；

It is formed from the epitaxial layer upper surface and extends to second groove and third groove in the epitaxial layer, and described Second dielectric layer and third dielectric layer are respectively formed in second groove and the third groove；

The first injection region of the second conduction type is respectively formed on the upside of first buried layer and second buried layer；? Second is respectively formed between the first groove and the second groove and between the first groove and the third groove Second injection region of conduction type；The third note of the first conduction type is formed between the second groove and the third groove Enter area；

Surface is respectively formed the first gold medal for connecting first injection region and second injection region on said epitaxial layer there Belong to layer and second metal layer；

Surface forms the first electrode for connecting the third injection region on said epitaxial layer there；

The second electrode of the substrate connection is formed in the lower surface of the substrate.

The technical solution of the embodiment of the present invention is by providing the substrate of the first conduction type；Surface is grown over the substrate The epitaxial layer of second conduction type；The first buried layer and the second buried layer of the first conduction type are formed in the epitaxial layer, it is described First buried layer and second buried layer are located at the two sides of the epitaxial layer；It is formed through the epitaxial layer and is extended to described The first groove of substrate, the first groove are located at the two sides of first buried layer and second buried layer, and described First medium layer is formed in first groove；Formed from the epitaxial layer upper surface extend to second groove in the epitaxial layer and Third groove, and second dielectric layer and third dielectric layer are respectively formed in the second groove and the third groove；Institute State the first injection region that the second conduction type is respectively formed on the upside of the first buried layer and second buried layer；In the first groove The of the second conduction type is respectively formed between the second groove and between the first groove and the third groove Two injection regions；The third injection region of the first conduction type is formed between the second groove and the third groove；Described Epitaxial layer upper surface is respectively formed the first metal layer and the second metal of connection first injection region and second injection region Layer；Surface forms the first electrode for connecting the third injection region on said epitaxial layer there；It is formed in the lower surface of the substrate , can be by surge voltage clamper in a reduced levels in the second electrode of substrate connection, while there is ultra-low capacitance again Signal is transmitted lossless.

Detailed description of the invention

In order to illustrate the technical solution of the embodiments of the present invention more clearly, below to needed in embodiment description Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.

Fig. 1 is the flow diagram of the production method for the Transient Voltage Suppressor that one embodiment of the present of invention provides；

Fig. 2 is the structural schematic diagram for the Transient Voltage Suppressor that one embodiment of the present of invention provides；

Fig. 3 to Fig. 9 is the structure of the production method step for the Transient Voltage Suppressor that one embodiment of the present of invention provides Schematic diagram；

Figure 10 is the equivalent circuit diagram for the Transient Voltage Suppressor structure that one embodiment of the present of invention provides；

In figure: 1, substrate；2, epitaxial layer；3, the first buried layer；4, the second buried layer；5, first groove；6, first medium layer；7, Second groove；8, third groove；9, second dielectric layer；10, third dielectric layer；11, the first injection region；12, the second injection region； 13, third injection region；14, the first metal layer；15, second metal layer；16, first electrode；17, second electrode；A1, the one or two pole Pipe；B1, the second diode；C1, third diode.

Specific embodiment

It below will the present invention will be described in more detail refering to attached drawing.In various figures, identical element uses similar attached Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.

It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another Layer, another region " following " or " lower section ".

If will use that " A is directly on B herein to describe located immediately at another layer, another region above scenario The expression method of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and And A and B is abutted directly against, rather than A is located in the doped region formed in B.

In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices The general designation of conductor structure, including all layers formed or region.

Many specific details of the invention, such as structure, material, the size, processing side of device are described hereinafter Method and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press The present invention is realized according to these specific details.

Below in conjunction with Fig. 1 to Figure 10 to a kind of Transient Voltage Suppressor provided in an embodiment of the present invention and preparation method thereof into Row is described in detail.

Referring next to attached drawing, a kind of production method of Transient Voltage Suppressor of the embodiment of the present invention is elaborated.

As depicted in figs. 1 and 2, the production method of the Transient Voltage Suppressor includes:

Step S01: the substrate 1 of the first conduction type is provided；In the outer of 1 upper surface growth regulation of substrate, two conduction type Prolong layer 2；

Step S02: forming the first buried layer 3 and the second buried layer 4 of the first conduction type in the epitaxial layer 2, and described One buried layer 3 and second buried layer 4 are located at the two sides of the epitaxial layer 2；

Step S03: form through the epitaxial layer 2 and extend to the first groove 5 of the substrate 1, the first groove 5 The two sides of first buried layer 3 and second buried layer 4 are located at, and form first medium layer in the first groove 5 6；

Step S04: the second groove 7 and third ditch extended in the epitaxial layer 2 from 2 upper surface of epitaxial layer is formed Slot 8, and second dielectric layer 9 and third dielectric layer 10 are respectively formed in the second groove 7 and the third groove 8；

Step S05: the of the second conduction type is respectively formed in the upside of first buried layer 3 and second buried layer 4 One injection region 11；Between the first groove 5 and the second groove 7 and the first groove 5 and the third groove The second injection region 12 of the second conduction type is respectively formed between 8；The shape between the second groove 7 and the third groove 8 At the third injection region 13 of the first conduction type；

Step S06: surface is respectively formed connection first injection region 11 and second injection on the epitaxial layer 2 The first metal layer 14 and second metal layer 15 in area 12；

Step S07: surface forms the first electrode 16 for connecting the third injection region 13 on the epitaxial layer 2；Institute The lower surface for stating substrate 1 is formed in the second electrode 17 that the substrate 1 connects.

Specifically, first conduction type is one of p-type doping and n-type doping, and second conduction type is P Type doping and the another kind in n-type doping.

Special to illustrate herein for convenience of description: first conduction type can be n-type doping, so that described second is conductive Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping. In next embodiment, adulterated by p-type of first conduction type, second conduction type is that n-type doping is Example is described, but is defined not to this.

Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three It closes.The N-type semiconductor is any combination of the silicon wafer for adulterating pentad, such as P elements or arsenic element or both.

Attached drawing 3 is please referred to, step S01 is executed, specifically: the substrate 1 of the first conduction type is provided；On the substrate 1 The epitaxial layer 2 of two conduction type of surface growth regulation；In some embodiments of the invention, the substrate 1 is, for example, monocrystalline silicon lining Bottom 1, and doping concentration is, for example, 1e15atoms/cm³.Wherein, in 1 upper surface growth regulation one of the substrate of the first conduction type The mode of the epitaxial layer 2 of conduction type is not limited to a kind of fixed mode, can use epitaxial growth in 1 upper surface of substrate It is formed, the epitaxial layer 2 can also be formed in 1 upper surface of substrate by ion implanting and/or the method for diffusion.Further Ground can be epitaxially-formed in the 1 upper surface use of substrate, can also by ion implanting and/or diffusion P elements or The method of any combination of arsenic element or both forms the epitaxial layer 2 in 1 upper surface of substrate.Specifically, the extension Or the method for diffusion includes depositing operation.In some embodiments of the invention, depositing operation can be used on the substrate 1 Surface forms the epitaxial layer 2, for example, depositing operation can be selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition One of product, sputtering.Preferably, epitaxial layer 2, chemical vapor deposition are formed using chemical vapor deposition on the substrate 1 Including process for vapor phase epitaxy.In production, chemical vapor deposition uses process for vapor phase epitaxy mostly, in 1 upper surface of substrate Epitaxial layer 2 is formed using process for vapor phase epitaxy, the perfection of silicon materials can be improved in process for vapor phase epitaxy, improves the integrated of device Degree, reaches raising minority carrier life time, reduces the leakage current of storage element.Preferably, the epitaxial layer 2 and the substrate 1 are all silicon Material is made, so that the substrate 1 and the epitaxial layer 2 have the silicon face of same crystal structure, to keep to dopant type With the control of concentration.Due to autodoping effect, in epitaxial process, the dopant from the substrate 1 can enter outer Prolong in layer 2, to change the electric conductivity of epitaxial semiconductor layer.The epitaxial layer 2 covers the upper surface of the substrate 1, and sets There is certain thickness.It should be noted that the thickness of the substrate 1 is, for example, 600-700 microns, the thickness of the epitaxial layer 2 For example, 15 microns.The epitaxial layer 2 and the substrate 1 are used to adjust the reverse breakdown electricity of the Transient Voltage Suppressor Pressure, is not involved in form PN junction.Preferably, it by adjusting from the substrate 1 to the doping concentration of the epitaxial layer 2, can control The breakdown voltage of the Transient Voltage Suppressor protection chip, such as in 2-48V or bigger range.

Attached drawing 4 is please referred to, step S02 is executed, specifically: the first of the first conduction type is formed in the epitaxial layer 2 Buried layer 3 and the second buried layer 4, first buried layer 3 and second buried layer 4 are located at the two sides of the epitaxial layer 2.Described One buried layer 3 and second buried layer 4 can also pass through ion implanting and/or diffusion boron element by being epitaxially-formed Or the method for any combination of phosphide element or aluminium element or three is formed.Preferably, the injection of ion selectivity region can be used And the method for carrying out High temperature diffusion forms first buried layer 3 and second buried layer 4, forms the buried layer by ion implanting The accumulated dose, depth distribution and surface uniformity that impurity can accurately be controlled can prevent spreading again for original impurity, while can realize Self-aligned technology, to reduce capacity effect.In some embodiments of the invention, first buried layer 3 and second buried layer 4 At least partly surface exposure in the upper surface of the epitaxial layer 2, i.e., the upper surface of the described buried layer is exposed to the epitaxial layer 2. As an example, first buried layer 3 and second buried layer 4 are symmetrical, and structure is roughly the same, and ion dose be 5E14~ 8E14CM^-2, Implantation Energy is 120~150KeV.In some embodiments of the invention, the buried layer is heavy doping, thus into One step reduces the resistivity of the power diode.Preferably, first buried layer 3 and second buried layer 4 pass through ion It injects and carries out the mode of High temperature diffusion specifically, carrying out 200~300 minutes heat in 1150~1250 DEG C of high temperature furnace pipe Process, so that the substrate 1 is connected to the buried layer.

Further, the lower surface of first buried layer 3 and second buried layer 4 is connect with the substrate 1 respectively.At this In some embodiments of invention, first buried layer 3 and second buried layer 4 are located at the two sides of the epitaxial layer 2, and It is connect respectively with the substrate 1, it is adjustable from the substrate 1 to first buried layer 3 and from the substrate 1 to described The doping concentration of two buried layers 4, and then can control the breakdown voltage of the Transient Voltage Suppressor protection chip.

Attached drawing 5 is please referred to, step S03 is executed, specifically: it is formed through the epitaxial layer 2 and extends to the substrate 1 First groove 5, the first groove 5 are located at the two sides of first buried layer 3 and second buried layer 4, and described First medium layer 6 is formed in one groove 5.In some embodiments of the invention, the first groove 5 be deep trench, and with institute State the contact of substrate 1.Specifically, one layer of exposure mask is prepared and covers in the upper surface of the epitaxial layer 2, which includes described in exposure The opening of whole upper surfaces of first groove 5, and in the opening of the exposure mask by carrying out dry etching in the epitaxial layer 2, Exposure mask is finally removed, the first groove 5 is formed, and fills first medium layer 6 in the first groove 5.Preferably, described The two sides for being located at first buried layer 3 and second buried layer 4 of first groove 5, also, the first medium layer 6 divides It is not connect with first buried layer 3 and second buried layer 4, it should be noted that first in the first groove 5 is situated between at this time First buried layer 3, the epitaxial layer 2 and second buried layer 4 are individually insulated and are come by matter layer 6, guarantee that described first buries Layer 3, second buried layer 4 and the epitaxial layer 2 mutually carry out reaction and form PN junction.Preferably, the first groove 5 is cutd open Face width is 1.2~1.5 μm, and depth profiled is 18 μm, and the depth of the first groove 5 is than the thickness of the epitaxial layer 2 Deep 20%, guarantee 5 depth of first groove into the substrate 1.

Attached drawing 6 is please referred to, step S04 is executed, specifically: it is formed from 2 upper surface of epitaxial layer and extends to the extension Second groove 7 and third groove 8 in layer 2, and second Jie is respectively formed in the second groove 7 and the third groove 8 Matter layer 9 and third dielectric layer 10.In some embodiments of the invention, the second groove 7 is relative to the first groove 5 Say to be shallow trench, the second groove 7 is connect with the epitaxial layer 2.Specifically, it is prepared simultaneously in the upper surface of the epitaxial layer 2 One layer of exposure mask is covered, which includes the opening of whole upper surfaces of the exposure second groove 7 and the third groove 8, and In the opening of the exposure mask by carrying out dry etching in the epitaxial layer 2, exposure mask is finally removed, the second groove 7 is formed With the third groove 8, and the second dielectric layer 9 and institute are filled respectively in the second groove 7 and the third groove 8 State third dielectric layer 10.It should be noted that the first medium layer 6, the second dielectric layer 9 and the third dielectric layer 10 Material be silicon oxide or silicon nitride or silicon oxynitride, specifically can be by using sputtering or thermal oxidation method or chemical vapor deposition Technique forms the first medium layer 6, the second dielectric layer 9 and the third dielectric layer 10.Preferably, the first medium Layer 6, the second dielectric layer 9 and the third dielectric layer 10 are the silicon oxide layer that thermal oxide is formed, in subsequent doping step In, the silicon oxide layer is as protective layer, and by the interlayer insulating film as resulting devices.In addition, the first medium layer 6, the second dielectric layer 9 and the third dielectric layer 10 are equipped with certain thickness, so that the first medium layer 6, described the Second medium layer 9 and the third dielectric layer 10 play the role of that electric current and insulation is isolated.Preferably, the second groove 7 and institute The sectional width for stating third groove 8 is 1.2~1.5 μm, the depth profiled of the second groove 7 and the third groove 8 is 8~ 10 μm, guarantee the depth profiled of the second groove 7 and the third groove 8 be less than the depth profiled of the first groove 5 with And the thickness of the epitaxial layer 2.

Further, first buried layer 3 and second buried layer 4 are symmetrical arranged, and the first medium layer 6 is symmetrically set It sets, the second dielectric layer 9 and the third dielectric layer 10 are symmetrical arranged.In some embodiments of the invention, the present invention is real The Transient Voltage Suppressor for applying example offer is center symmetrical structure.In technique, the technology difficulty of symmetrical structure is than asymmetric Structure technology difficulty it is lower, improve production efficiency.In structure, symmetrical structure can reduce the embodiment of the present invention and mention The defect of the Transient Voltage Suppressor of confession, it is easier to realize its performance.

Attached drawing 7 is please referred to, step S05 is executed, specifically: in the upside of first buried layer 3 and second buried layer 4 point The first injection region 11 of the second conduction type is not formed；It is between the first groove 5 and the second groove 7 and described The second injection region 12 of the second conduction type is respectively formed between first groove 5 and the third groove 8；In the second groove The third injection region 13 of the first conduction type is formed between 7 and the third groove 8.In some embodiments of the invention, institute Stating the first injection region 11, second injection region 12 and the third injection region 13 is to inject to be formed by ion selectivity And rta technique is carried out, the implant damage during rta technique can be formed ion implanting is repaired. Specifically, first injection region 11 and second injection region 12 pass through ion implanting and/or diffusion P elements or arsenic element Or both the method for any combination formed, the third injection region 13 passes through ion implanting and/or diffusion boron element or indium member The method of any combination of element or aluminium element or three is formed, the injection of first injection region 11 and second injection region 12 Dosage is for example 8E15~1.2E16CM^-2, Implantation Energy is for example 80~100KeV, the injection of the third injection region 13 Dosage is, for example, 4E15~6E15CM^-2, Implantation Energy is, for example, 80~100KeV.Specifically, first injection region 11, described The condition that second injection region 12 and the third injection region 13 carry out high annealing is, in 1100~1150 DEG C of high temperature chamber It is interior, carry out 8~12 seconds thermal process.

Further, the doping concentration of the substrate 1 is higher than the doping concentration of the epitaxial layer 2.Of the invention some In embodiment, during growing epitaxial layer 2 on the substrate 1, since the epitaxial layer 2 is in the base of the substrate 1 It is formed on plinth, therefore the doping concentration of the substrate 1 is higher than the doping concentration of the epitaxial layer 2.The electricity of the epitaxial layer 2 at this time Resistance rate is higher than the resistivity of the substrate 1, so as to adjust the integral device resistivity of the Transient Voltage Suppressor, obtains More Surge handling capabilities.

Further, first injection region 11 is connect with first buried layer 3 and second buried layer 4 respectively.At this In some embodiments of invention, the quantity of first buried layer 3 is at least one, and the quantity of second buried layer 4 is at least one It is a, therefore, the quantity at least two of first injection region 11, since first buried layer 3 and second buried layer 4 are symmetrical Setting, therefore two first injection regions 11 are symmetrical arranged, first injection region 11 is divided for positioned at 3 He of the first buried layer It the upside of second buried layer 4 and is connect with first buried layer 3 and second buried layer 4, for so that first buried layer 3 PN junction is formed with first injection region 11 respectively with second buried layer 4, and then forms diode.

Further, second injection region 12 and the third injection region 13 are connect with the epitaxial layer 2 respectively.At this In some embodiments of invention, the quantity of the second groove 7 is at least one, and the quantity of the third groove 8 is at least one A, therefore the quantity at least two of second injection region 12, the quantity of the third injection region 13 is at least one, and Second injection region 12 and the third injection region 13 are connect with the epitaxial layer 2 respectively, so that the third is injected Area 13 and the epitaxial layer 2 form PN junction, to form diode.

Further, second injection region 12 is different with the doping concentration of the epitaxial layer 2, so as to control to adjust The integral device resistivity of the Transient Voltage Suppressor, obtains more Surge handling capabilities.

It please refers to attached drawing 8, executes step S06, specifically: surface is respectively formed connection described the on the epitaxial layer 2 The first metal layer 14 and second metal layer 15 of one injection region 11 and second injection region 12.In some embodiments of the present invention In, the first metal layer 14 and the second metal layer 15 are by carrying out sputtering gold in the front of the chip (silicon wafer) Belong to, then is formed by lithography and etching technique.Specifically, the first metal layer 14 and the second metal layer 15 are interconnection gold Belong to.Preferably, the first metal layer 14 and the second metal layer 15 are symmetrical, and the first metal layer 14 and described second Metal layer 15 links together first injection region 11 and second injection region 12, so that 11 He of the first injection region Second injection region 12 is electrically connected.

Attached drawing 8 and attached drawing 9 are please referred to, step S07 is executed, specifically: surface is formed described in connection on the epitaxial layer 2 The first electrode 16 of third injection region 13；The second electrode 17 that the substrate 1 connects is formed in the lower surface of the substrate 1. In some embodiments of the invention, splash-proofing sputtering metal is being carried out by the front in the chip, then is passing through lithography and etching work During skill forms the first metal layer 14 and the second metal layer 15, it is preferred that described can also be formed simultaneously One electrode 16, the first electrode 16 are specially the end IO metal layer, and the first electrode 16 is also front electrode.It needs to illustrate It is that the embodiment of the present invention also carries out chip (silicon wafer) back side thinned, evaporation metal is being carried out to the back side, to form described the Two electrodes 17, the second electrode 17 are specially ground terminal metal, and the second electrode 17 is also rear electrode.As an example, The chip (silicon wafer) be thinned after with a thickness of 150-200 microns.It should be understood that the first electrode 16 are drawn and are located at described the Third injection region 13 in second medium layer 9 and the third dielectric layer 10, not with the second dielectric layer 9, the third medium Layer 10 and be the second injection region 12 connection.

It should be understood that the first electrode 16 and 17 upper surface of the second electrode could be covered with passivation layer, it is described blunt Change layer for protecting the first electrode 16 and the second electrode 17, so that protecting the entire Transient Voltage Suppressor.

The embodiment of the present invention in device inside by foring as the first groove 5 of deep trench and as shallow ridges The second groove 7 of slot and the third groove 8, and in the first groove 5, the second groove 7 and the third groove 8 Between form respectively first injection region 11, second injection region 12 and the third injection region 13, due to described outer The resistivity for prolonging layer 2 is very high, and doping concentration is very low, so that the Transient Voltage Suppressor that the embodiment of the present invention is formed is with very wide Depletion region, since second injection region 12 and the third injection region 13 pass through the second dielectric layer 9 and the third Dielectric layer 10 is isolated, so that the area of the depletion region is smaller, so that the transient voltage that the embodiment of the present invention is formed inhibits Device has the characteristic of ultra-low capacitance, and capacitance can be less than 0.1pF, and capacitor transient stage voltage suppressor lower than tradition reduces 50% or more capacitor, therefore more practical high speed signal port.

As shown in Fig. 2, the embodiment of the present invention provides a kind of Transient Voltage Suppressor, shown Transient Voltage Suppressor includes:

The substrate 1 of first conduction type；

The epitaxial layer 2 of second conduction type is grown on 1 upper surface of substrate；

The first buried layer 3 and the second buried layer 4 of first conduction type, first buried layer 3 and second buried layer 4 distinguish position In the two sides of the epitaxial layer 2；

First medium layer 6 extends through the epitaxial layer 2 and extends to the substrate 1, and is respectively formed in described first The two sides of buried layer 3 and second buried layer 4；

Second dielectric layer 9 and third dielectric layer 10 extend in the epitaxial layer 2 from 2 upper surface of epitaxial layer respectively；

First injection region 11 of the second conduction type is respectively formed in the upper of first buried layer 3 and second buried layer 4 Side；Second injection region 12 of the second conduction type, is respectively formed between the first medium layer 6 and the second dielectric layer 9, And between the first medium layer 6 and the third dielectric layer 10；The third injection region 13 of first conduction type, is formed in institute It states between second dielectric layer 9 and the third dielectric layer 10；

The first metal layer 14 and second metal layer 15, be respectively formed in 2 upper surface of epitaxial layer and with first note Enter area 11 and second injection region 12 connection；

First electrode 16 is formed in 2 upper surface of epitaxial layer and connect with the third injection region 13；

Second electrode 17 is formed in 1 lower surface of substrate and connect with the substrate 1.

In some embodiments of the invention, as shown in Fig. 2, Transient Voltage Suppressor provided in an embodiment of the present invention includes The substrate 1 of first conduction type and the epitaxial layer 2 of the second conduction type are grown on 1 upper surface of substrate.The epitaxial layer 2 are grown on 1 upper surface of substrate.Specifically, the substrate 1 is the carrier in integrated circuit, and the substrate 1 plays support Effect, the substrate 1 also assist in the work of the integrated circuit.The substrate 1 can be silicon substrate, or sapphire lining Bottom can also be silicon Chu substrate, it is preferred that the substrate 1 is silicon substrate, this is because silicon substrate material is with inexpensive, big Size, conductive feature, avoid edge effect, can increase substantially yield.As an example, the resistance of the substrate 1 Rate is 0.001~0.002 Ω * cm, and the resistivity of the epitaxial layer 2 is 150~200 Ω * cm.

In some embodiments of the invention, as shown in Fig. 2, Transient Voltage Suppressor provided in an embodiment of the present invention also wraps It includes and extends through the epitaxial layer 2 and extend to the substrate 1, and be respectively formed in first buried layer 3 and described second and bury The first medium layer 6 of the two sides of layer 4, it should be noted that since the first medium layer 6 is located at first buried layer 3 With the two sides of second buried layer 4, therefore, the quantity of the first medium layer 6 is at least 4, to guarantee that described first is situated between Matter layer 6 keeps apart first buried layer 3 and second buried layer 4 with the epitaxial layer 2 respectively.

In some embodiments of the invention, as shown in Fig. 2, in Transient Voltage Suppressor provided in an embodiment of the present invention Second injection region 12 and the third injection region 13 are isolated by the second groove 7 and the third groove 8 respectively, by It relative to the first groove 5 is shallow trench, therefore, second injection region in the second groove 7 and the third groove 8 12 and the third injection region 13 spacing it is smaller, to save out more areas for the Transient Voltage Suppressor so that The Transient Voltage Suppressor has integrated level higher, the lower advantage of production cost.

In some embodiments of the invention, as shown in Fig. 2, in Transient Voltage Suppressor provided in an embodiment of the present invention The first groove 5 is mutually isolated to first injection region 11, second injection region 12 respectively, so that described first The PN junction that injection region 11 and the buried layer are formed, the PN junction that second injection region 12 is formed with the epitaxial layer 2 are isolated, separately Outside, the first groove 5 is deep trench, has big depth-to-width ratio, thus area needed for reducing device surface isolation, therefore can There are more areas for antisurge, the stronger characteristic of surge current protective capacities is made it have.

Further, the first groove 5 can also improve the reliability of device, and especially silicon wafer is in scribing encapsulation process In, the first groove 5 of chip both sides of the edge and the first medium layer 6 can protect chip edge from caused by scribing Sliver risk.

In some embodiments of the invention, as shown in Fig. 2, in Transient Voltage Suppressor provided in an embodiment of the present invention Substrate 1 is thinned,, can will be unrestrained when so that device carrying out surge protection to reduce the conducting resistance of entire device Voltage clamping is gushed in lower voltage range, it is significantly more efficient to protect late-class circuit.

Current Transient Voltage Suppressor is largely only adapted to form the suppression of single channel transient voltage in a chip Device processed.In order to form multichannel Transient Voltage Suppressor, then need to form a channel unit in respective chip respectively, so By by bonding wire, each chip is electrically connected to each other to form array.Bonding wire between chip leads to packaging cost Increase, and introduce lead resistance and parasitic capacitance, so that the reliability of semiconductor devices reduces.

In conclusion the Transient Voltage Suppressor overall structure is symmetrical and is the first primitive unit cell.

Please refer to the equivalent circuit diagram of Transient Voltage Suppressor structure shown in Fig. 10.It should be noted that formed below The forward and reverse of PN junction p-type is set as with the first conduction type, it is of the invention one that second conduction type, which is set as N-type, A embodiment judged, but also not to this restriction.Apply high speed when the first electrode 16 is in normal operating conditions When signal, the epitaxial layer 2 and the third injection region 13 form first diode a1, at this time the first diode a1 tool There is especially small capacitor, therefore signal is unaffected, it is ensured that normal transmission.When the first electrode 16 is met with suddenly When surge current, surge current passes through the first diode a1 first.The buried layer and first injection region 11 form the Two diode b1, the substrate 1 and the epitaxial layer 2 form third diode c1, the second diode b1 and the third Diode c1 is in parallel, and the second diode b1 is reversed at this time, its breakdown reverse voltage is far smaller than the three or two pole at this time Pipe c1, the reverse breakdown therefore the second diode b1 takes the lead in, surge current are able to by described in the second diode b1 entrance Second electrode 17 is released, so that impact of the back-end circuit from surge current, to protect back-end circuit.

It should be noted that the first diode a1 holds for dropping, the second diode b1 is used for antisurge, described Third diode c1 is parasitic high-voltage diode.

It should be noted that since the Transient Voltage Suppressor overall structure is symmetrical and is the first primitive unit cell.For convenience of saying Bright, the embodiment of the present invention specifically describes the structure of the Transient Voltage Suppressor by taking first primitive unit cell as an example, but is not limited only to This, those skilled in the art can the primitive unit cell of the Transient Voltage Suppressor determines according to actual conditions specific structure.

The technical solution of the embodiment of the present invention is had been described in detail above with reference to the accompanying drawings, the embodiment of the present invention is in traditional transient state electricity It is improved on the basis of pressure suppressor and proposes a kind of low capacitor transient stage voltage suppressor, by foring work in device inside The first groove 5 for deep trench and the second groove 7 as shallow trench and the third groove 8, and described first First injection region 11, second note are formed respectively between groove 5, the second groove 7 and the third groove 8 Enter area 12 and the third injection region 13, therefore the epitaxial layer 2 and the third injection region 13 form the transient voltage The depletion region of suppressor.Since the resistivity of the epitaxial layer 2 is very high, doping concentration is very low, therefore the depletion region is very wide, and And second injection region 12 and the third injection region 13 are isolated by the second groove 7 and the third groove 8 respectively It comes, so the depletion region can only extend downwards, therefore can guarantee the wider width of the depletion region, while depletion region Junction area is limited between the second groove 7 and the third groove 8, without horizontal area, therefore entire depletion region Area is smaller, so that the first diode a1 has the characteristic of ultra-low capacitance.The first diode a1 and institute at this time The second diode b1 series connection is stated, entire device is also just provided with the characteristic of ultra-low capacitance, and capacitance can be less than 0.1pF, than Traditional low-capacitance TVS device reduces 50% or more capacitor, therefore is more applicable in high speed signal port.Therefore, the present invention is real The Transient Voltage Suppressor for applying example offer can be by surge voltage clamper in a reduced levels, while having ultra-low capacitance pair again Signal transmission is lossless.

It should be noted that herein, relational terms such as first and second and the like are used merely to a reality Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that There is also other identical elements in process, method, article or equipment including the element.

It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right The limitation of claim and its full scope and equivalent.

Claims

1. a kind of Transient Voltage Suppressor characterized by comprising

The substrate of first conduction type；

The first buried layer and the second buried layer of first conduction type, first buried layer and second buried layer are located at described outer Prolong the two sides of layer；

First medium layer extends through the epitaxial layer and extends to the substrate, and be respectively formed in first buried layer and The two sides of second buried layer；

First injection region of the second conduction type is respectively formed in the upside of first buried layer and second buried layer；Second Second injection region of conduction type, is respectively formed between the first medium layer and the second dielectric layer and described Between one dielectric layer and the third dielectric layer；The third injection region of first conduction type, be formed in the second dielectric layer and Between the third dielectric layer；

The first metal layer and second metal layer, be respectively formed in the epitaxial layer upper surface and with first injection region and described The connection of second injection region；

2. Transient Voltage Suppressor according to claim 1, which is characterized in that first injection region is respectively with described One buried layer is connected with second buried layer.

3. Transient Voltage Suppressor according to claim 1, which is characterized in that second injection region and third note Enter area to connect with the epitaxial layer respectively.

4. Transient Voltage Suppressor according to claim 1, which is characterized in that first buried layer and second buried layer It is symmetrical arranged, the first medium layer is symmetrical arranged, and the second dielectric layer and the third dielectric layer are symmetrical arranged.

5. Transient Voltage Suppressor according to claim 1, which is characterized in that first buried layer and second buried layer Lower surface connect respectively with the substrate.

6. a kind of production method of Transient Voltage Suppressor comprising:

The substrate of first conduction type is provided；

The first buried layer and the second buried layer of the first conduction type, first buried layer and described second are formed in the epitaxial layer Buried layer is located at the two sides of the epitaxial layer；

The first groove of the substrate is formed through the epitaxial layer and extends to, the first groove is located at described first The two sides of buried layer and second buried layer, and first medium layer is formed in the first groove；

It is formed from the epitaxial layer upper surface and extends to second groove and third groove in the epitaxial layer, and described second Second dielectric layer and third dielectric layer are respectively formed in groove and the third groove；

The first injection region of the second conduction type is respectively formed on the upside of first buried layer and second buried layer；Described The second conduction is respectively formed between first groove and the second groove and between the first groove and the third groove Second injection region of type；The third injection of the first conduction type is formed between the second groove and the third groove Area；

Surface is respectively formed the first metal layer for connecting first injection region and second injection region on said epitaxial layer there And second metal layer；

7. a kind of production method of Transient Voltage Suppressor according to claim 6, which is characterized in that first injection Area is connect with first buried layer and second buried layer respectively.

8. a kind of production method of Transient Voltage Suppressor according to claim 6, which is characterized in that second injection Area and the third injection region are connect with the epitaxial layer respectively.

9. a kind of production method of Transient Voltage Suppressor according to claim 6, which is characterized in that first buried layer It is symmetrical arranged with second buried layer, the first medium layer is symmetrical arranged, the second dielectric layer and the third dielectric layer It is symmetrical arranged.

10. a kind of production method of Transient Voltage Suppressor according to claim 6, which is characterized in that described first buries The lower surface of layer and second buried layer is connect with the substrate respectively.