CN109813348B - A distributed optical fiber sensing system and its control method - Google Patents

A distributed optical fiber sensing system and its control method Download PDF

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CN109813348B
CN109813348B CN201910091098.9A CN201910091098A CN109813348B CN 109813348 B CN109813348 B CN 109813348B CN 201910091098 A CN201910091098 A CN 201910091098A CN 109813348 B CN109813348 B CN 109813348B
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digital signals
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CN109813348A (en
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喻强
吕立冬
张刚
张增华
王玮
虞跃
刘川
李炳林
郭经红
刘伟麟
吴鹏
陶静
黄在朝
张�浩
刘世栋
卜宪德
姚继明
郭云飞
邓辉
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State Grid Corp of China SGCC
State Grid Zhejiang Electric Power Co Ltd
Global Energy Interconnection Research Institute
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State Grid Zhejiang Electric Power Co Ltd
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Abstract

本发明涉及一种分布式光纤传感系统及其控制方法,所述系统包括:高速A/D并行采集单元、数字下变频器、并行累加平均器单元和信号提取与计算单元;所述高速A/D并行采集单元、数字下变频器、并行累加平均器单元和信号提取与计算单元依次连接。本发明提供的技术方案,减少了传统方案中多个外部功能模块引入的各种噪声干扰,增加了系统的集成度,大大缩短了信号分析的时间,从而提高了分布式光纤传感系统的稳定性与可靠性。

Figure 201910091098

The invention relates to a distributed optical fiber sensing system and its control method. The system includes: a high-speed A/D parallel acquisition unit, a digital down-converter, a parallel accumulative averager unit, and a signal extraction and calculation unit; the high-speed A/D The /D parallel acquisition unit, the digital down-converter, the parallel accumulative averager unit and the signal extraction and calculation unit are sequentially connected. The technical solution provided by the present invention reduces various noise interference introduced by multiple external functional modules in the traditional solution, increases the integration of the system, greatly shortens the time for signal analysis, and thus improves the stability of the distributed optical fiber sensing system sex and reliability.

Figure 201910091098

Description

一种分布式光纤传感系统及其控制方法A distributed optical fiber sensing system and its control method

技术领域technical field

本发明涉及分布式光纤传感技术领域,具体涉及一种分布式光纤传感系统及其控制方法。The invention relates to the technical field of distributed optical fiber sensing, in particular to a distributed optical fiber sensing system and a control method thereof.

背景技术Background technique

光纤不仅可以作为光波的传输媒质,而且当光波在光纤中传播时,表征光波的特征参量(振幅、相位、偏振态、波长等)因外界因素(如温度、压力、磁场、电场、位移等)的作用而间接或直接地发生变化,从而可将光纤用作传感元件来探测各种待测量(物理量、化学量和生物量等),这就是光纤传感器的基本原理。Optical fiber can not only be used as the transmission medium of light wave, but also when the light wave propagates in the optical fiber, the characteristic parameters (amplitude, phase, polarization state, wavelength, etc.) The role of the fiber can be changed indirectly or directly, so that the optical fiber can be used as a sensing element to detect various to be measured (physical quantity, chemical quantity and biomass, etc.), which is the basic principle of the fiber optic sensor.

现代信息技术是由信息的采集、传输和处理技术组成,因此传感器、通信和计算机技术成为信息技术的三大支柱。特别是当今社会已进入以光纤通信技术为主要特征的信息时代,光纤传感技术代表了新一代传感器的发展趋势。Modern information technology is composed of information collection, transmission and processing technology, so sensor, communication and computer technology have become the three pillars of information technology. In particular, today's society has entered the information age characterized by optical fiber communication technology, and optical fiber sensing technology represents the development trend of a new generation of sensors.

按照测量方式不同,光纤传感器分为点式和分布式两种。分布式光纤传感器具备提取大范围测量场的分布信息的能力,能够解决目前测量领域的众多难题。其中分布式光纤温度传感器可用于如大型电力变压器、高压电力网、高层建筑等大的或长的设备的温度分布测量和监控。随着基于布里渊散射的分布式光纤传感技术研究的不断深入,实时性、稳定性、可靠性好以及高精度的分布式传感系统将得到更大的发展。According to different measurement methods, fiber optic sensors are divided into point type and distributed type. Distributed optical fiber sensors have the ability to extract the distribution information of a large-scale measurement field, and can solve many problems in the current measurement field. Among them, the distributed optical fiber temperature sensor can be used for temperature distribution measurement and monitoring of large or long equipment such as large power transformers, high-voltage power grids, and high-rise buildings. With the continuous deepening of research on distributed optical fiber sensing technology based on Brillouin scattering, real-time, stable, reliable and high-precision distributed sensing systems will be further developed.

目前的分布式光纤传感技术,一次测量时间较长,若在多通道系统中,全部通道扫描一遍的周期就会更长,这样对传感系统的实时性就会产生较大影响;此外,由于信号处理模块采用分立元件搭建而成,且引入了额外的扫频模块,会给整个数字信号处理通道引入的外部噪声,从而使原本微弱的反射信号变的更难识别与判断。The current distributed optical fiber sensing technology takes a long time to measure once. If in a multi-channel system, the cycle of scanning all channels will be longer, this will have a greater impact on the real-time performance of the sensing system; in addition, Since the signal processing module is built with discrete components and an additional frequency sweep module is introduced, external noise will be introduced to the entire digital signal processing channel, making the original weak reflection signal more difficult to identify and judge.

发明内容Contents of the invention

针对现有技术的不足,本发明的目的是通过利用高速A/D并行采集单元、数字下变频器、并行累加平均器单元、信号提取与计算单元和控制单元构建分布式光纤传感系统,减少了传统方案中多个外部功能模块引入的各种噪声干扰,增加了系统的集成度,大大缩短了信号分析的时间,从而提高了分布式光纤传感系统的稳定性与可靠性。For the deficiencies in the prior art, the object of the invention is to construct a distributed optical fiber sensing system by utilizing a high-speed A/D parallel acquisition unit, a digital down-converter, a parallel accumulative averager unit, a signal extraction and calculation unit and a control unit, reducing It eliminates various noise interference introduced by multiple external functional modules in the traditional scheme, increases the integration of the system, greatly shortens the time of signal analysis, and thus improves the stability and reliability of the distributed optical fiber sensing system.

本发明的目的是采用下述技术方案实现的:The object of the present invention is to adopt following technical scheme to realize:

一种分布式光纤传感系统,其改进之处在于,所述系统包括:高速A/D并行采集单元、数字下变频器、并行累加平均器单元和信号提取与计算单元;A distributed optical fiber sensing system, which is improved in that the system includes: a high-speed A/D parallel acquisition unit, a digital down-converter, a parallel accumulative averager unit, and a signal extraction and calculation unit;

所述高速A/D并行采集单元、数字下变频器、并行累加平均器单元和信号提取与计算单元依次连接;The high-speed A/D parallel acquisition unit, digital down-converter, parallel accumulative averager unit and signal extraction and calculation unit are sequentially connected;

所述高速A/D并行采集单元,用于将接收的模拟电信号转换成4路不同相位的数字信号,将所述4路不同相位的数字信号按相位时序组合成一条串行采样流,并将所述串行采样流输出至所述数字下变频器;The high-speed A/D parallel acquisition unit is used to convert the received analog electrical signal into 4 digital signals of different phases, combine the 4 digital signals of different phases into a serial sampling stream according to phase timing, and outputting the serial sample stream to the digital down converter;

所述数字下变频器,用于将接收的串行采样流转换成多个并行的基带数字信号,并将所述多个并行的基带数字信号输出至所述并行累加平均器单元;The digital down converter is used to convert the received serial sampling stream into a plurality of parallel baseband digital signals, and output the plurality of parallel baseband digital signals to the parallel accumulative averager unit;

所述并行累加平均器单元,用于分别获取所述多个并行的基带数字信号中每个基带数字信号的平均值,并将所述多个并行的基带数字信号中每个基带数字信号的平均值输出至信号提取与计算单元;The parallel accumulative averager unit is used to separately obtain the average value of each baseband digital signal in the plurality of parallel baseband digital signals, and average the average value of each baseband digital signal in the plurality of parallel baseband digital signals The value is output to the signal extraction and calculation unit;

所述信号提取与计算单元,用于对所述多个并行的基带数字信号中每个基带数字信号的平均值进行快速傅里叶变换,获取所述多个并行基带数字信号中每个基带数字信号的平均值的频谱,并将所述多个并行基带数字信号中每个基带数字信号的平均值的频谱拟合成洛伦兹曲线。The signal extraction and calculation unit is configured to perform fast Fourier transform on the average value of each baseband digital signal in the plurality of parallel baseband digital signals, and obtain each baseband digital signal in the plurality of parallel baseband digital signals The frequency spectrum of the average value of the signal, and the frequency spectrum of the average value of each baseband digital signal in the plurality of parallel baseband digital signals is fitted to a Lorenz curve.

优选的,所述高速A/D并行采集单元,包括:放大电路、四个并联的ADC芯片、数字时钟管理模块和A/D采样值缓冲区;Preferably, the high-speed A/D parallel acquisition unit includes: an amplification circuit, four parallel ADC chips, a digital clock management module and an A/D sampling value buffer;

所述放大电路,用于对光电探测器提供的模拟电信号进行放大和滤波,并将放大和滤波后的模拟电信号分别传送到四个并行的ADC芯片;The amplifying circuit is used to amplify and filter the analog electrical signal provided by the photodetector, and transmit the amplified and filtered analog electrical signal to four parallel ADC chips respectively;

所述数字时钟管理模块,用于分别为四个并联的ADC芯片提供0度相位时钟信号、90度相位时钟信号、180度相位时钟信号和270度相位时钟信号;The digital clock management module is used to respectively provide a 0-degree phase clock signal, a 90-degree phase clock signal, a 180-degree phase clock signal and a 270-degree phase clock signal for four parallel ADC chips;

所述ADC芯片,用于若接收的时钟信号的相位为x度,则将相位为x度的放大和滤波后的模拟电信号转换为数字信号,其中,x为0、90、180或270;The ADC chip is used to convert the amplified and filtered analog electrical signal with a phase of x degrees into a digital signal if the phase of the received clock signal is x degrees, where x is 0, 90, 180 or 270;

所述A/D采样值缓冲区,用于将相位为0度、90度、180度和270度的数字信号按相位时序组合成一条串行采样流,并将所述串行采样流输出至所述数字下变频器。The A/D sampling value buffer is used to combine digital signals with phases of 0 degrees, 90 degrees, 180 degrees and 270 degrees into a serial sampling stream according to phase timing, and output the serial sampling stream to the digital downconverter.

进一步的,所述ADC芯片的采样率和分辨率分别为250MSPS和16bit;Further, the sampling rate and resolution of the ADC chip are 250MSPS and 16bit respectively;

所述ADC芯片的型号为AD9467-250或AD9652;The model of the ADC chip is AD9467-250 or AD9652;

所述数字时钟管理模块为Xilinx FPGA内部的PLL或DCM单元。The digital clock management module is a PLL or DCM unit inside the Xilinx FPGA.

优选的,所述并行累加平均器单元由m个累加平均器并联组成。Preferably, the parallel accumulative averager unit is composed of m accumulative averagers connected in parallel.

进一步的,所述数字下变频器,用于:Further, the digital down converter is used for:

对接收的串行采样流依次进行混频运算、FIR滤波运算和抽取运算,获取m个并行的基带数字信号,并将所述m个并行的基带数字信号分别输出至所述并行累加平均器单元中m个并行的累加平均器,其中,m为正整数且m>1。Perform frequency mixing operation, FIR filtering operation and extraction operation on the received serial sampling stream in sequence to obtain m parallel baseband digital signals, and output the m parallel baseband digital signals to the parallel accumulative averager unit respectively Among them, there are m parallel cumulative averagers, where m is a positive integer and m>1.

具体的,所述信号提取与计算单元,包括:m个FFT时频变换模块和洛伦兹曲线拟合及分析模块;Specifically, the signal extraction and calculation unit includes: m FFT time-frequency transformation modules and a Lorentz curve fitting and analysis module;

所述FFT时频变换模块,用于对所述m个并行基带数字信号中的1个基带数字信号的平均值进行快速傅里叶变换,获取该基带数字信号的平均值的频谱;The FFT time-frequency transformation module is used to perform fast Fourier transform on the average value of one baseband digital signal among the m parallel baseband digital signals, and obtain the frequency spectrum of the average value of the baseband digital signal;

所述洛伦兹曲线拟合及分析模块,用于将m个并行基带数字信号中每个基带数字信号的平均值的频谱拟合成洛伦兹曲线。The Lorentz curve fitting and analysis module is used to fit the frequency spectrum of the average value of each baseband digital signal in the m parallel baseband digital signals into a Lorentz curve.

具体的,所述FFT时频变换模块为Xilinx FPGA的FFT IP CORE;Specifically, the FFT time-frequency transformation module is the FFT IP CORE of Xilinx FPGA;

所述洛伦兹曲线拟合及分析单元的执行逻辑采用VHDL或Verilog语言编写。The execution logic of the Lorenz curve fitting and analysis unit is written in VHDL or Verilog language.

优选的,所述系统,还包括:控制单元;Preferably, the system further includes: a control unit;

所述控制单元分别与所述高速A/D并行采集单元、数字下变频器、并行累加平均器单元和信号提取与计算单元连接;The control unit is respectively connected with the high-speed A/D parallel acquisition unit, digital down-converter, parallel accumulative averager unit and signal extraction and calculation unit;

所述控制单元,用于控制高速A/D并行采集单元、数字下变频器、并行累加平均器单元和信号提取与计算单元的执行顺序。The control unit is used to control the execution sequence of the high-speed A/D parallel acquisition unit, the digital down-converter, the parallel cumulative averager unit and the signal extraction and calculation unit.

进一步的,所述控制单元,具体用于:Further, the control unit is specifically used for:

当高速A/D并行采集单元接收到模拟电信号时,控制高速A/D并行采集单元将接收的模拟电信号转换成4路不同相位的数字信号,将所述4路不同相位的数字信号按相位时序组合成一条串行采样流,并将所述串行采样流输出至所述数字下变频器;When the high-speed A/D parallel acquisition unit receives the analog electrical signal, the high-speed A/D parallel acquisition unit is controlled to convert the received analog electrical signal into 4 channels of digital signals with different phases, and the 4 channels of digital signals with different phases are converted into Combining phase timing into a serial sampling stream, and outputting the serial sampling stream to the digital down converter;

当数字下变频器接收到串行采样流时,控制数字下变频器将接收的采样流转换成多个并行的基带数字信号,并将所述多个并行的基带数字信号输出至所述并行累加平均器单元;When the digital down-converter receives the serial sampling stream, the digital down-converter is controlled to convert the received sampling stream into multiple parallel baseband digital signals, and output the multiple parallel baseband digital signals to the parallel accumulation Averager unit;

当并行累加平均器单元接收到多个并行的基带数字信号时,控制并行累加平均器单元分别获取所述多个并行的基带数字信号中每个基带数字信号的平均值,并将所述多个并行的基带数字信号中每个基带数字信号的平均值输出至信号提取与计算单元;When the parallel accumulative averager unit receives a plurality of parallel baseband digital signals, the parallel accumulative averager unit is controlled to obtain the average value of each baseband digital signal in the plurality of parallel baseband digital signals respectively, and the multiple The average value of each baseband digital signal in the parallel baseband digital signals is output to the signal extraction and calculation unit;

当所述信号提取与计算单元接收到多个并行的基带数字信号中每个基带数字信号的平均值时,控制信号提取与计算单元对所述多个并行的基带数字信号中每个基带数字信号的平均值进行快速傅里叶变换,获取所述多个并行基带数字信号中每个基带数字信号的平均值的频谱,并将所述多个并行基带数字信号中每个基带数字信号的平均值的频谱拟合成洛伦兹曲线。When the signal extraction and calculation unit receives the average value of each baseband digital signal in a plurality of parallel baseband digital signals, the control signal extraction and calculation unit controls each baseband digital signal in the plurality of parallel baseband digital signals Fast Fourier transform is performed on the average value of the multiple parallel baseband digital signals, and the frequency spectrum of the average value of each baseband digital signal in the multiple parallel baseband digital signals is obtained, and the average value of each baseband digital signal in the multiple parallel baseband digital signals is The spectrum is fitted to a Lorenz curve.

一种分布式光纤传感系统的控制方法,其改进之处在于,所述方法包括:A control method for a distributed optical fiber sensing system, the improvement is that the method includes:

S1.初始化迭代次数n=0,n∈[1,N];S1. The number of initialization iterations n=0, n∈[1,N];

S2.控制单元控制高速A/D并行采集单元将接收的模拟电信号转换成4路不同相位的数字信号,将所述4路不同相位的数字信号按相位时序组合成一条串行采样流,并将所述串行采样流输出至所述数字下变频器;S2. The control unit controls the high-speed A/D parallel acquisition unit to convert the received analog electrical signal into 4 digital signals of different phases, and combine the 4 digital signals of different phases into a serial sampling stream according to phase timing, and outputting the serial sample stream to the digital down converter;

S3.控制单元控制数字下变频器对接收的串行数字信号依次进行混频运算、FIR滤波运算和抽取运算,获取m个并行的基带数字信号,并将所述m个并行的基带数字信号分别输出至所述并行累加平均器单元中m个并行的累加平均器;S3. The control unit controls the digital down-converter to sequentially perform frequency mixing operation, FIR filtering operation and extraction operation on the received serial digital signal to obtain m parallel baseband digital signals, and separate the m parallel baseband digital signals output to m parallel cumulative averagers in the parallel cumulative averager unit;

其中,m为正整数且m>1;Wherein, m is a positive integer and m>1;

S4.控制单元判断迭代次数n是否等于N,若n等于N,则执行步骤S5;若n不等于N,则令n=n+1,并执行步骤S2;S4. The control unit judges whether the number of iterations n is equal to N, if n is equal to N, then execute step S5; if n is not equal to N, then make n=n+1, and execute step S2;

S5.控制单元控制并行累加平均器单元分别获取所述m个并行的基带数字信号中每个基带数字信号的平均值,并将所述m个并行的基带数字信号中每个基带数字信号的平均值输出至信号提取与计算单元;S5. The control unit controls the parallel accumulative averager unit to respectively obtain the average value of each baseband digital signal in the m parallel baseband digital signals, and average the average value of each baseband digital signal in the m parallel baseband digital signals The value is output to the signal extraction and calculation unit;

S6.控制单元控制信号提取与计算单元对所述m个并行的基带数字信号中每个基带数字信号的平均值进行快速傅里叶变换,获取所述m个并行基带数字信号中每个基带数字信号的平均值的频谱,并将所述m个并行基带数字信号中每个基带数字信号的平均值的频谱拟合成洛伦兹曲线。S6. The control unit controls the signal extraction and calculation unit to perform fast Fourier transform on the average value of each baseband digital signal in the m parallel baseband digital signals, and obtain each baseband digital signal in the m parallel baseband digital signals The frequency spectrum of the average value of the signal, and the frequency spectrum of the average value of each baseband digital signal in the m parallel baseband digital signals is fitted to a Lorenz curve.

与最接近的现有技术相比,本发明具有的有益效果:Compared with the closest prior art, the present invention has the beneficial effects:

本发明提供的技术方案,通过高速A/D并行采集单元、数字下变频器、并行累加平均器单元、信号提取与计算单元和控制单元构建分布式光纤传感系统,减少了传统方案中多个外部功能模块引入的各种噪声干扰,增加了系统的集成度,大大缩短了信号分析的时间,从而提高了分布式光纤传感系统的稳定性与可靠性;The technical scheme provided by the present invention constructs a distributed optical fiber sensing system through a high-speed A/D parallel acquisition unit, a digital down-converter, a parallel accumulative averager unit, a signal extraction and calculation unit, and a control unit, reducing multiple All kinds of noise interference introduced by external functional modules increase the integration of the system and greatly shorten the time of signal analysis, thus improving the stability and reliability of the distributed optical fiber sensing system;

本发明提供的技术方案,通过采用高速A/D并行采集单元和数字下变频器,可以对m个频段的信号可以进行一次采集后并行处理,将原来的处理时间缩短为1/m,从而大大缩短了信号提取时间。The technical solution provided by the present invention, by adopting a high-speed A/D parallel acquisition unit and a digital down-converter, the signals of m frequency bands can be processed in parallel after one acquisition, and the original processing time is shortened to 1/m, thereby greatly Reduced signal extraction time.

附图说明Description of drawings

图1是本发明实施例中一种分布式光纤传感系统的结构示意图;Fig. 1 is the structural representation of a kind of distributed optical fiber sensing system in the embodiment of the present invention;

图2是本发明实施例中一种分布式光纤传感系统中高速A/D并行采集单元、并行累加平均器单元和信号提取与计算单元的结构示意图;Fig. 2 is a schematic structural view of a high-speed A/D parallel acquisition unit, a parallel accumulative averager unit, and a signal extraction and calculation unit in a distributed optical fiber sensing system in an embodiment of the present invention;

图3是本发明实施例中一种分布式光纤传感系统的高速A/D并行采集单元中的放大电路的结构示意图;Fig. 3 is the structure schematic diagram of the amplifying circuit in the high-speed A/D parallel acquisition unit of a kind of distributed optical fiber sensing system in the embodiment of the present invention;

图4是本发明实施例中一种分布式光纤传感系统的高速A/D并行采集单元中的A/D采样值缓冲区的工作原理图;Fig. 4 is the working principle diagram of the A/D sampling value buffer in the high-speed A/D parallel acquisition unit of a kind of distributed optical fiber sensing system in the embodiment of the present invention;

图5是本发明实施例中一种分布式光纤传感系统中数字下变频器的结构示意图;5 is a schematic structural diagram of a digital downconverter in a distributed optical fiber sensing system in an embodiment of the present invention;

图6是本发明实施例中一种分布式光纤传感系统的另一种结构示意图;Fig. 6 is another schematic structural diagram of a distributed optical fiber sensing system in an embodiment of the present invention;

图7是本发明实施例中一种分布式光纤传感系统的控制方法的流程示意图。Fig. 7 is a schematic flowchart of a control method of a distributed optical fiber sensing system in an embodiment of the present invention.

具体实施方式Detailed ways

下面结合附图对本发明的具体实施方式作进一步的详细说明。The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.

为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

本发明提供了一种分布式光纤传感系统,如图1所示,所述系统包括:高速A/D并行采集单元、数字下变频器、并行累加平均器单元和信号提取与计算单元;The present invention provides a distributed optical fiber sensing system, as shown in Figure 1, the system includes: a high-speed A/D parallel acquisition unit, a digital down-converter, a parallel accumulative averager unit, and a signal extraction and calculation unit;

所述高速A/D并行采集单元、数字下变频器、并行累加平均器单元和信号提取与计算单元依次连接;The high-speed A/D parallel acquisition unit, digital down-converter, parallel accumulative averager unit and signal extraction and calculation unit are sequentially connected;

所述高速A/D并行采集单元,用于将接收的模拟电信号转换成4路不同相位的数字信号,将所述4路不同相位的数字信号按相位时序组合成一条串行采样流,并将所述串行采样流输出至所述数字下变频器;The high-speed A/D parallel acquisition unit is used to convert the received analog electrical signal into 4 digital signals of different phases, combine the 4 digital signals of different phases into a serial sampling stream according to phase timing, and outputting the serial sample stream to the digital down converter;

所述数字下变频器,用于将接收的串行采样流转换成多个并行的基带数字信号,并将所述多个并行的基带数字信号输出至所述并行累加平均器单元;The digital down converter is used to convert the received serial sampling stream into a plurality of parallel baseband digital signals, and output the plurality of parallel baseband digital signals to the parallel accumulative averager unit;

所述并行累加平均器单元,用于分别获取所述多个并行的基带数字信号中每个基带数字信号的平均值,并将所述多个并行的基带数字信号中每个基带数字信号的平均值输出至信号提取与计算单元;The parallel accumulative averager unit is used to separately obtain the average value of each baseband digital signal in the plurality of parallel baseband digital signals, and average the average value of each baseband digital signal in the plurality of parallel baseband digital signals The value is output to the signal extraction and calculation unit;

所述信号提取与计算单元,用于对所述多个并行的基带数字信号中每个基带数字信号的平均值进行快速傅里叶变换,获取所述多个并行基带数字信号中每个基带数字信号的平均值的频谱,并将所述多个并行基带数字信号中每个基带数字信号的平均值的频谱拟合成洛伦兹曲线。The signal extraction and calculation unit is configured to perform fast Fourier transform on the average value of each baseband digital signal in the plurality of parallel baseband digital signals, and obtain each baseband digital signal in the plurality of parallel baseband digital signals The frequency spectrum of the average value of the signal, and the frequency spectrum of the average value of each baseband digital signal in the plurality of parallel baseband digital signals is fitted to a Lorenz curve.

进一步的,如图2所示,所述高速A/D并行采集单元,包括:放大电路、四个并联的ADC芯片、数字时钟管理模块和A/D采样值缓冲区;Further, as shown in Figure 2, the high-speed A/D parallel acquisition unit includes: an amplification circuit, four parallel ADC chips, a digital clock management module and an A/D sampling value buffer;

所述放大电路,用于对光电探测器提供的模拟电信号进行放大和滤波,并将放大和滤波后的模拟电信号分别传送到四个并行的ADC芯片,例如,如图3所示;The amplifying circuit is used to amplify and filter the analog electrical signal provided by the photodetector, and transmit the amplified and filtered analog electrical signal to four parallel ADC chips, for example, as shown in Figure 3;

所述数字时钟管理模块,用于分别为四个并联的ADC芯片提供0度相位时钟信号、90度相位时钟信号、180度相位时钟信号和270度相位时钟信号;The digital clock management module is used to respectively provide a 0-degree phase clock signal, a 90-degree phase clock signal, a 180-degree phase clock signal and a 270-degree phase clock signal for four parallel ADC chips;

所述ADC芯片,用于若接收的时钟信号的相位为x度,则将相位为x度的放大和滤波后的模拟电信号转换为数字信号,其中,x为0、90、180或270;The ADC chip is used to convert the amplified and filtered analog electrical signal with a phase of x degrees into a digital signal if the phase of the received clock signal is x degrees, where x is 0, 90, 180 or 270;

所述A/D采样值缓冲区,用于将相位为0度、90度、180度和270度的数字信号按相位时序组合成一条串行采样流,并将所述串行采样流输出至所述数字下变频器;例如,如图4所示。The A/D sampling value buffer is used to combine digital signals with phases of 0 degrees, 90 degrees, 180 degrees and 270 degrees into a serial sampling stream according to phase timing, and output the serial sampling stream to The digital down converter; for example, as shown in FIG. 4 .

具体的,所述ADC芯片的采样率和分辨率分别为250MSPS和16bit;Specifically, the sampling rate and resolution of the ADC chip are 250MSPS and 16bit respectively;

所述ADC芯片的型号为AD9467-250或AD9652;The model of the ADC chip is AD9467-250 or AD9652;

所述数字时钟管理模块为Xilinx FPGA内部的PLL或DCM单元。The digital clock management module is a PLL or DCM unit inside the Xilinx FPGA.

进一步的,如图2所示,所述并行累加平均器单元由m个累加平均器并联组成。Further, as shown in FIG. 2 , the parallel accumulative averager unit is composed of m accumulative averagers connected in parallel.

进一步的,如图5所示,所述数字下变频器,用于:Further, as shown in Figure 5, the digital down converter is used for:

对接收的串行采样流依次进行混频运算、FIR滤波运算和抽取运算,获取m个并行的基带数字信号,并将所述m个并行的基带数字信号分别输出至所述并行累加平均器单元中m个并行的累加平均器,其中,m为正整数且m>1。Perform frequency mixing operation, FIR filtering operation and extraction operation on the received serial sampling stream in sequence to obtain m parallel baseband digital signals, and output the m parallel baseband digital signals to the parallel accumulative averager unit respectively Among them, there are m parallel cumulative averagers, where m is a positive integer and m>1.

进一步的,如图2所示,所述信号提取与计算单元,包括:m个FFT时频变换模块和洛伦兹曲线拟合及分析模块;Further, as shown in FIG. 2, the signal extraction and calculation unit includes: m FFT time-frequency transformation modules and a Lorentz curve fitting and analysis module;

所述FFT时频变换模块,用于对所述m个并行基带数字信号中的1个基带数字信号的平均值进行快速傅里叶变换,获取该基带数字信号的平均值的频谱;The FFT time-frequency transformation module is used to perform fast Fourier transform on the average value of one baseband digital signal among the m parallel baseband digital signals, and obtain the frequency spectrum of the average value of the baseband digital signal;

所述洛伦兹曲线拟合及分析模块,用于将m个并行基带数字信号中每个基带数字信号的平均值的频谱拟合成洛伦兹曲线。The Lorentz curve fitting and analysis module is used to fit the frequency spectrum of the average value of each baseband digital signal in the m parallel baseband digital signals into a Lorentz curve.

具体的,所述FFT时频变换模块为Xilinx FPGA的FFT IP CORE;Specifically, the FFT time-frequency transformation module is the FFT IP CORE of Xilinx FPGA;

所述洛伦兹曲线拟合及分析单元的执行逻辑采用VHDL或Verilog语言编写。The execution logic of the Lorenz curve fitting and analysis unit is written in VHDL or Verilog language.

优选的,如图6所示,所述系统,还包括:控制单元;Preferably, as shown in FIG. 6, the system further includes: a control unit;

所述控制单元分别与所述高速A/D并行采集单元、数字下变频器、并行累加平均器单元和信号提取与计算单元连接;The control unit is respectively connected with the high-speed A/D parallel acquisition unit, digital down-converter, parallel accumulative averager unit and signal extraction and calculation unit;

所述控制单元,用于控制高速A/D并行采集单元、数字下变频器、并行累加平均器单元和信号提取与计算单元的执行顺序。The control unit is used to control the execution sequence of the high-speed A/D parallel acquisition unit, the digital down-converter, the parallel cumulative averager unit and the signal extraction and calculation unit.

进一步的,所述控制单元,具体用于:Further, the control unit is specifically used for:

当高速A/D并行采集单元接收到模拟电信号时,控制高速A/D并行采集单元将接收的模拟电信号转换成4路不同相位的数字信号,将所述4路不同相位的数字信号按相位时序组合成一条串行采样流,并将所述串行采样流输出至所述数字下变频器;When the high-speed A/D parallel acquisition unit receives the analog electrical signal, the high-speed A/D parallel acquisition unit is controlled to convert the received analog electrical signal into 4 channels of digital signals with different phases, and the 4 channels of digital signals with different phases are converted into Combining phase timing into a serial sampling stream, and outputting the serial sampling stream to the digital down converter;

当数字下变频器接收到串行采样流时,控制数字下变频器将接收的采样流转换成多个并行的基带数字信号,并将所述多个并行的基带数字信号输出至所述并行累加平均器单元;When the digital down-converter receives the serial sampling stream, the digital down-converter is controlled to convert the received sampling stream into multiple parallel baseband digital signals, and output the multiple parallel baseband digital signals to the parallel accumulation Averager unit;

当并行累加平均器单元接收到多个并行的基带数字信号时,控制并行累加平均器单元分别获取所述多个并行的基带数字信号中每个基带数字信号的平均值,并将所述多个并行的基带数字信号中每个基带数字信号的平均值输出至信号提取与计算单元;When the parallel accumulative averager unit receives a plurality of parallel baseband digital signals, the parallel accumulative averager unit is controlled to obtain the average value of each baseband digital signal in the plurality of parallel baseband digital signals respectively, and the multiple The average value of each baseband digital signal in the parallel baseband digital signals is output to the signal extraction and calculation unit;

当所述信号提取与计算单元接收到多个并行的基带数字信号中每个基带数字信号的平均值时,控制信号提取与计算单元对所述多个并行的基带数字信号中每个基带数字信号的平均值进行快速傅里叶变换,获取所述多个并行基带数字信号中每个基带数字信号的平均值的频谱,并将所述多个并行基带数字信号中每个基带数字信号的平均值的频谱拟合成洛伦兹曲线。When the signal extraction and calculation unit receives the average value of each baseband digital signal in a plurality of parallel baseband digital signals, the control signal extraction and calculation unit controls each baseband digital signal in the plurality of parallel baseband digital signals Fast Fourier transform is performed on the average value of the multiple parallel baseband digital signals, and the frequency spectrum of the average value of each baseband digital signal in the multiple parallel baseband digital signals is obtained, and the average value of each baseband digital signal in the multiple parallel baseband digital signals is The spectrum is fitted to a Lorenz curve.

本实施例提供的技术方案,通过对传统的BOTDR系统中的布里渊信号检测与处理模块进行改进和优化,引入了软件无线电技术中的关键技术一数字下变频(DDC)技术,替代了传统的扫频模块,对m个频段的信号可以进行一次采集后并行处理,将原来的处理时间缩短为1/m,从而大大缩短了信号提取时间;The technical solution provided by this embodiment introduces the key technology in software radio technology - digital down conversion (DDC) technology by improving and optimizing the Brillouin signal detection and processing module in the traditional BOTDR system, replacing the traditional The frequency sweeping module can carry out parallel processing on the signals of m frequency bands once collected, shortening the original processing time to 1/m, thus greatly shortening the signal extraction time;

此外,通过引入利用数字时钟管理模块(DCM)以及在DDC模块中采用了全数字技术的DDS频率合成方法,对反射信号的处理全部采用数字手段,对传统方案中采用模拟加数字的信号处理方式进行了优化,有着频率分辨率高、频率转换时间短以及频率改变时,输出相位连续等显著优点。In addition, by introducing the digital clock management module (DCM) and the DDS frequency synthesis method using all-digital technology in the DDC module, all the processing of the reflected signal is by digital means, and the analog plus digital signal processing method is used in the traditional solution. It has been optimized and has significant advantages such as high frequency resolution, short frequency conversion time and continuous output phase when frequency changes.

本发明还提供一种分布式光纤传感系统的控制方法,如图7所示,所述方法包括:The present invention also provides a control method for a distributed optical fiber sensing system, as shown in FIG. 7, the method includes:

101.初始化迭代次数n=0,n∈[1,N];101. The number of initialization iterations n=0, n∈[1,N];

102.控制单元控制高速A/D并行采集单元将接收的模拟电信号转换成4路不同相位的数字信号,将所述4路不同相位的数字信号按相位时序组合成一条串行采样流,并将所述串行采样流输出至所述数字下变频器;102. The control unit controls the high-speed A/D parallel acquisition unit to convert the received analog electrical signal into 4 digital signals of different phases, and combine the 4 digital signals of different phases into a serial sampling stream according to phase timing, and outputting the serial sample stream to the digital down converter;

103.控制单元控制数字下变频器对接收的串行数字信号依次进行混频运算、FIR滤波运算和抽取运算,获取m个并行的基带数字信号,并将所述m个并行的基带数字信号分别输出至所述并行累加平均器单元中m个并行的累加平均器;103. The control unit controls the digital down-converter to sequentially perform frequency mixing operation, FIR filtering operation and extraction operation on the received serial digital signal to obtain m parallel baseband digital signals, and separate the m parallel baseband digital signals output to m parallel cumulative averagers in the parallel cumulative averager unit;

其中,m为正整数且m>1;Wherein, m is a positive integer and m>1;

104.控制单元判断迭代次数n是否等于N,若n等于N,则执行步骤105;若n不等于N,则令n=n+1,并执行步骤102;104. The control unit judges whether the number of iterations n is equal to N, if n is equal to N, then execute step 105; if n is not equal to N, then make n=n+1, and execute step 102;

105.控制单元控制并行累加平均器单元分别获取所述m个并行的基带数字信号中每个基带数字信号的平均值,并将所述m个并行的基带数字信号中每个基带数字信号的平均值输出至信号提取与计算单元;105. The control unit controls the parallel accumulative averager unit to respectively obtain the average value of each baseband digital signal in the m parallel baseband digital signals, and average the average value of each baseband digital signal in the m parallel baseband digital signals The value is output to the signal extraction and calculation unit;

106.控制单元控制信号提取与计算单元对所述m个并行的基带数字信号中每个基带数字信号的平均值进行快速傅里叶变换,获取所述m个并行基带数字信号中每个基带数字信号的平均值的频谱,并将所述m个并行基带数字信号中每个基带数字信号的平均值的频谱拟合成洛伦兹曲线。106. The control unit controls the signal extraction and calculation unit to perform fast Fourier transform on the average value of each baseband digital signal in the m parallel baseband digital signals, and obtain each baseband digital signal in the m parallel baseband digital signals The frequency spectrum of the average value of the signal, and the frequency spectrum of the average value of each baseband digital signal in the m parallel baseband digital signals is fitted to a Lorenz curve.

本领域内的技术人员应明白,本申请的实施例可提供为方法、系统、或计算机程序产品。因此,本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且,本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。Those skilled in the art should understand that the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器,使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。The present application is described with reference to flowcharts and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中,使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品,该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上,使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理,从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

最后应当说明的是:以上实施例仅用以说明本发明的技术方案而非对其限制,尽管参照上述实施例对本发明进行了详细的说明,所属领域的普通技术人员应当理解:依然可以对本发明的具体实施方式进行修改或者等同替换,而未脱离本发明精神和范围的任何修改或者等同替换,其均应涵盖在本发明的权利要求保护范围之内。Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the present invention can still be Any modifications or equivalent replacements that do not depart from the spirit and scope of the present invention shall fall within the protection scope of the claims of the present invention.

Claims (2)

1. A distributed fiber optic sensing system, comprising: the device comprises a high-speed A/D parallel acquisition unit, a digital down converter, a parallel accumulation averager unit and a signal extraction and calculation unit;
the high-speed A/D parallel acquisition unit, the digital down converter, the parallel accumulation averager unit and the signal extraction and calculation unit are sequentially connected;
the high-speed A/D parallel acquisition unit is used for converting received analog electric signals into 4 paths of digital signals with different phases, combining the 4 paths of digital signals with different phases into a serial sampling stream according to a phase time sequence, and outputting the serial sampling stream to the digital down converter;
the digital down converter is used for converting a received serial sampling stream into a plurality of parallel baseband digital signals and outputting the plurality of parallel baseband digital signals to the parallel accumulation averager unit;
the parallel accumulation averager unit is used for respectively acquiring the average value of each baseband digital signal in the plurality of parallel baseband digital signals and outputting the average value of each baseband digital signal in the plurality of parallel baseband digital signals to the signal extraction and calculation unit;
the signal extracting and calculating unit is configured to perform fast fourier transform on an average value of each baseband digital signal in the plurality of parallel baseband digital signals, obtain a spectrum of the average value of each baseband digital signal in the plurality of parallel baseband digital signals, and fit the spectrum of the average value of each baseband digital signal in the plurality of parallel baseband digital signals into a lorentzian curve;
the high-speed A/D parallel acquisition unit comprises: the device comprises an amplifying circuit, four ADC chips connected in parallel, a digital clock management module and an A/D sampling value buffer area;
the amplifying circuit is used for amplifying and filtering the analog electric signals provided by the photoelectric detector and respectively transmitting the amplified and filtered analog electric signals to four parallel ADC chips;
the digital clock management module is used for respectively providing a 0-degree phase clock signal, a 90-degree phase clock signal, a 180-degree phase clock signal and a 270-degree phase clock signal for the four ADC chips which are connected in parallel;
the ADC chip is used for converting the amplified and filtered analog electric signal with the phase of x degrees into a digital signal if the phase of the received clock signal is x degrees, wherein x is 0, 90, 180 or 270;
the A/D sampling value buffer area is used for combining digital signals with phases of 0 degree, 90 degrees, 180 degrees and 270 degrees into a serial sampling stream according to a phase sequence and outputting the serial sampling stream to the digital down converter;
the sampling rate and the resolution of the ADC chip are respectively 250MSPS and 16bit;
the model of the ADC chip is AD9467-250 or AD9652;
the digital clock management module is a PLL or DCM unit in the XilinxFPGA;
the parallel accumulation averager unit is formed by connecting m accumulation averagers in parallel;
the digital down converter is configured to:
sequentially performing frequency mixing operation, FIR filtering operation and extraction operation on a received serial sampling stream to obtain m parallel baseband digital signals, and respectively outputting the m parallel baseband digital signals to m parallel accumulation averagers in the parallel accumulation averager unit, wherein m is a positive integer and m is greater than 1;
the signal extraction and calculation unit comprises: m FFT time-frequency transformation modules and Lorentz curve fitting and analyzing modules;
the FFT time-frequency transformation module is used for carrying out fast Fourier transformation on the average value of 1 baseband digital signal in the m parallel baseband digital signals to obtain the frequency spectrum of the average value of the baseband digital signals;
the Lorentz curve fitting and analyzing module is used for fitting the frequency spectrum of the average value of each baseband digital signal in the m parallel baseband digital signals into a Lorentz curve;
the FFT time-frequency transformation module is FFTIPCORE of the XilinxFPGA;
the execution logic of the Lorentz curve fitting and analyzing unit is written by adopting VHDL or Verilog language;
the system, still include: a control unit;
the control unit is respectively connected with the high-speed A/D parallel acquisition unit, the digital down converter, the parallel accumulation averager unit and the signal extraction and calculation unit;
the control unit is used for controlling the execution sequence of the high-speed A/D parallel acquisition unit, the digital down converter, the parallel accumulation averager unit and the signal extraction and calculation unit;
the control unit is specifically configured to:
when the high-speed A/D parallel acquisition unit receives an analog electric signal, the high-speed A/D parallel acquisition unit is controlled to convert the received analog electric signal into 4 paths of digital signals with different phases, the 4 paths of digital signals with different phases are combined into a serial sampling stream according to a phase sequence, and the serial sampling stream is output to the digital down converter;
when the digital down converter receives the serial sampling stream, the digital down converter is controlled to convert the received sampling stream into a plurality of parallel baseband digital signals and output the plurality of parallel baseband digital signals to the parallel accumulation averager unit;
when the parallel accumulation averager unit receives a plurality of parallel baseband digital signals, the parallel accumulation averager unit is controlled to respectively obtain the average value of each baseband digital signal in the plurality of parallel baseband digital signals, and the average value of each baseband digital signal in the plurality of parallel baseband digital signals is output to the signal extraction and calculation unit;
when the signal extracting and calculating unit receives the average value of each baseband digital signal in the plurality of parallel baseband digital signals, the signal extracting and calculating unit is controlled to perform fast Fourier transform on the average value of each baseband digital signal in the plurality of parallel baseband digital signals, obtain the frequency spectrum of the average value of each baseband digital signal in the plurality of parallel baseband digital signals, and simulate the frequency spectrum of the average value of each baseband digital signal in the plurality of parallel baseband digital signals into a Lorentz curve.
2. A method of controlling a distributed fibre optic sensing system according to claim 1, the method comprising:
s1, initializing iteration times n =0, n belongs to [1, N ];
s2, the control unit controls the high-speed A/D parallel acquisition unit to convert the received analog electric signals into 4 paths of digital signals with different phases, the 4 paths of digital signals with different phases are combined into a serial sampling stream according to a phase sequence, and the serial sampling stream is output to the digital down converter;
s3, the control unit controls the digital down converter to sequentially perform frequency mixing operation, FIR filtering operation and extraction operation on the received serial digital signals to obtain m parallel baseband digital signals, and the m parallel baseband digital signals are respectively output to m parallel accumulation averagers in the parallel accumulation averager unit;
wherein m is a positive integer and m > 1;
s4, the control unit judges whether the iteration number N is equal to N, and if the iteration number N is equal to N, the step S5 is executed; if N is not equal to N, let N = N +1, and execute step S2;
s5, the control unit controls the parallel accumulation averager unit to respectively obtain the average value of each baseband digital signal in the m parallel baseband digital signals, and outputs the average value of each baseband digital signal in the m parallel baseband digital signals to the signal extraction and calculation unit;
and S6, the control unit controls the signal extraction and calculation unit to perform fast Fourier transform on the average value of each baseband digital signal in the m parallel baseband digital signals, so that the frequency spectrum of the average value of each baseband digital signal in the m parallel baseband digital signals is obtained, and the frequency spectrum of the average value of each baseband digital signal in the m parallel baseband digital signals is simulated into a Lorentz curve.
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