CN109801884A - A kind of IC semiconductor encapsulating structure and its manufacture craft - Google Patents
A kind of IC semiconductor encapsulating structure and its manufacture craft Download PDFInfo
- Publication number
- CN109801884A CN109801884A CN201811649990.6A CN201811649990A CN109801884A CN 109801884 A CN109801884 A CN 109801884A CN 201811649990 A CN201811649990 A CN 201811649990A CN 109801884 A CN109801884 A CN 109801884A
- Authority
- CN
- China
- Prior art keywords
- substrate
- packaging material
- plastic packaging
- encapsulating structure
- metallic circuit
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention relates to a kind of IC semiconductor encapsulating structure and its manufacture crafts, the encapsulating structure includes substrate (1), the substrate (1) includes multiple pins (2), area filling between pin (2) and pin (2) has the first plastic packaging material (3), the pin (2) includes interior pin (21) and outer pin (22), chip (4) are provided on the interior pin (21), chip (4) peripheral region is encapsulated with the second plastic packaging material (5), metal ball (7) are provided in the outer pin (22) at substrate (1) back side, the periphery of the metal ball (7) is provided with a corral dam (6) close to substrate (1) marginal position.The present invention provides a corral dam in welding semiconductor devices face, height is identical as device welding and assembling height, when semiconductor devices and PCB are assembled, box dam can be close to PCB and not stay gap, 5 face of device (upper surface and surrounding) and the baseplane PCB add up to 6 faces, form comprehensive shielding to semiconductor devices.
Description
Technical field
The present invention relates to a kind of IC semiconductor encapsulating structure and its manufacture crafts, belong to semiconductor packaging neck
Domain.
Background technique
The EMI shielding mode of semiconductor devices can only all accomplish the surrounding and upper surface screen of device in custom integrated circuit
It covers, can not be shielded with the bottom surface of PCB welding.In SMT assembling, semiconductor devices and PCB welding surface always exist
Gap, external interference can pass through gap and form interference to semiconductor device inside.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of IC semiconductor encapsulation for the above-mentioned prior art
Structure and its manufacture craft, it provides a corral dam in welding semiconductor devices face, highly identical as device welding and assembling height, when half
When conductor device and PCB are assembled, box dam can be close to pcb board, 5 face of semiconductor devices (upper surface and surrounding) and the baseplane PCB
Total 6 faces, form comprehensive shielding to semiconductor devices.
The present invention solves the above problems used technical solution are as follows: a kind of IC semiconductor encapsulating structure, it is wrapped
Substrate is included, the substrate includes metallic circuit, and the area filling between metallic circuit and metallic circuit has the first plastic packaging material, described
Metallic circuit includes internal wiring and outer pin, and chip is provided on the internal wiring, and the chip periphery region is encapsulated with
Second plastic packaging material is provided with metal ball in the outer pin of the substrate back, and the periphery of the metal ball is close to substrate edges position
It installs and is equipped with a corral dam.
Preferably, the box dam height is lower than the height of metal ball.
Preferably, first plastic packaging material, the second plastic packaging material and box dam lateral surface are provided with one layer of shielding gold by sputtering
Belong to layer.
Preferably, it is stainless steel that the shielding metal leve internal layer, which is copper, outer layer,.
A kind of manufacture craft of IC semiconductor encapsulating structure, the technique the following steps are included:
Step 1: taking a metal support plate；
Step 2: forming metallic circuit by plating on metal support plate surface, metallic circuit includes internal wiring and draws outside
Foot；
Step 3: the region between metallic circuit and metallic circuit is encapsulated using the first plastic packaging material；
Step 4: forming box dam by plating in the position where substrate back Cutting Road, the width of box dam is greater than cutting
The width in road；
Step 5: removal metal support plate；
Step 6: the pasting chip on internal wiring, chip is connect with electrical property of substrate, and carried out using the second plastic packaging material
Encapsulating, ball is planted in required position in outer pin；
Step 7: substrate is cut along Cutting Road, single product, the periphery of the back side tin ball of single product are formed
One corral dam is formed by cutting by the position of proximal edge, the lateral surface of box dam is exposed；
Step 8: forming one layer of shielding metal leve by sputtering in the first plastic packaging material, the second plastic packaging material and box dam lateral surface.
Preferably, the material of the metal support plate uses SPCC.
Preferably, step 2 and step 3, which are repeated as many times, forms multilager base plate.
Preferably, it is stainless steel that the shielding metal leve shielding metal leve in step 8, which is layers of copper outer layer for internal layer,.
Compared with the prior art, the advantages of the present invention are as follows:
1, box dam of the invention extends to outside substrate body, can reduce semiconductor package when being welded on pcb board
The gap of assembling structure and PCB, so that the shield effectiveness of semiconductor devices is more preferable；
2, box dam of the invention optionally with PCB is connected, and keeps device ground effect more preferable；
3, a corral dam at edge of the present invention can increase single intensity of product, improve the resistance to warping of entire encapsulating structure
Energy.
Detailed description of the invention
Fig. 1 is a kind of schematic diagram of IC semiconductor encapsulating structure of the present invention.
Fig. 2 is a kind of welding schematic diagram of IC semiconductor encapsulating structure of the present invention.
Fig. 3~Figure 10 is a kind of each process process signal of IC semiconductor encapsulating structure manufacture craft of the present invention
Figure.
Wherein:
Substrate 1
Metallic circuit 2
Internal wiring 21
Outer pin 22
First plastic packaging material 3
Chip 4
Second plastic packaging material 5
Box dam 6
Metal ball 7
Shielding metal leve 8
Pcb board 9
Tin cream 10.
Specific embodiment
The present invention will be described in further detail below with reference to the embodiments of the drawings.
Referring to Fig. 1, a kind of IC semiconductor encapsulating structure of the present invention, it includes substrate 1, the substrate 1
Including metallic circuit 2, the area filling between metallic circuit 2 and metallic circuit 2 has the first plastic packaging material 3, and the metallic circuit 2 wraps
Internal wiring 21 and outer pin 22 are included, chip 4 is provided on the internal wiring 21,4 peripheral region of chip is encapsulated with
Two plastic packaging materials 5 are provided with metal ball 7 in the outer pin 22 at 1 back side of substrate, and the periphery of the metal ball 7 is close to 1 side of substrate
Edge position is provided with a corral dam 6；
6 height of box dam is lower than the height of metal ball 7；
First plastic packaging material 3, the second plastic packaging material 5 and 6 lateral surface of box dam are provided with one layer of shielding metal leve by sputtering
8；
It is stainless steel that the internal layer of the shielding metal leve 8, which is copper outer layer,.
Referring to fig. 2, a kind of IC semiconductor encapsulating structure of the present invention is welded on pcb board 9, the metal
Ball 7 is electrically connected by tin cream 10 and pcb board 9, and the box dam 6 is above pcb board 9；
The box dam 6 passes through 10 grounding connection of tin cream with pcb board 9.
Its manufacture craft the following steps are included:
Step 1: taking a metal support plate referring to Fig. 3；
Step 2: referring to fig. 4, forming metallic circuit by plating on metal support plate surface, metallic circuit includes inner wire
Road and outer pin；
Step 3: the region between metallic circuit and metallic circuit is encapsulated using the first plastic packaging material referring to Fig. 5；
Step 4: forming box dam, the width of box dam by plating in the position where substrate back Cutting Road referring to Fig. 6
Greater than the width of Cutting Road；
Step 5: removing metal support plate referring to Fig. 7；
Step 6: referring to Fig. 8, chip is connect by the pasting chip on internal wiring with electrical property of substrate, and using the second modeling
Envelope material is encapsulated, and required position is implanted into tin ball in outer pin；
Step 7: cutting substrate along Cutting Road referring to Fig. 9, single product, the back side tin of single product are formed
The periphery of ball forms a corral dam by cutting by the position of proximal edge, and the lateral surface of box dam is exposed；
Step 8: forming one layer not by sputtering in the first plastic packaging material, the second plastic packaging material and box dam lateral surface referring to Figure 10
The layers of copper that the steel that becomes rusty is protected.
Multilager base plate can be made by repeating step 2 and step 3.
Outside above-described embodiment, the invention also includes have other embodiments, all use equivalent transformation or equivalent replacement sides
The technical solution that formula is formed, should all fall within the scope of the hereto appended claims.
Claims (7)
1. a kind of IC semiconductor encapsulating structure, it is characterised in that: it includes substrate (1), and the substrate (1) includes metal
Route (2), the area filling between metallic circuit (2) and metallic circuit (2) have the first plastic packaging material (3), the metallic circuit (2)
It including internal wiring (21) and outer pin (22), is provided with chip (4) on the internal wiring (21), chip (4) periphery
Region is encapsulated with the second plastic packaging material (5), is provided with metal ball (7), the metal in the outer pin (22) at substrate (1) back side
The periphery of ball (7) is provided with a corral dam (6) close to substrate (1) marginal position.
2. a kind of IC semiconductor encapsulating structure according to claim 1, it is characterised in that: the box dam (6) is high
Degree is lower than the height of metal ball (7).
3. a kind of IC semiconductor encapsulating structure according to claim 1, it is characterised in that: first plastic packaging material
(3), the second plastic packaging material (5) and box dam (6) lateral surface, which pass through to sputter, is provided with one layer of shielding metal leve (8).
4. a kind of IC semiconductor encapsulating structure according to claim 1, it is characterised in that: the shielding metal leve
(8) it is stainless steel that internal layer, which is copper outer layer,.
5. a kind of manufacture craft of IC semiconductor encapsulating structure, it is characterised in that the technique the following steps are included:
Step 1: taking a metal support plate；
Step 2: forming metallic circuit by plating on metal support plate surface, metallic circuit includes internal wiring and outer pin；
Step 3: the region between metallic circuit and metallic circuit is encapsulated using the first plastic packaging material；
Step 4: forming box dam by plating in the position where substrate back Cutting Road, the width of box dam is greater than Cutting Road
Width；
Step 5: removal metal support plate；
Step 6: the pasting chip on internal wiring, chip is connect with electrical property of substrate, and wrapped using the second plastic packaging material
Envelope, ball is planted in required position in outer pin；
Step 7: substrate is cut along Cutting Road, single product is formed, the periphery of the back side tin ball of single product is close
The position at edge forms a corral dam by cutting, and the lateral surface of box dam is exposed；
Step 8: forming one layer of shielding metal leve by sputtering in the first plastic packaging material, the second plastic packaging material and box dam lateral surface.
6. a kind of manufacture craft of IC semiconductor encapsulating structure according to claim 5, it is characterised in that: step
Two and step 3 be repeated as many times and form multilager base plate.
7. a kind of manufacture craft of IC semiconductor encapsulating structure according to claim 5, it is characterised in that: step
It is stainless steel that shielding metal leve internal layer in eight, which is copper outer layer,.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811649990.6A CN109801884A (en) | 2018-12-31 | 2018-12-31 | A kind of IC semiconductor encapsulating structure and its manufacture craft |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811649990.6A CN109801884A (en) | 2018-12-31 | 2018-12-31 | A kind of IC semiconductor encapsulating structure and its manufacture craft |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109801884A true CN109801884A (en) | 2019-05-24 |
Family
ID=66556963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811649990.6A Pending CN109801884A (en) | 2018-12-31 | 2018-12-31 | A kind of IC semiconductor encapsulating structure and its manufacture craft |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109801884A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298743A (en) * | 2016-10-20 | 2017-01-04 | 江苏长电科技股份有限公司 | Encapsulating structure with shield effectiveness and preparation method thereof |
| US20170280561A1 (en) * | 2016-03-24 | 2017-09-28 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Module with external shield and back-spill barrier for protecting contact pads |
-
2018
- 2018-12-31 CN CN201811649990.6A patent/CN109801884A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170280561A1 (en) * | 2016-03-24 | 2017-09-28 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Module with external shield and back-spill barrier for protecting contact pads |
| CN106298743A (en) * | 2016-10-20 | 2017-01-04 | 江苏长电科技股份有限公司 | Encapsulating structure with shield effectiveness and preparation method thereof |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190524 |
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| RJ01 | Rejection of invention patent application after publication |