CN109795980B - Method for manufacturing MEMS device - Google Patents
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- CN109795980B CN109795980B CN201910014732.9A CN201910014732A CN109795980B CN 109795980 B CN109795980 B CN 109795980B CN 201910014732 A CN201910014732 A CN 201910014732A CN 109795980 B CN109795980 B CN 109795980B
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Abstract
The invention discloses a manufacturing method of an MEMS device, which comprises the following steps: providing a first silicon wafer and forming a limiting structure and a bonding substrate layer; secondly, forming a dielectric layer side wall on the side face of the limiting structure and the side face of the bonding substrate layer; step three, forming a first bonding layer; step four, photoetching is carried out to form a first photoresist pattern, silicon etching is carried out to form a groove and a main body part of the MEMS device, and the first photoresist pattern has a structure that a central area is thinner than an edge area due to the side wall of the dielectric layer; step five, providing a second silicon wafer with a CMOS integrated circuit, wherein a top metal layer on the surface of the second silicon wafer is a second bonding layer; and step six, contacting the first bonding layer and the second bonding layer and carrying out eutectic bonding to form a eutectic bonding structure. The invention can enable the photoresist to simultaneously meet the requirements of smaller width of the groove and the requirements of protecting the edge area of the silicon wafer in the etching of the groove of the MEMS device.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a MEMS device.
Background
As shown in fig. 1A to fig. 1E, the present invention is a schematic device structure diagram in each step of a manufacturing method of a conventional MEMS device, and the conventional method includes the following steps:
as shown in fig. 1A, a silicon wafer 101 is provided.
As shown in fig. 1B, the silicon etching is performed to form a confinement structure (stopper)102 on the surface of the silicon wafer 101 and a bonding substrate layer 103, the positions of which are defined by the photolithography process. In fig. 1B, confinement structures 102 are disposed at both side edges of silicon wafer 101.
As shown in fig. 1C, germanium sidewalls 104 are formed on the sides of the confinement structure 102 and the bonded substrate layer 103. The germanium spacers 104 are formed on the sides of the confinement structure 102 and the bonded substrate layer 103 by depositing a germanium layer and performing a blanket etch self-alignment of the germanium.
As shown in fig. 1C, a first bonding layer 105 is formed on a surface of the bonding substrate layer 103. In the conventional method, the first bonding layer 105 is usually a germanium layer, and a structure only on the surface of the bonding substrate layer 103 is formed by depositing the germanium layer, performing photolithography to select a formation region, and performing etching.
As shown in fig. 1D, a main body portion 107 of the MEMS device is formed in the silicon wafer 101, and the main body portion 107 of the MEMS device includes a fixed electrode and a movable electrode with a trench 106 therebetween. The body portion 107 is formed by performing a silicon etch to form the trench 106, i.e., the region where the trench 106 is to be formed is selected by photolithography, and then the trench 106 is formed by etching, where the trench 106 needs to be etched through the silicon wafer 101.
As shown in fig. 1E, a silicon wafer 108 formed with a CMOS integrated circuit 109 is provided, and an interlayer film is formed on top of the CMOS integrated circuit 109 with a metal layer between the interlayer films, wherein a top metal layer (TM) is used as a second bonding layer, and the material of the top metal layer is usually aluminum.
Fig. 1E shows a situation when the first bonding layer 105 and the second bonding layer are just aligned and contacted, eutectic bonding between germanium and aluminum is subsequently required to form a eutectic bonding structure, and after the eutectic bonding is performed between the first bonding layer 105 and the second bonding layer, the silicon wafer 101 and the second silicon wafer 108 are bonded together and electrical connection is achieved. In eutectic bonding, the thickness of the first bonding layer 105 and the second bonding layer may gradually decrease, wherein the limiting structure 102 is to limit the minimum thickness of the first bonding layer 105 and the second bonding layer after bonding, that is, if the thickness of the first bonding layer 105 and the second bonding layer is too small, the surface of the limiting structure 102 will be pressed against the surface of the silicon wafer 108, so as to prevent the thickness of the first bonding layer 105 and the second bonding layer from further decreasing.
In fig. 1E, a bottom panel (BottomPlate) structure 110 is formed on the surface of the silicon wafer 108 at the bottom of the body portion 107, and a Pad structure 111 for leading-out terminals of the CMOS integrated circuit 109 is also included.
In the prior art method, in the step shown in fig. 1B, the height of the limiting structure 102 is typically 2 to 3 microns, so that the etching amount for silicon etching is 2 to 3 microns.
In the prior art method, the germanium sidewalls 104 may have an adverse effect on the step of forming the trench 106 shown in fig. 1D. The reason is that in the formation region of the lithographically defined trench 106, the photoresist may cross over the confinement structure 102 and the germanium sidewall 104 on the side thereof at the edge of the silicon wafer 101, and the photoresist may easily form a thinner photoresist on the side of the confinement structure 102 during the process of jumping over the germanium sidewall 104. If the thickness of the photoresist on the side of the limiting structure 102 is too thin, germanium damage is easily generated in the subsequent deep silicon etching, that is, the germanium sidewall 104 is etched due to weak protection capability of the photoresist, the germanium etching may cause heavy polymer, and the heavy polymer may affect the etching cavity, that is, the etching cavity may be contaminated and further may contaminate the product. Therefore, to prevent germanium damage, the thickness of the photoresist needs to be increased.
However, the thickness of the photoresist is also required to meet the line width requirement of the trench 106, and is usually set according to the minimum feature size (CD) of the trench 106, and the smaller the CD, the thinner the photoresist thickness. Therefore, in the existing method, the requirement of the germanium sidewall 104 for the thicker photoresist is opposite to the requirement of the smaller CD of the trench 106 for the thinner photoresist, so that the product requirement is often not realized.
Disclosure of Invention
The invention aims to solve the technical problem of providing a manufacturing method of an MEMS device, which can enable photoresist to simultaneously meet the requirement of smaller width of a groove and the requirement of protecting the edge area of a silicon wafer in the etching of the groove of the MEMS device, can improve the product performance and simultaneously avoid polluting an etching cavity.
In order to solve the above technical problem, the method for manufacturing the MEMS device provided by the present invention comprises the following steps:
step one, providing a first silicon wafer, defining a forming area of a limiting structure and a bonding substrate layer through photoetching, and then performing silicon etching to form the limiting structure and the bonding substrate layer.
And secondly, depositing a first dielectric layer and comprehensively etching the first dielectric layer to form dielectric layer side walls on the side surfaces of the limiting structures and the side surfaces of the bonding substrate layer.
And step three, forming a first bonding layer on the top surface of the bonding substrate layer.
And fourthly, photoetching to form a first photoresist pattern, and carrying out silicon etching by taking the first photoresist pattern as a mask to form a groove in the first silicon wafer so as to form a main body part of the MEMS device, wherein the main body part comprises a fixed electrode and a movable electrode, and the groove is arranged between the fixed electrode and the movable electrode.
The main body part is located in the central area of the first silicon wafer, and the limiting structure is located on the outer sides of the bonding substrate layer and the main body part and located in the edge area of the first silicon wafer.
The thickness of the first photoresist pattern in the edge area of the first silicon wafer is increased through the dielectric layer side wall on the side face of the limiting structure, so that the first photoresist pattern has a structure that the central area is thinner than the edge area, the thickness of the dielectric layer side wall of the limiting structure combined with the thickness of the edge area of the first photoresist pattern meets the protection of the edge area of the first silicon wafer in the silicon etching, and the thickness of the central area of the first photoresist pattern meets the requirement of the minimum width of the groove.
Providing a second silicon wafer, wherein a CMOS integrated circuit is formed on the second silicon wafer, a plurality of layers of interlayer films are formed on the top of the CMOS integrated circuit, and a metal layer is arranged between each layer of interlayer film; and the top metal layer on the surface of the second silicon wafer is a second bonding layer.
Step six, contacting the first bonding layer and the second bonding layer and carrying out eutectic bonding to form a eutectic bonding structure; the thickness of the first bonding layer and the second bonding layer is reduced in a eutectic bonding process, and the limiting structure is used for limiting the minimum thickness of the eutectic bonding structure.
In a further improvement, the first dielectric layer is made of an oxide layer.
The further improvement is that the thickness and the side surface inclination angle of the dielectric layer side wall can be adjusted, and the adjusting method comprises the following steps: splitting the first medium layer with the required thickness into a plurality of first medium sublayers, sequentially depositing each first medium sublayer, performing one-time overall etching after the deposition of each first medium sublayer is finished to form sub-side walls corresponding to the first medium sublayers, and forming the medium layer side walls by overlapping the sub-side walls.
In a further improvement, the height of the confinement structure is between 2 microns and 3 microns.
In a further improvement, the material of the top metal layer is aluminum.
In a further improvement, the process conditions of eutectic bonding in the sixth step include: the temperature is 400 ℃, and the pressure is 20 kN-40 kN.
In a further improvement, a bottom panel structure is formed on the surface of the second silicon wafer and is positioned at the bottom of the main body part, and the second silicon wafer further comprises a leading-out terminal pad structure for leading out a CMOS integrated circuit.
The further improvement is that the third step comprises the following steps:
and forming a first bonding layer on the surface of the first silicon wafer.
And photoetching and etching the first bonding layer, wherein the etched first bonding layer is formed on the top surface of the bonding substrate layer.
In a further refinement, the first bonding layer comprises a germanium layer.
After the limiting structure and the bonding substrate layer are etched and formed and before the first bonding layer is formed, a forming process of a dielectric layer side wall is carried out on the side face of the limiting structure and the side face of the bonding substrate layer, and the germanium side wall in the existing method is replaced by the dielectric layer side wall; therefore, the thickness of the photoresist corresponding to the groove etching can be completely set according to the requirement of the minimum width of the groove in the central area, namely the minimum CD, so that the requirement of a product can be met.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1E are schematic views of a device structure at various steps of a method of fabricating a prior art MEMS device;
FIG. 2 is a flow chart of a method of fabricating a MEMS device according to an embodiment of the present invention;
fig. 3A-3F are schematic views of device structures in steps of a method of fabricating a MEMS device according to an embodiment of the invention.
Detailed Description
Fig. 2 is a flowchart of a method for manufacturing a MEMS device according to an embodiment of the present invention, and fig. 3A to 3F are schematic diagrams of a device structure in each step of the method for manufacturing a MEMS device according to an embodiment of the present invention, and the method for manufacturing a MEMS device according to an embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, a first silicon wafer 1 is provided.
As shown in fig. 3B, the forming regions of the limiting structure 2 and the bonding substrate layer 3 are defined by photolithography, and then silicon etching is performed to form the limiting structure 2 and the bonding substrate layer 3.
In the embodiment of the present invention, the height of the confinement structure 2 is 2 to 3 micrometers.
Step two, as shown in fig. 3C, depositing a first dielectric layer and performing overall etching on the first dielectric layer to form dielectric layer side walls 4 on the side surfaces of the limiting structures 2 and the side surfaces of the bonding substrate layer 3.
In the embodiment of the invention, the first dielectric layer is made of an oxide layer.
The thickness and the side surface inclination angle of the dielectric layer side wall 4 can be adjusted, and the adjusting method comprises the following steps: splitting the first medium layer with the required thickness into a plurality of first medium sublayers, sequentially depositing each first medium sublayer, performing one-time overall etching after the deposition of each first medium sublayer is finished to form sub-side walls corresponding to the first medium sublayers, and forming the medium layer side walls 4 by overlapping the sub-side walls. Namely: in the embodiment of the invention, the thickness and the angle of the side wall are adjusted by adopting multiple times of deposition, namely deposition- > etching- > deposition- > etching.
And step three, as shown in fig. 3D, forming a first bonding layer 5 on the top surface of the bonding substrate layer 3.
The third step comprises the following steps:
a first bonding layer 5 is formed on the surface of the first silicon wafer 1. The first bonding layer 5 comprises a germanium layer.
And photoetching and etching the first bonding layer 5, wherein the etched first bonding layer 5 is formed on the top surface of the bonding substrate layer 3.
Step four, as shown in fig. 3E, performing photolithography to form a first photoresist pattern, performing silicon etching with the first photoresist pattern as a mask to form a trench 6 in the first silicon wafer 1, thereby forming a main body portion 7 of the MEMS device, where the main body portion 7 includes a fixed electrode and a movable electrode, and the trench 6 is spaced between the fixed electrode and the movable electrode.
The main body part 7 is located in the central region of the first silicon wafer 1, and the confinement structure 2 is located outside the bonded substrate layer 3 and the main body part 7 and in the edge region of the first silicon wafer 1.
The thickness of the first photoresist pattern in the edge region of the first silicon wafer 1 is increased through the dielectric layer side wall 4 on the side face of the limiting structure 2, so that the first photoresist pattern has a structure that the central region is thinner than the edge region, the thickness of the dielectric layer side wall 4 of the limiting structure 2 combined with the edge region of the first photoresist pattern meets the protection of the edge region of the first silicon wafer 1 in the silicon etching, and the thickness of the central region of the first photoresist pattern meets the requirement of the minimum width of the groove 6.
Step five, as shown in fig. 3F, providing a second silicon wafer 8, forming a CMOS integrated circuit 9 on the second silicon wafer 8, forming a plurality of layers of interlayer films on the top of the CMOS integrated circuit 9, and forming a metal layer between each layer of interlayer film; the top metal layer on the surface of the second silicon wafer 8 is a second bonding layer.
The top metal layer is made of aluminum.
A bottom panel structure 10 located at the bottom of the main body part 7 and a terminal pad structure 11 for leading out the CMOS integrated circuit 9 are also formed on the surface of the second silicon wafer 8.
Step six, contacting the first bonding layer 5 and the second bonding layer and carrying out eutectic bonding to form a eutectic bonding structure; the thickness of the first bonding layer 5 and the second bonding layer is reduced during eutectic bonding, and the limiting structure 2 is used for limiting the minimum thickness of the eutectic bonding structure.
The process conditions of eutectic bonding comprise: the temperature is 400 ℃, and the pressure is 20 kN-40 kN.
After the limiting structure 2 and the bonding substrate layer 3 are etched and formed and before the first bonding layer 5 is formed, the forming process of the dielectric layer side wall 4 is carried out on the side face of the limiting structure 2 and the side face of the bonding substrate layer 3, the germanium side wall in the existing method is replaced by the dielectric layer side wall 4, the thickness of the photoresist in the edge area of the first silicon wafer 1 can be improved in the subsequent etching of the groove 6 of the main body part 7 of the MEMS device, the thinner photoresist generated in the process that the photoresist climbs the climbing slope of the limiting structure 2 cannot bring adverse effects to the etching of the groove 6, and the medium of the dielectric layer side wall 4 can also be used as a mask for silicon etching; therefore, the thickness of the photoresist corresponding to the etching of the groove 6 in the embodiment of the invention can be completely set according to the requirement of the minimum width, namely the minimum CD, of the groove 6 in the central area, so that the requirement of a product can be met, therefore, the embodiment of the invention can enable the photoresist to simultaneously meet the requirement of the smaller width of the groove 6 and the requirement of protecting the edge area of a silicon wafer in the etching of the groove 6 of the MEMS device, can improve the product performance and simultaneously avoid polluting an etching cavity.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (9)
1. A method of fabricating a MEMS device, comprising the steps of:
step one, providing a first silicon wafer, defining a forming area of a limiting structure and a bonding substrate layer through photoetching, and then performing silicon etching to form the limiting structure and the bonding substrate layer;
depositing a first dielectric layer and comprehensively etching the first dielectric layer to form a dielectric layer side wall on the side surface of the limiting structure and the side surface of the bonding substrate layer;
step three, forming a first bonding layer on the top surface of the bonding substrate layer;
step four, photoetching is carried out to form a first photoresist pattern, silicon etching is carried out by taking the first photoresist pattern as a mask to form a groove in the first silicon wafer, and a main body part of the MEMS device is formed, wherein the main body part comprises a fixed electrode and a movable electrode, and the groove is arranged between the fixed electrode and the movable electrode;
the main body part is positioned in the central area of the first silicon wafer, and the limiting structure is positioned on the bonding substrate layer and the outer side of the main body part and positioned in the edge area of the first silicon wafer;
increasing the thickness of the first photoresist pattern in the edge region of the first silicon wafer through the dielectric layer side wall on the side surface of the limiting structure so that the first photoresist pattern has a structure that the central region is thinner than the edge region, wherein the thickness of the dielectric layer side wall of the limiting structure combined with the edge region of the first photoresist pattern meets the protection of the edge region of the first silicon wafer in the silicon etching, and the thickness of the central region of the first photoresist pattern meets the requirement of the minimum width of the groove;
providing a second silicon wafer, wherein a CMOS integrated circuit is formed on the second silicon wafer, a plurality of layers of interlayer films are formed on the top of the CMOS integrated circuit, and a metal layer is arranged between each layer of interlayer film; the top metal layer on the surface of the second silicon wafer is a second bonding layer;
step six, contacting the first bonding layer and the second bonding layer and carrying out eutectic bonding to form a eutectic bonding structure; the thickness of the first bonding layer and the second bonding layer is reduced in a eutectic bonding process, and the limiting structure is used for limiting the minimum thickness of the eutectic bonding structure.
2. The method of manufacturing a MEMS device of claim 1, wherein: the first dielectric layer is made of an oxide layer.
3. A method of manufacturing a MEMS device according to claim 1 or 2, wherein: the thickness and the side surface inclination angle of the dielectric layer side wall can be adjusted, and the adjusting method comprises the following steps: splitting the first medium layer with the required thickness into a plurality of first medium sublayers, sequentially depositing each first medium sublayer, performing one-time overall etching after the deposition of each first medium sublayer is finished to form sub-side walls corresponding to the first medium sublayers, and forming the medium layer side walls by overlapping the sub-side walls.
4. The method of manufacturing a MEMS device of claim 1, wherein: the height of the limiting structure is 2-3 microns.
5. The method of manufacturing a MEMS device of claim 1, wherein: the top metal layer is made of aluminum.
6. The method of manufacturing a MEMS device of claim 5, wherein: the process conditions of eutectic bonding in the sixth step comprise: the temperature is 400 ℃, and the pressure is 20 kN-40 kN.
7. The method of manufacturing a MEMS device of claim 1, wherein: and a bottom panel structure positioned at the bottom of the main body part and a leading-out terminal pad structure used for leading out the CMOS integrated circuit are also formed on the surface of the second silicon wafer.
8. The method of manufacturing a MEMS device of claim 1, wherein: the third step comprises the following steps:
forming a first bonding layer on the surface of the first silicon wafer;
and photoetching and etching the first bonding layer, wherein the etched first bonding layer is formed on the top surface of the bonding substrate layer.
9. The method of manufacturing a MEMS device of claim 8, wherein: the first bonding layer includes a germanium layer.
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Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2018113679A (en) * | 2016-12-02 | 2018-07-19 | スカイワークス ソリューションズ, インコーポレイテッドSkyworks Solutions, Inc. | Method for manufacturing electronic device formed in cavity between boards and including vias |
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| CN1691313A (en) * | 2001-05-31 | 2005-11-02 | 松下电器产业株式会社 | Power module and method of manufacturing the same |
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