CN109792498A - Analog to digital conversion circuit, imaging sensor and D conversion method - Google Patents
Analog to digital conversion circuit, imaging sensor and D conversion method Download PDFInfo
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- CN109792498A CN109792498A CN201880002863.9A CN201880002863A CN109792498A CN 109792498 A CN109792498 A CN 109792498A CN 201880002863 A CN201880002863 A CN 201880002863A CN 109792498 A CN109792498 A CN 109792498A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
Abstract
Present disclose provides a kind of analog to digital conversion circuit, imaging sensor and D conversion methods.Analog-digital conversion circuit as described includes comparison circuit, the first counter, charge accumulation circuitry, discharge circuit and the second counter.The comparison circuit compares analog signal and ramp signal, and the analog signal and the ramp signal add predetermined migration.First counter counts the number of cycles of clock signal when the signal level of the analog signal is greater than the signal level of the ramp signal.The charge accumulation circuitry accumulates the charge from the first electric current when the signal level that the signal level of the analog signal is less than the ramp signal adds the predetermined migration.During first counter stops counting, the discharge circuit discharges accumulated charge with the second electric current.During charge release, second counter counts the number of cycles of the clock signal.Analog-digital conversion circuit as described has the effect of economize on electricity.
Description
Technical field
This disclosure relates to modulus conversion technique, more particularly to it is a kind of for the progress modulus turn of analog signal caused by pixel
The analog to digital conversion circuit and its relevant imaging sensor and D conversion method changed.
Background technique
The needs of in order to meet high-resolution and high speed imaging, usual complement metal oxide semiconductor image sensor
(CMOS image sensor, CIS) has used column parallel A/D transformational structure (column-parallel ADC
Architecture) signal caused by pixel is acquired and converted.Due to monocline analog-digital converter (single
Slope ADC) can satisfy small size pixel design, column parallel A/D transformational structure almost by monocline analog-digital converter come reality
It applies.However, as image resolution ratio further increases, not only the conversion speed of monocline analog-digital converter be unable to satisfy high speed at
The power consumption of the demand of picture, the counter of monocline analog-digital converter is consequently increased.
Therefore, it is necessary to a kind of analog-to-digital conversion structures of innovation, can meet high-resolution, high speed imaging, small size simultaneously
Pixel design and the demand of low power consumption.
Summary of the invention
The first purpose of the disclosure is to provide a kind of mould for carrying out analog signal caused by pixel analog-to-digital conversion
Number conversion circuit and its relevant imaging sensor and D conversion method, to solve the above problems.
One embodiment of the disclosure provides a kind of analog to digital conversion circuit.Analog-digital conversion circuit as described is used for analog signal
Be converted to digital signal.Analog-digital conversion circuit as described includes comparison circuit, the first counter, charge accumulation circuitry, discharge circuit
And second counter.The comparison circuit making comparisons the analog signal and ramp signal to generate first compared with letter
Number, and the analog signal is made comparisons with the ramp signal plus predetermined migration to generate the second comparison signal.It is described
First counter is coupled to the comparison circuit, to indicate the signal electricity of the analog signal in first comparison signal
When the flat signal level for being greater than the ramp signal, the number of cycles of clock signal is counted to obtain the digital signal
First part.The charge accumulation circuitry is coupled to the comparison circuit, to indicate institute in first comparison signal
The signal level for stating analog signal is greater than the signal level of the ramp signal, and second comparison signal indicates the mould
When the signal level that the signal level of quasi- signal is less than the ramp signal adds the predetermined migration, in the charge accumulation electricity
The charge from the first electric current is accumulated at the charge accumulation end on road.The discharge circuit is coupled to the charge accumulation end, to
During first counter stops counting, discharged with the second electric current the charge accumulation end, wherein second electric current
Less than first electric current.Second counter is coupled to the charge accumulation circuitry, to put at the charge accumulation end
During electricity, the number of cycles of the clock signal is counted to obtain the second part of the digital signal.
One embodiment of the disclosure provides a kind of imaging sensor.Described image sensor includes pixel array, control
Circuit and at least an analog to digital conversion circuit.The pixel array includes the multiple pixels for being arranged in multirow and multiple row.The control
Circuit processed is to generate clock signal and ramp signal.An at least analog to digital conversion circuit be coupled to the pixel array with
The control circuit, analog signal caused by a column pixel in the pixel array is converted to digital signal.
One embodiment of the disclosure provides a kind of D conversion method.The D conversion method the following steps are included:
Analog signal is made comparisons with ramp signal to generate the first comparison signal；The analog signal and the ramp signal are added
Predetermined migration is made comparisons to generate the second comparison signal；The signal electricity of the analog signal is indicated in first comparison signal
When the flat signal level for being greater than the ramp signal, the number of cycles of clock signal is counted to obtain the first count value；
Indicate that the signal level of the analog signal is greater than the signal level of the ramp signal, and institute in first comparison signal
It states the second comparison signal and indicates that the signal level of the analog signal is less than the signal level of the ramp signal plus described
When predetermined migration, the charge from the first electric current is accumulated at charge accumulation end；Stop accumulation at the charge accumulation end and comes from institute
It during the charge for stating the first electric current, is discharged with the second electric current the charge accumulation end, wherein second electric current is less than institute
State the first electric current；And the charge accumulation end discharge during, to the number of cycles of the clock signal counted with
Obtain the second count value, wherein first count value and second count value respectively as digital signal first part and
Second part.
Detailed description of the invention
Fig. 1 is the function box schematic diagram of an embodiment of disclosure imaging sensor.
One Fig. 2 shows multiple analog to digital conversion circuits shown in FIG. 1 at least analog to digital conversion circuit therein is specific real
Apply the schematic diagram of mode.
Fig. 3 is the schematic diagram of an embodiment of analog to digital conversion circuit shown in Fig. 2.
Fig. 4 is the signal timing diagram of an embodiment of signal processing operations involved in analog to digital conversion circuit shown in Fig. 3.
Fig. 5 is the flow chart of an embodiment of disclosure D conversion method.
Wherein, the reference numerals are as follows:
100 imaging sensors
102 pixel arrays
110 control circuits
The analog to digital conversion circuit of 120_1-120_K, 220,320
232,332 first comparator
234,334 second comparator
240,340 first counter
250,350 charge accumulation circuitry
260,360 discharge circuit
270,370 second counter
352 ON-OFF control circuits
354 charge accumulation units
356 comparators
502-512 step
P11-PMKPixel
A11, A21 and door
A31 first and door
A32 second and door
A33 third and door
A34 the 4th and door
I1, I2 phase inverter
DF11-DF19, DF21-DF23 d type flip flop
D data input pin
Q data output end
Q' oppisite phase data output end
R reset terminal
TCA charge accumulation end
S1 first switch
S2 second switch
S3 third switch
S4 the 4th is switched
S5 the 5th is switched
S6 the 6th is switched
SD switch
CS1, CS2 current source
TI1 first input end
The second input terminal of TI2
TO output end
Nref reference mode
CLK clock signal
VR ramp signal
VA1-VAK, VA analog signal
Vos predetermined migration
VD1, VD digital signal
The first comparison signal of CP1
The second comparison signal of CP2
The first count value of CV_C
The second count value of CV_F
CP2b inversion signal
The first input clock signal of CKD1
The second input clock signal of CKD2
EN begins can signal
T1-t6 time point
The first reset signal of rstb1
The second reset signal of rstb2
V1, V2, Vr signal level
Qp first switch controls signal
Qn second switch controls signal
Q1g third switch control signal
The 4th switch control signal of qn1g
The first inverted control signal of qp '
The second inverted control signal of qn '
Specific embodiment
Specification and before claims in used some vocabulary and censure specific component.This field
Technical staff is, it is to be appreciated that manufacturer may call same component with different nouns.This specification and power before
Sharp claim is not in such a way that the difference of title is as component is distinguished, but with the difference of component functionally as area
The benchmark divided.Specification in the whole text and before claims when mentioned in "comprising" be an open term, therefore
It should be construed to " including but not limited to ".In addition, " coupling " word includes any electrical connection means directly or indirectly herein.Cause
This, if it is described herein that a first device is coupled to a second device, then represent the first device can directly be electrically connected to it is described
Second device, or it is electrically connected to the second device indirectly by other devices or connection means.
Fig. 1 is the function box schematic diagram of an embodiment of disclosure imaging sensor.In this embodiment, image sensing
Device 100 can be used column parallel A/D transformational structure to carry out analog-to-digital conversion operation to transducing signal, and may include (but being not limited to)
One pixel array 102, a control circuit 110 and multiple analog to digital conversion circuits (are labeled as " ADC ") 120_1-120_K, wherein K
It is greater than 1 positive integer.Pixel array 102 may include multiple pixels (or pixel unit) P for being arranged in M row and K column11-PMK,
Wherein M is greater than 1 positive integer, each pixel P11-PMKCan carrying out image sensing respectively, (such as one passes to generate an analog signal
Electrification pressure or a sense current).
Control circuit 110 can produce a clock signal clk and a ramp signal (ramp signal) VR.Analog-to-digital conversion
Circuit 120_1-120_K is coupled to pixel array 102 and control circuit 110, and each analog to digital conversion circuit can be according to clock signal clk
And ramp signal VR is by each column pixel P11-PMKGenerated analog signal (such as multiple analog signal VA1-VAKAmong it is corresponding
Analog signal) be converted to a digital signal.With a column pixel P11-PM1For, analog to digital conversion circuit 120_1 can be according to clock
Signal CLK and ramp signal VR is by analog signal VA1Be converted to a digital signal VD1。
It is worth noting that, although each D/A converting circuit shown in FIG. 1 can directly receive mould caused by each column pixel
Quasi- signal, however, this only facilitates explanation, the disclosure is not limited thereto.In certain embodiments, each column pixel is produced
Raw analog signal can first pass through relevant signal processing and then be transmitted to corresponding D/A converting circuit.For example,
Programmable gain amplifier (programmable gain amplifier, PGA) may be disposed at a column pixel and corresponding number
Between analog conversion circuit, therefore, the analog signal that the column pixel generates can first pass through programmable gain amplifier and carry out signal
Enhanced processing and then it is transmitted to corresponding D/A converting circuit.
In this embodiment, each analog to digital conversion circuit can be according to ramp signal VR and corresponding analog signal, different
Counting stage counts the number of cycles of clock signal clk, and corresponding analog signal is converted to digital signal.With mould
For number conversion circuit 120_1, analog to digital conversion circuit 120_1 first can be according to ramp signal VR and analog signal VA1Carry out clock synchronization
The number of cycles of clock signal CLK carries out the first counting operation.Clock signal clk can be implemented by the clock signal of low frequency, thus
Reduce the power consumption of signal processing.That is, first counting operation can be considered thick counting operation (coarse
counting).When the signal level of ramp signal VR will reach analog signal VA1Signal level when (for example, ramp signal
The signal level and analog signal VA of VR1The gap of both signal levels be located in a preset range), in addition to according to carrying out institute
The first counting operation is stated, analog to digital conversion circuit 120_1 can also accumulate the charge from the first electric current I1.Stopping first meter
After number operation, analog to digital conversion circuit 120_1 can discharge accumulated charge based on the second electric current I2, wherein the second electric current I2 is small
In the first electric current I1.
It is worth noting that, the charge that analog to digital conversion circuit 120_1 is accumulated can indicate that stopping described first counts behaviour
At the time point at count value last time increased time point and stopping first counting operation, accumulated between the two before work
Charge.Therefore, lesser electric current (the second electric current I2) can be used to discharge the charge accumulated from biggish electric current, and
The number of cycles of clock signal clk is counted during this period, to improve the resolution ratio of analog to digital conversion circuit 120_1.
For example (but the present disclosure is not limited thereto), the second electric current I2 can be 1/8th of the first electric current I1, therefore,
Time needed for discharging accumulated charge with the second electric current I2 is generally with the time needed for the first electric current I1 stored charge
It is octuple.Therefore, in terms of being carried out in a period of discharging accumulated charge by the second electric current I2 to the number of cycles of clock signal clk
Number, is equivalent in a period of with the first electric current I1 stored charge, to another clock signal, (frequency is the frequency of clock signal clk
Rate it is octuple) number of cycles counted.That is, second counting operation can be considered fine counting operation (fine
counting).By being counted in a period of discharging accumulated charge to the number of cycles of clock signal clk, modulus
Conversion circuit 120_1 can use the clock signal of lower frequency to realize high-precision digital-to-analogue conversion operation.In this way, image passes
The power consumption of analog-to-digital conversion operation can be greatly reduced under the needs of meeting high-resolution and high speed imaging in sensor 100.
Please come together with Fig. 1 refering to Fig. 2.Fig. 2 shows multiple analog to digital conversion circuit 120_1-120_K shown in FIG. 1 wherein
An at least analog to digital conversion circuit a specific embodiment schematic diagram.Analog to digital conversion circuit 220 can be by an analog signal VA
(such as multiple analog signal VA1-VAKOne of them) a digital signal VD is converted to, and may include that (but being not limited to) comparison is electric
Road 230, one first counter 240, a charge accumulation circuitry 250, a discharge circuit 260 and one second counter 270.Compare
Circuit 230 generates one first comparison signal CP1 analog signal VA to make comparisons with ramp signal VR, and simulation is believed
Number VA makes comparisons with digital signal VD plus a predetermined migration Vos to generate one second comparison signal CP2.That is, first
Comparison signal CP1 can indicate that the size relation of " analog signal VA " and " ramp signal VR " signal level between the two, second
Comparison signal CP2 can indicate that " analog signal VA " and " ramp signal VR adds predetermined migration Vos " signal level between the two
Size relation.Therefore, it gradually increases in the signal level of ramp signal VR with the mistake of the signal level of approaching simulation signal VA
Cheng Zhong, compared to the first comparison signal CP1, the signal level of the second comparison signal CP2 can first overturn (toggle), indicate letter
The change of number size relation.
For example (but the present disclosure is not limited thereto), comparison circuit 230 may include (but being not limited to) first comparator 232
With one second comparator 234.First comparator 232 is to receive analog signal VA and ramp signal VR, and by analog signal VA
It is made comparisons with ramp signal VR to generate the first comparison signal CP1.Second comparator 234 is then to believe analog signal VA and slope
Number VR makes comparisons plus predetermined migration Vos, generates the second comparison signal CP2 accordingly.Predetermined migration Vos can be (but are not limited to)
The intrinsic comparator offset (comparator offset) in second comparator, 234 inside.That is, with first comparator 232
Similar, the second comparator 234 also can receive analog signal VA and ramp signal VR.Since the second comparator 234 has comparator
Offset, therefore, the comparison operation that the second comparator 234 is carried out can be considered to analog signal VA and ramp signal VR plus predetermined
Offset Vos is compared.The offset of predetermined migration Vos can be adjusted according to design requirement.
It is worth noting that, in certain embodiments, first comparator 232 and the second comparator 234 are combinable at having
The single comparison circuit of two output ends.In certain embodiments, the second comparator 234 may be incorporated into first comparator 232.?
That is the relevant design variation of comparison circuit 230, is all contained in the protection scope of the disclosure.
First counter 240 is coupled to comparison circuit 230, to control clock signal according to the first comparison signal CP1
The counting operation of the number of cycles of CLK.For example, indicating that the signal level of analog signal VA is greater than in the first comparison signal CP1
When the signal level of ramp signal VR, the first counter 240 can count to obtain number the number of cycles of clock signal clk
The first part (i.e. the first count value CV_C) of word signal VD.
In certain embodiments, the first counter 240, which can be in due course, just starts the number of cycles of clock signal clk
Counting operation, to reduce power consumption.For example, control circuit 110 does not allow the first counter before ramp signal VR generation
240 starting counting operations；When ramp signal VR is generated, the counting operation of the first counter 240 just be will start.
Charge accumulation circuitry 250 is coupled to comparison circuit 230, to indicate analog signal in the first comparison signal CP1
The signal level of VA is greater than the signal level of ramp signal VR, and the second comparison signal CP2 indicates the signal of analog signal VA
When signal level of the level less than ramp signal VR adds predetermined migration Vos, at a charge accumulation end of charge accumulation circuitry 250
TCA accumulates the charge from the first electric current I1.The charge that charge accumulation end TCA is accumulated can indicate that the first counter 240 stops
At the first count value CV_C last time increased time point, stop the time point counting with the first counter 240 before only counting
The charge accumulated between the two.
In certain embodiments, charge accumulation circuitry 250 can start when the first count value CV_C increases in charge accumulation
TCA is held to accumulate the charge from the first electric current I1.For example, in signal of the signal level of analog signal VA greater than ramp signal VR
Level, and the signal level less than ramp signal VR is believed plus during predetermined migration Vos when clock signal clk is in predetermined
When number edge (rising edge or failing edge), charge accumulation circuitry 250 can start to accumulate in charge accumulation end TCA from the first electric current I1
Charge.
In certain embodiments, it is tired can to carry out one or many charges to charge accumulation end TCA for charge accumulation circuitry 250
Product operation, wherein when the first count value CV_C increases, charge accumulation circuitry 250 can reset charge accumulate end TCA, and exist again
Charge accumulation end TCA accumulates the charge from the first electric current I1.For example, in the signal level and ramp signal VR of analog signal VA
Signal level between gap be less than predetermined migration Vos in a period of, whenever the first count value CV_C increase when, charge accumulation
Circuit 250 can reset charge accumulate end TCA, and again charge accumulation end TCA accumulate the charge from the first electric current I1.
In addition, in certain embodiments, when the first comparison signal CP1 indicates that the signal level of analog signal VA is less than tiltedly
When the signal level of slope signal VR, charge accumulation circuitry 250 can stop at charge accumulation end TCA accumulation from the first electric current I1's
Charge.
Discharge circuit 260 is coupled to charge accumulation end TCA, to during the first counter 240 stops counting, with the
Two electric current I2 discharge to charge accumulation end TCA.For example, the signal of analog signal VA is indicated in the first comparison signal CP1
When level is less than the signal level of ramp signal VR, the first counter 240 can stop carrying out the number of cycles of clock signal clk
It counts.Discharge circuit 260 can be when the signal level of analog signal VA be less than the signal level of ramp signal VR, with the second electric current
I2 discharges to charge accumulation end TCA.
Second counter 270 is coupled to charge accumulation circuitry 250, to charge accumulation end TCA electric discharge during, clock synchronization
The number of cycles of clock signal CLK is counted to obtain the second part of digital signal VD (i.e. the second count value CV_F).It is worth
It is noted that the second electric current I2 is less than the first electric current I1.Therefore, to clock signal clk during charge accumulation end TCA discharges
Number of cycles carry out counting operation, be equivalent to charge accumulation end TCA accumulate from the charge of the first electric current I1 during
It is interior, the number of cycles of another clock signal (frequency that frequency is greater than clock signal clk) is counted.That is, first
Counter 240 can be considered coarse counter (coarse counter), and the second counter 270 can be considered fine counter (fine
Counter), wherein the charge in charge accumulation end TCA accumulation can correspond between the first two neighboring numerical value of count value CV_C
Numerical scale.
Although it is worth noting that, be above with column parallel A/D transformational structure come illustrate digital-to-analogue disclosed in this invention turn
Circuit is changed, however, the present invention is not limited thereto.For example, K column pixel shown in FIG. 1 can also pass through a switching circuit
Share single D/A converting circuit, wherein the single D/A converting circuit can D/A converting circuit 220 as shown in Figure 2 it is real
It applies.
Technical characteristic to facilitate the understanding of the present invention illustrates that institute of the invention is public using a demonstrative circuit structure below
The details for the analog-to-digital conversion opened.However, this only facilitates explanation.It is any to use the reality based on circuit structure shown in Fig. 2
It is feasible for applying mode.Referring to Fig. 3, its schematic diagram for an embodiment of analog to digital conversion circuit 220 shown in Fig. 2.Mould
Number conversion circuit 320 may include a first comparator 332, one second comparator 334 (having predetermined migration Vos), one first meter
Number device 340, a charge accumulation circuitry 350, a discharge circuit 360 and one second counter 370, wherein shown in Fig. 2 first
Comparator 232, the second comparator 234, the first counter 242, charge accumulation circuitry 250, discharge circuit 260 and second count
Device 270 can be respectively by first comparator 332, the second comparator 334, the first counter 340, charge accumulation circuitry 350, electric discharge electricity
Road 360 and the second counter 370 are implemented.
First counter 340 may include (but being not limited to) one and door A11 and Y trigger (Y is greater than 1 positive integer).
In this embodiment, the Y trigger can be implemented by 9 d type flip flops (D flip-flop) DF11-DF19, wherein with door
A11 can receive respectively clock signal clk and the first comparison signal CP1 in two input terminals, to generate in the output end of door A11
One first input clock signal CKD1.Multiple d type flip flop DF11-DF19 are successively cascaded (that is, d type flip flop DF11-DF18 is respective
Data output end Q is respectively coupled to the input end of clock of d type flip flop DF12-DF19)；Also, d type flip flop DF11 is couple to and door
The output end (that is, the input end of clock of d type flip flop DF11 is couple to the first input clock signal CKD1) of A11, wherein each D is triggered
The data input pin D and oppisite phase data output end Q' of device DF11-DF19 is connected to each other, and the reset of each d type flip flop DF11-DF19
End R can be couple to a control circuit (control circuit 110 such as shown in FIG. 1；It is not painted), to receive the control circuit institute
The one first reset signal rstb1 generated.Multiple d type flip flop DF11-DF19 can be used to count the first input clock signal CKD1
Number of cycles to generate the first count value CV_C (output of the data output end Q comprising each trigger DF11-DF19), as
The first part of the corresponding digital signal of analog signal VA (digital signal VD such as shown in Fig. 2).
Charge accumulation circuitry 350 may include (but a being not limited to) ON-OFF control circuit 352 and a charge accumulation unit 354.
ON-OFF control circuit 352 may include (but being not limited to) multiple first and door A31, second and door A32, third and door A33, the 4th and
Door A34 and multiple phase inverter I1 and I2.First can receive the data of d type flip flop DF11 with two input terminals of door A31 respectively
An inversion signal CP2b of q1 and the second comparison signal CP2 is exported, to generate a first switch in the output end of first and door A31
Control signal qp.For example, analog to digital conversion circuit 320 can further include a phase inverter (not being painted), compare for reverse phase second
Signal CP2 is to generate inversion signal CP2b.Second can receive the reverse phase of d type flip flop DF11 with two input terminals of door A32 respectively
Data export q1n and inversion signal CP2b, control signal qn to generate a second switch in the output end of second and door A32.The
Three can receive the first comparison signal CP1 and first switch control signal qp with two input terminals of door A33 respectively, in third with
The output end of door A33 generates a third switch control signal q1g.Two input terminals of 4th and door A34 can receive first respectively
Comparison signal CP1 and second switch control signal qn, to generate one the 4th switch control signal in the output end of the 4th and door A34
qn1g.In addition, phase inverter I1 is to reverse phase first switch control signal qp to generate one first inverted control signal qp '.Reverse phase
Device I2 is to reverse phase second switch control signal qn to generate one second inverted control signal qn '.
Charge accumulation unit 354 may include that (but being not limited to) one first stores end TO1, one second storage end TO2, one first
Capacitor C1, one second capacitor C2 and a current source CS1.First storage end TO1 is optionally coupled to charge accumulation end TCA,
And second storage end TO2 be optionally coupled to charge accumulation end TCA.First capacitor C1 be coupled to the first storage end TO1 with
Between one reference mode Nref and the second capacitor C2 is coupled between the second storage end TO2 and reference mode Nref.Current source
CS1 is couple to first capacitor C1 by the first storage end TO1, and is couple to the second capacitor C2 by the second storage end TO2.Electricity
Stream source CS1 to provide the first electric current I1, and can clock signal clk different cycles with the first electric current I1 alternately to first
Capacitor C1 and the second capacitor C2 charges, to come from the first electric current I1 in the first storage end TO1 and the second storage end TO2 accumulation in turn
Charge.When current source CS1 charges to first capacitor C1, the first storage end TO1 is coupled to charge accumulation end TCA；Work as electric current
When source CS1 charges to the second capacitor C2, the second storage end TO2 is coupled to charge accumulation end TCA.That is, in clock signal
In some period of CLK, current source CS1 can be used the first electric current I1 to first capacitor C1 and the second capacitor C2 one of those
It charges, to accumulate the charge from the first electric current I1 at storage end accordingly；In the next cycle of clock signal clk
In, current source CS1 can be used the first electric current I1 and charge to first capacitor C1 and the second therein another of capacitor C2, with
The charge from the first electric current I1 is accumulated at another corresponding storage end.
In addition, in this embodiment, when current source CS1 charges to first capacitor C1, the second storage end TO2 can be answered
Position；When current source CS1 charges to the second capacitor C2, the first storage end TO1 can be reset.In this way, current source CS1 can be in clock
The different cycles of signal CLK again charge to first capacitor C1/ the second capacitor C2.
For example (but the present disclosure is not limited thereto), charge accumulation unit 354 may also include a first switch S1, one second
Switch S2, a third switch S3 and one the 4th switch S4.First switch S1 is controlled by the first inverted control signal qp ', is used
To be optionally coupled between the first storage end TO1 and reference mode Nref.Second switch S2 is by the second inverted control signal
Qn ' is controlled, to be optionally coupled between the second storage end TO2 and reference mode Nref.Third switch S3 is by first
Switch control signal qp is controlled, to be optionally coupled between the first storage end TO1 and charge accumulation end TCA.4th
Switch S4 is controlled by second switch control signal qn, to be optionally coupled to the second storage end TO2 and charge accumulation end
Between TCA.When current source CS1 charges to first capacitor C1, first switch S1 and the 4th switch S4 can be closed and second holds
Closing S2 and third switch S3 can open；When current source CS1 charges to the second capacitor C2, first switch S1 and the 4th switch S4 meeting
It opens and second switch S2 and third switch S3 can be closed.Therefore, when current source CS1 charges to first capacitor C1, first
Storage end TO1 can be coupled to charge accumulation end TCA, and the second storage end TO2 can be reset.Similarly, when current source CS1 is to
When two capacitor C2 charge, the second storage end TO2 can be coupled to charge accumulation end TCA, and the first storage end TO1 can be reset
In this embodiment, charge accumulation unit 354 may also include one the 5th switch S5, one the 6th switch S6 and a ratio
Compared with device 356.5th switch S5 is controlled by third switch control signal q1g, to be optionally coupled to current source CS1 and
Between one storage end TO1.6th switch S6 is controlled by the 4th switch control signal qn1g, to be optionally coupled to electric current
Between the storage of source CS1 and second end TO2.Comparator 356 has first input end TI1, the second input terminal TI2 and output end TO,
Wherein first input end TI1 is coupled to charge accumulation end TCA, and the second input terminal TI2 is coupled to reference mode Nref, and output
End TO is coupled to the second counter 370.When the signal level of first input end TI1 is greater than the signal level of the second input terminal TI2
When, comparator 356 can export an enable signal EN from output end TO to enable the second counter 370.
Discharge circuit 360 may include (but being not limited to) one to be discharged based on the second electric current I2 charge accumulation end TCA
A current source CS2 and switch SD.Current source CS2 is to receive the second electric current I2.Switch SD is selectively coupled to charge accumulation end
Between TCA and current source CS2, wherein being opened during charge accumulation circuitry 350 stops accumulation from the charge of the first electric current I1
Closing SD can be coupled between charge accumulation end TCA and current source CS2, and the second electric current I2 is made to pour into electric current from charge accumulation end TCA
Source CS2.That is, during charge accumulation circuitry 350 stops accumulation from the charge of the first electric current I1, charge accumulation end
The charge of TCA accumulation is releasably to current source CS2.
Second counter 370 may include (but being not limited to) one and door A21 and P trigger (P is greater than 1 positive integer).
In this embodiment, the P trigger can be implemented by 3 d type flip flops (D flip-flop) DF21-DF23, wherein with door
A21 can receive respectively clock signal clk and enable signal EN in two input terminals, in generating one the with the output end of door A21
Two input clock signal CKD2.Multiple d type flip flop DF21-DF23 are successively cascaded (that is, the respective number of d type flip flop DF21 and DF22
The input end of clock of d type flip flop DF22 and DF23 is respectively coupled to according to output end Q)；Also, d type flip flop DF21 is couple to and door
The output end (that is, the input end of clock of d type flip flop DF21 is couple to the second input clock signal CKD2) of A21, wherein each D is triggered
The data input pin D and oppisite phase data output end Q' of device DF21-DF23 is connected to each other, and the reset of each d type flip flop DF21-DF23
End R can be couple to a control circuit (control circuit 110 such as shown in FIG. 1；It is not painted), to receive the control circuit institute
The one second reset signal rstb2 generated.Multiple d type flip flop DF21-DF23 can be used to count the second input clock signal CKD2
Number of cycles to generate the second count value CV_F (output of the data output end Q comprising each trigger DF21-DF23), as
The second part of the corresponding digital signal of analog signal VA (digital signal VD such as shown in Fig. 2).
Also referring to Fig. 3 and Fig. 4.Fig. 4 is signal processing operations involved in analog to digital conversion circuit 320 shown in Fig. 3
An embodiment signal timing diagram.For convenience of explanation, in this embodiment, the size of current of the second electric current I2 can be
/ 8th of one electric current I1.However, the present invention is not limited thereto.Before time point t1, the signal electricity of analog signal VA
The flat signal level greater than ramp signal VR, therefore, the first counter 340 can periods to the first input clock signal CKD1
Number is counted.In addition, signal level of the signal level greater than ramp signal VR of analog signal VA adds before time point t1
Upper predetermined migration Vos, therefore, the charge accumulation operation of charge accumulation circuitry 350 can not be activated.
In time point t1, the signal level of analog signal VA is still greater than the signal level of ramp signal VR, however, simulation letter
Signal level of the signal level of number VA less than ramp signal VR adds predetermined migration Vos.Therefore, the second comparison signal CP2
Signal level overturning, charge accumulation circuitry 350 can start to accumulate the charge from the first electric current I1 in charge accumulation end TCA.
In time point t2, the first count value CV_C of the first counter 340 by N increase be N+1 when, charge accumulation circuitry
350 can reset charge accumulate end TCA, and again charge accumulation end TCA accumulate the charge from the first electric current I1.For example, the
One switch S1 can be opened, and the 5th switch S5 can be closed, and the first storage end TO1 (having signal level V1) is made to be reset.Second opens
Closing S2 can close, and the 6th switch S6 can be opened, and make current source CS1 that can charge to the second capacitor C2, to store end TO2 second
Charge of (the there is signal level V2) accumulation from the first electric current I1.In addition, third switch S3 can be closed, the 4th switch S4 can be held
It opens, the second storage end TO2 is made to be couple to charge accumulation end TCA.
In time point t3, when the first count value CV_C of the first counter 340 increases again (increased by N+1 is N+2),
Charge accumulation circuitry 350 reset charge can accumulate end TCA again, and come from the first electric current in charge accumulation end TCA accumulation again
The charge of I1.For example, second switch S2 can be opened, the 6th switch S6 can be closed, and the second storage end TO2 is made to be reset.First opens
Closing S1 can close, and the 5th switch S5 can be opened, and make current source CS1 that can charge to first capacitor C1, with tired in the first storage end TO1
Charge of the product from the first electric current I1.In addition, third switch S3 can be opened, the 4th switch S4 can be closed, and make the first storage end TO1
It is couple to charge accumulation end TCA.
In time point t4, the signal level of analog signal VA is less than the signal level of ramp signal VR, so that first compares
The signal level of signal CP1 is overturn.Therefore, the first counter 340 can stop relevant counting operation, and charge accumulation circuitry
350 can stop relevant charge accumulation operation.
During the first counter 340 stops counting, discharge circuit 360 can be based on the second electric current I2 to charge accumulation end
TCA electric discharge.Second counter 370 can carry out the number of cycles of clock signal clk during charge accumulation end TCA discharges
It counts to obtain the second part of digital signal VD.For example, stopping accumulation from the first electric current I1's in charge accumulation circuitry 350
After charge (after time point t4), when clock signal clk for the first time occur prearranged signals along when, the second counter 370 can be opened
Beginning counts the number of cycles of clock signal clk.
In this embodiment, in time point t5 the rising edge of first time (clock signal clk after time t 4), electric discharge
Charge accumulation end TCA can be couple to current source CS2 according to the second reset signal rstb2 by the switch SD of circuit 360, to discharge electricity
The charge that lotus accumulation end TCA is accumulated is (that is, first capacitor C1/ first stores end TO1 institute between time point t4 and time point t5
The charge of accumulation).Second counter 370 can reset the second count value CV_F according to the second reset signal rstb2, and believe clock
The number of cycles of number CLK is counted, to update the second count value CV_F.
In time point t6, when the signal level of the first input end TI1 of comparator 356 is less than the letter of first input end TI2
When number level (i.e. the signal level Vr that reference mode Vref has), the exported enable signal EN of output end TO can be in low signal
Level, the second counter 370 can stop counting operation.First count value CV_C (N+2) and the second count value CV_F (3) respectively can
A part as digital signal VD.
By the digital-to-analogue conversion mechanism of the disclosure, it can be realized using the clock signal of lower frequency and be provided simultaneously with low-power consumption
With the imaging sensor of high frame per second.For example (but the present disclosure is not limited thereto) obtains the image sensing of a frame in every 2.5 μ s
In device, according to the D/A converting circuit of 12 bits, the clock signal frequency that the prior art needs is about 2GHz (212/2.5μs
=1.638GHz) clock signal handle, with meet least significant bit in count value (least significant bit,
LSB the frequency that bit value) changes.However, obtaining one D/A converting circuit 320 shown in Fig. 3 is applied to every 2.5 μ s
In some embodiments of the imaging sensor of frame, setting for imaging sensor can be met using the clock signal clk of lower frequency
Meter demand.For example, the frequency of clock signal clk can be set as to 1/8th (250MHz) of 2GHz.That is, clock signal
The cycle time of CLK is 4ns.In addition, the size of the second electric current I2 can be set as 1/8th of the size of the first electric current I1.Using
Second electric current I2 required time that discharge is preferably at most 32ns (i.e. 8 × 4ns).Therefore, D/A converting circuit 3205 is whole
Conversion time is 2080ns (i.e. 29×4ns+8×4ns).That is, even if digital-to-analogue turns using the clock signal of lower frequency
A frame can still be obtained in 2.5 μ s by changing circuit 320, to meet the design requirement of high frame per second.
It note that above only for the purpose of explanation, be not used as limitation of the invention.In certain design variation examples
In, the signal source that predetermined migration Vos can be outside the second comparator 334 is provided.For example, analog to digital conversion circuit 320 can wrap
Containing a signal source, the signal source can produce predetermined migration Vos, and predetermined migration Vos is transmitted to the negative of the second comparator 334
Input terminal.In another example control circuit 110 shown in FIG. 1 can produce another ramp signal different from ramp signal VR, wherein institute
The signal level of the signal level of another ramp signal equal to ramp signal VR is stated plus predetermined migration Vos, and the second comparator
334 can receive in negative input end reception another ramp signal.In another example another ramp signal can be ramp signal
The advanced copy (advanced replica) of VR wherein has between the advanced copy and ramp signal VR of ramp signal VR pre-
Phase bit offset makes signal level of the signal level of the advanced copy of ramp signal VR equal to ramp signal VR plus predetermined inclined
Move Vos.
In certain design variation examples, different circuit knots is can be used in the first counter 340 and/or the second counter 370
Structure.For example, the trigger number and/or type that the first counter 340 is included can determine according to design requirement,
And/or second the trigger number that is included of counter 370 and/or type can be determined according to design requirement.
In certain design variation examples, different circuit structures is can be used at charge accumulation end in charge accumulation circuitry 350
TCA accumulates the charge from the first electric current I1.For example, three or more capacitors can be used to tire out in charge accumulation circuitry 350
Accumulated charge.As long as the electricity from the first electric current can be accumulated in charge accumulation end before counting operation (i.e. thick counting operation) stopping
Lotus, and the counting operation stopping after with lesser second electric current release, while to the number of cycles of clock signal into
Row is counted to realize the analog to digital conversion circuit finely counted, and relevant variation follows spirit of the invention and falls into this in design
The scope of invention.
Analog-to-digital conversion mechanism disclosed in this invention can simply be summarized as flow chart shown in fig. 5.Fig. 5 is modulus of the present invention
The flow chart of one embodiment of conversion method.If obtained result is substantially roughly the same, then step be not necessarily intended to according to
Sequence shown in fig. 5 carries out.For example, certain steps can be assigned in wherein.For convenience of explanation, below arrange in pairs or groups Fig. 3 institute
The analog to digital conversion circuit 320 that shows illustrates to illustrate D conversion method shown in fig. 5.However, by analog-to-digital conversion shown in fig. 5
Method is applied to analog to digital conversion circuit 220 shown in Fig. 2 and/or each analog to digital conversion circuit shown in FIG. 1 is also feasible.Fig. 5
Shown in D conversion method can simply be summarized as follows.
Step 502: an analog signal is made comparisons with a ramp signal to generate one first comparison signal.For example, first
Comparator 332 makes comparisons analog signal VA with ramp signal VR to generate the first comparison signal CP1.
Step 504: the analog signal is made comparisons with the ramp signal plus a predetermined migration to generate one second
Comparison signal.For example, the second comparator 334 makes comparisons analog signal VA plus predetermined migration Vos to produce with ramp signal VR
Raw second comparison signal CP2.
Step 506: indicating that the signal level of the analog signal is believed greater than the slope in first comparison signal
Number signal level when, the number of cycles of clock signal is counted to obtain the first count value.For example, comparing letter first
Number CP1 indicates (time point t4 as shown in Figure 4 when the signal level of analog signal VA is greater than the signal level of ramp signal VR
Before), the first counter 340 can count the number of cycles of clock signal clk to obtain the first count value CV_C.
Step 508: indicating that the signal level of the analog signal is believed greater than the slope in first comparison signal
Number signal level, and second comparison signal indicates that the signal level of the analog signal is less than the ramp signal
When signal level adds the predetermined migration, the charge from the first electric current is accumulated at charge accumulation end.For example, comparing first
When signal CP1 indicates that the signal level of analog signal VA is greater than the signal level of ramp signal VR, and the second comparison signal CP2
When indicating signal level of the signal level of analog signal VA less than ramp signal VR plus predetermined migration Vos (as shown in Figure 4
Time point t1 and time point t4 between), charge accumulation circuitry 350 can charge accumulation end TCA accumulate come from the first electric current I1
Charge.
Step 510: during the charge accumulation end stops accumulation from the charge of first electric current, with the second electricity
Stream discharges to the charge accumulation end, wherein second electric current is less than first electric current.For example, in charge accumulation end TCA
During stopping charge of the accumulation from the first electric current I1, discharge circuit 350 can be based on the second electric current I2 to charge accumulation end TCA
It discharges (time point t5 as shown in Figure 4), wherein the second electric current I2 is less than the first electric current I1.
Step 512: the charge accumulation end discharge during, to the number of cycles of the clock signal counted with
Obtain the second count value, wherein first count value and second count value respectively as digital signal first part and
Second part.For example, being counted the number of cycles of clock signal clk to obtain during charge accumulation end TCA electric discharge
Second count value CV_F (between time point t5 and time point t6 as shown in Figure 4).First count value CV_C and the second count value
First part and second part of the CV_F respectively as digital signal VD.
In step 508, when first count value increases, the charge accumulation end can be resetted, and again described
The charge from first electric current is accumulated at charge accumulation end.For example, charge accumulation circuitry 350 can increase in the first count value CV_C
Added-time (such as time point t2/t3 shown in Fig. 4), reset charge accumulate end TCA, and come again in charge accumulation end TCA accumulation
From the charge of the first electric current I1.
In step 512, after the charge accumulation end stops charge of the accumulation from first electric current, when described
Clock signal for the first time occur prearranged signals along when, can start to count the number of cycles of the clock signal.For example,
Charge accumulation circuitry 350 stops at after charge of the TCA accumulation in charge accumulation end from the first electric current I1, works as clock signal clk
Occur for the first time prearranged signals along when (such as rising edge；Time point t5 shown in Fig. 4), the week to clock signal clk can be started
Phase number is counted.
After being illustrated due to those skilled in the art by the relevant paragraph of reading Fig. 1 to Fig. 4, it should be appreciated that Fig. 5 institute
The details of each step in the D conversion method shown, therefore further instruction just repeats no more herein.
From the foregoing, it will be observed that analog-to-digital conversion mechanism provided by the disclosure can be not necessarily to increase the quantity of ramp signal generating circuit,
And low-frequency clock signal can be used, thick counting operation and fine counting operation can be realized, so that power consumption be effectively reduced, reach
To the effect of economize on electricity.
The foregoing is merely embodiment of the disclosure, are not limited to the disclosure, for those skilled in the art
For member, the disclosure can have various modifications and variations.It is all the disclosure spirit and principle within, it is made it is any modification,
Equivalent replacement, improvement etc., should be included within the protection scope of the disclosure.
Claims (20)
1. a kind of analog to digital conversion circuit, for converting analog signals into digital signal characterized by comprising
Comparison circuit, making comparisons with ramp signal the analog signal to generate the first comparison signal, and will be described
Analog signal is made comparisons with the ramp signal plus predetermined migration to generate the second comparison signal；
First counter is coupled to the comparison circuit, to indicate the analog signal in first comparison signal
When signal level is greater than the signal level of the ramp signal, the number of cycles of clock signal is counted to obtain the number
The first part of word signal；
Charge accumulation circuitry is coupled to the comparison circuit, to indicate the analog signal in first comparison signal
Signal level be greater than the signal level of the ramp signal, and second comparison signal indicates the letter of the analog signal
It is tired in the charge of the charge accumulation circuitry when signal level that number level is less than the ramp signal adds the predetermined migration
The charge from the first electric current is accumulated at product end；
Discharge circuit is coupled to the charge accumulation end, to first counter stop count during, with second electricity
Stream discharges to the charge accumulation end, wherein second electric current is less than first electric current；And
Second counter is coupled to the charge accumulation circuitry, to the charge accumulation end discharge during, to it is described when
The number of cycles of clock signal is counted to obtain the second part of the digital signal.
2. analog to digital conversion circuit as described in claim 1, which is characterized in that indicate the mould in first comparison signal
When the signal level of quasi- signal is less than the signal level of the ramp signal, first counter stops to the clock signal
Number of cycles counted.
3. analog to digital conversion circuit as described in claim 1, which is characterized in that when first comparison signal indicates the mould
When the signal level of quasi- signal is less than the signal level of the ramp signal, it is tired that the charge accumulation circuitry stops at the charge
The charge from first electric current is accumulated at product end.
4. analog to digital conversion circuit as described in claim 1, which is characterized in that when the count value of first counter increases
When, the charge storage circuit can reset the charge accumulation end, and again in charge accumulation end accumulation from described the
The charge of one electric current.
5. analog to digital conversion circuit as described in claim 1, which is characterized in that the charge accumulation circuitry includes:
First storage end, is optionally coupled to the charge accumulation end；
Second storage end, is optionally coupled to the charge accumulation end；
First capacitor is coupled between the first storage end and reference mode；
Second capacitor is coupled between the second storage end and the reference mode,
Current source is couple to the first capacitor by first storage end, and is couple to by second storage end
Second capacitor, first current source to provide first electric current, and the different cycles of the clock signal with
First electric current is alternately to the first capacitor and second capacitor charging, in turn in the first storage end and institute
Charge of the second storage end accumulation from first electric current is stated, wherein when first current source charges to the first capacitor
When, first storage end is coupled to the charge accumulation end；When first current source is to second capacitor charging, institute
It states the second storage end and is coupled to the charge accumulation end.
6. analog to digital conversion circuit as claimed in claim 5, which is characterized in that wherein when the current source is to the first capacitor
When charging, second storage end can be reset；When the current source is to second capacitor charging, first storage end
It can be reset.
7. analog to digital conversion circuit as claimed in claim 5, which is characterized in that further include:
First switch is optionally coupled between the first storage end and the reference mode；
Second switch is optionally coupled between the second storage end and the reference mode；
Third switch is optionally coupled between the first storage end and the charge accumulation end；And
4th switch is optionally coupled between the second storage end and the charge accumulation end；
Wherein when the current source charges to the first capacitor, the first switch and the 4th switch can be closed, with
And the second switch and third switch can be opened；When the current source is to second capacitor charging, described first
Switch and it is described 4th switch can open and the second switch and the third switch can close.
8. analog to digital conversion circuit as claimed in claim 5, which is characterized in that the charge accumulation circuitry further include:
Comparator has first input end, the second input terminal and output end, wherein the first input end is coupled to the charge
End is accumulated, second input terminal is coupled to the reference mode and the output end is coupled to second counter.
9. analog to digital conversion circuit as claimed in claim 8, which is characterized in that wherein when the signal level of the first input end
Greater than second input terminal signal level when, the comparator exports enable signal from the output end to enable described the
Two counters.
10. analog to digital conversion circuit as described in claim 1, which is characterized in that wherein stop in the charge accumulation circuitry tired
After charge of the product from first electric current, when the clock signal occur for the first time prearranged signals along when, second meter
Number device starts to count the number of cycles of the clock signal.
11. analog to digital conversion circuit as described in claim 1, which is characterized in that the discharge circuit includes:
Current source, to receive second electric current；And
Switch, is selectively coupled between the charge accumulation end and the current source, wherein stopping in the charge accumulation circuitry
During only accumulating the charge from first electric current, the switch be coupled to the charge accumulation end and the current source it
Between, so that second electric current is poured into the current source from the charge accumulation end.
12. analog to digital conversion circuit as described in claim 1, which is characterized in that the comparison circuit includes:
First comparator, to receive the analog signal and the first slope signal, by the analog signal with it is described
Ramp signal is made comparisons；And
Second comparator, wherein the predetermined migration is the intrinsic comparator offset of second comparator, described second compares
Device adds institute to receive the analog signal and the first slope signal, by the analog signal and the ramp signal
Predetermined migration is stated to make comparisons.
13. a kind of imaging sensor characterized by comprising
Pixel array, multiple pixels including being arranged in multirow and multiple row；
Control circuit, to generate clock signal and ramp signal；And
At least just like analog to digital conversion circuit described in any one of claims 1 to 12, be coupled to the pixel array with it is described
Control circuit, analog signal caused by a column pixel in the pixel array is converted to digital signal.
14. a kind of D conversion method characterized by comprising
Analog signal is made comparisons with ramp signal to generate the first comparison signal；
The analog signal is made comparisons with the ramp signal plus predetermined migration to generate the second comparison signal；
Indicate that the signal level of the analog signal is greater than the signal level of the ramp signal in first comparison signal
When, the number of cycles of clock signal is counted to obtain the first count value；
Indicate that the signal level of the analog signal is greater than the signal level of the ramp signal in first comparison signal,
And second comparison signal indicates that the signal level of the analog signal is added less than the signal level of the ramp signal
When the predetermined migration, the charge from the first electric current is accumulated at charge accumulation end；
During the charge accumulation end stops accumulation from the charge of first electric current, with the second electric current to the charge
End electric discharge is accumulated, wherein second electric current is less than first electric current；And
During the charge accumulation end is discharged, the number of cycles of the clock signal is counted to obtain second and count
Value, wherein the first part and second part of first count value and second count value respectively as digital signal.
15. D conversion method as claimed in claim 14, which is characterized in that further include:
Indicate that the signal level of the analog signal is less than the signal level of the ramp signal in first comparison signal
When, stop at the charge of the charge accumulation end accumulation from first electric current.
16. D conversion method as claimed in claim 14, which is characterized in that further include:
When first comparison signal indicates that the signal level of the analog signal is less than the signal level of the ramp signal
When, stopping counts the number of cycles of the clock signal.
17. D conversion method as claimed in claim 14, which is characterized in that at charge accumulation end, accumulation comes from the first electric current
Charge the step of include:
When first count value increases, the charge accumulation end is resetted, and accumulation comes from the charge accumulation end again
The charge of first electric current.
18. D conversion method as claimed in claim 14, which is characterized in that at the charge accumulation end, accumulation is from described
The step of charge of first electric current includes:
The clock signal different cycles with first electric current alternately to first capacitor and the second capacitor charging, with wheel
Stream accumulates the charge from first electric current at the first storage end and the second storage end, wherein the first capacitor is coupled to institute
State between the first storage end and reference mode, second capacitor be coupled to it is described second storage end and the reference mode it
Between；
When the first capacitor is electrically charged, first storage end is couple to the charge accumulation end；And
When second capacitor is electrically charged, second storage end is couple to the charge accumulation end.
19. D conversion method as claimed in claim 18, which is characterized in that at the charge accumulation end, accumulation is from described
The step of charge of first electric current further include:
When the first capacitor is electrically charged, second storage end is resetted；And
When second capacitor is electrically charged, first storage end is resetted.
20. D conversion method as claimed in claim 14, which is characterized in that carried out to the number of cycles of the clock signal
Count to obtain second count value the step of include:
After the charge accumulation end stops charge of the accumulation from first electric current, when the clock signal goes out for the first time
Existing prearranged signals along when, start to count the number of cycles of the clock signal.
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| PCT/CN2018/122250 WO2020124469A1 (en) | 2018-12-20 | 2018-12-20 | Analog-to-digital conversion circuit, image sensor, and analog-to-digital conversion method |
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| CN111770293A (en) * | 2020-06-29 | 2020-10-13 | 深圳市南北微电子技术有限公司 | Analog-to-digital conversion method, analog-to-digital converter and image sensor |
| CN111770293B (en) * | 2020-06-29 | 2022-07-26 | 深圳市南北微电子技术有限公司 | Analog-to-digital conversion method, analog-to-digital converter and image sensor |
| US11870455B2 (en) | 2020-06-29 | 2024-01-09 | Shenzhen Rgbic Microelectronics Technology Co., Ltd | Analog-to-digital conversion method, analog-to-digital converter and image sensor |
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| WO2020124469A1 (en) | 2020-06-25 |
| CN109792498B (en) | 2021-02-23 |
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