CN109786333A - 半导体结构的形成方法 - Google Patents

半导体结构的形成方法 Download PDF

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CN109786333A
CN109786333A CN201811011635.6A CN201811011635A CN109786333A CN 109786333 A CN109786333 A CN 109786333A CN 201811011635 A CN201811011635 A CN 201811011635A CN 109786333 A CN109786333 A CN 109786333A
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沙哈吉·B·摩尔
李承翰
张世杰
杨怀德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明为半导体结构的形成方法。本公开实施例说明形成硅锗源极/漏极外延堆叠的方法，其硼掺杂轮廓与锗浓度可诱发外部应力至完全应变的硅锗通道。此方法包含形成一或多个栅极结构于鳍状物上，其中鳍状物包括鳍状物高度、第一侧壁、以及与第一侧壁对向的第二侧壁。方法亦包括形成第一间隔物于鳍状物的第一侧壁上，并形成第二间隔物于鳍状物的第二侧壁上；蚀刻鳍状物以降低栅极结构之间的鳍状物高度；以及蚀刻栅极结构之间的第一间隔物与第二间隔物，使蚀刻后的第一间隔物比蚀刻后的第二间隔物短，且蚀刻后的第一间隔物与蚀刻后的第二间隔物比蚀刻后的鳍状物短。方法还包括形成外延堆叠于栅极结构之间的蚀刻后的鳍状物上。

Description

半导体结构的形成方法
技术领域
本发明实施例关于硅锗源极/漏极外延堆叠的例示性制作方法。
背景技术
在半导体装置如互补式金属氧化物半导体装置中，完全应变通道可改良载子移动率并降低通道电阻。此外，改良载子移动率可增加应变诱发驱动电流，其可用于通道长度缩小的互补式金属氧化物半导体装置。
发明内容
本发明一实施例提供的半导体结构的形成方法，包括：形成一或多个栅极结构于鳍状物上，其中鳍状物包括鳍状物高度、第一侧壁、以及与第一侧壁对向的第二侧壁；形成第一间隔物于鳍状物的第一侧壁上，并形成第二间隔物于鳍状物的第二侧壁上；蚀刻鳍状物以降低栅极结构之间的鳍状物高度；蚀刻栅极结构之间的第一间隔物与第二间隔物，使蚀刻后的第一间隔物比蚀刻后的第二间隔物短，且蚀刻后的第一间隔物与蚀刻后的第二间隔物比蚀刻后的鳍状物短；以及形成外延堆叠于栅极结构之间的蚀刻后的鳍状物上。
附图说明
图1是一些实施例中，用于形成具有一或多个外延层的硅锗源极/漏极外延堆叠的例示性制作方法的流程图。
图2是一些实施例中，基板上的完全应变鳍状物的剖视图。
图3是一些实施例中，多个鳍状物上的多个栅极结构的上视图。
图4是一些实施例中，在形成硅盖层与其上的栅极氧化物之后，基板上的完全应变鳍状物的剖视图。
图5是一些实施例中，在形成多晶硅层之后，基板上的完全应变鳍状物的剖视图。
图6是一些实施例中，在沉积间隔物堆叠之后，鳍状物上的图案化栅极结构的剖视图。
图7是一些实施例中，在形成鳍状物凹陷区于图案化栅极结构之间之后，鳍状物上的图案化栅极结构的剖视图。
图8是一些实施例中，在形成多个鳍状物凹陷区于相邻的栅极结构之间之后，栅极结构与鳍状物的上视图。
图9是一些实施例中，具有第一型装置的芯片的区域中的例示性鳍状物凹陷区的剖视图。
图10是一些实施例中，具有第二型装置的芯片的区域中的例示性鳍状物凹陷区的剖视图。
图11是一些实施例中，成长于具有第一型装置的芯片的区域中的例示性硅锗源极/漏极外延堆叠的剖视图。
图12是一些实施例中，成长于具有第二型装置的芯片的区域中的例示性硅锗源极/漏极外延堆叠的剖视图。
图13是一些实施例中，在形成图案化栅极结构之间合并的源极/漏极区之后，鳍状物上的图案化栅极结构的剖视图。
符号说明
A 凹陷量
B、B’ 部分
C、C’ 侧壁高度
D、H 高度
100 制作方法
110、120、130、140、150、160 步骤
200 鳍状物
210 硅锗应变材料
220 硅层
230 n型硅区
240 介电层
250 衬垫层
300 栅极结构
400 硅盖层
410 栅极氧化物
500 多晶硅层
510 氮化硅层
520 氧化物层
600 间隔物
600A 第一间隔物
600B 第二间隔物
610 第三间隔物
700 鳍状物凹陷区
710、920 虚线
720 线段
1100、1200 硅锗源极/漏极外延(epitaxial，磊晶)堆叠
1110 第一外延子层
1120 第二外延子层
1130 第三外延子层
具体实施方式
下述内容提供的不同实施例或实例可实施本发明的不同结构。特定构件与排列的例子是用以简化本发明而非局限本发明。举例来说，形成第一结构于第二结构上的叙述包含两者直接接触，或两者之间隔有其他额外结构而非直接接触。此外，本发明的多种例子中可重复标号，但这些重复仅用以简化与清楚说明，不代表不同实施例和/或设置之间具有相同标号的单元之间具有相同的对应关系。
此外，空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。
鳍状场效晶体管的种类之一为金属氧化物半导体场效晶体管。金属氧化物半导体场效晶体管可为形成于基板(如半导体晶圆)的平坦表面之中或之上的平面结构。金属氧化物半导体场效晶体管亦可为具有半导体材料的三维及垂直取向的结构，其可称作鳍状物。用语“鳍状场效晶体管”指的是形成于半导体(如硅)鳍状物上的场效晶体管，其垂直方向相对于晶圆的平坦表面。
此处所述的外延层指的是结晶材料的层状物或结构。类似地，此处所述的外延成长，指的是成长结晶材料的层状物或结构的工艺。外延成长材料可掺杂或未掺杂。
此处所述的用语“实质上”指的是给定值可依半导体装置相关的特定技术节点变化。举例来说，用语“实质上”所指的数值可为给定值的±5％，端视特定的技术节点而定。
此处所述的用语“约”指的是给定值可依半导体装置相关的特定技术节点变化。举例来说，用语“约”所指的数值可为给定值的±5％至±30％之间(比如给定值的±5％、±10％、±20％、或±30％)，端视特定的技术节点而定。
此处所述的用语“垂直”指的是名义上垂直于基板表面。
完全应变通道可改善晶体管的载子移动率，并降低其通道电阻。此外，改良载子移动率可增进应变诱发的驱动电流，以用于通道长度缩小的晶体管。用于p型场效晶体管与n型场效晶体管的应变通道材料可不同。举例来说(但不限于此)，采用完全应变的掺杂碳的硅通道可增进n型场效晶体管中的电子移动率，而采用完全应变的硅锗通道可增进p型场效晶体管中的空穴移动率。完全应变外延通道可衍生自形成于鳍状物顶部上的外延层。完全应变通道的形成工艺具有挑战性，其需要多个制作步骤如图案化、预清洁、退火、外延成长工艺、与类似步骤。
完全应变通道的固有应力可能无法免于松驰。举例来说，在中段工艺或后段工艺的制作步骤中，完全应变外延通道可能松驰。此外，在一长列晶体管末端的晶体管可能因缺乏相邻的晶体管而产生应力松驰。若完全应变外延通道的应力松驰，将降低载子移动率。
此处所述的实施例关于硅锗源极/漏极外延堆叠的例示性制作方法，其可诱发外部应力至所需装置上的个别硅锗完全应变通道。硅锗源极/漏极外延堆叠可包含三个或更多具有不同硼掺质与锗浓度的子层。硅锗源极/漏极外延层依据其硼掺质轮廓与锗浓度，可诱发外部应力至完全应变的硅锗通道。在一些实施例中，外部应力可补偿完全应变硅锗通道中可能的应力损失。此处所述的实施例中，硅锗源极/漏极外延层可具有渐变的应力。举例来说，诱发至完全应变硅锗通道区的应力，在通道的上侧部分高于在通道的下侧部分。
图1是例示性的制作方法100的流程图。制作方法100说明具有一或多个外延层的硅锗源极/漏极外延堆叠的形成方法。这些硅锗源极/漏极外延堆叠可沿着完全应变通道区的高度，诱发应力梯度至完全应变通道区。在一些实施例中，例示性的制作方法100可提供一或多个具有不同硼掺质轮廓、锗浓度、与形状的外延层硅锗源极/漏极外延堆叠。在例示性的制作方法100的一或多个步骤之间可进行其他步骤，但省略其他步骤的内容以清楚说明。例示性的制作方法100并不限于下述步骤，而可包含额外步骤。用以说明例示性的制作方法100的附图仅用于举例而未依比例示出。此外，附图并未反映结构或膜状物的实际几何形状。为说明目的，可刻意增大一些结构、膜状物、或尺寸。
例示性的制作方法100一开始进行步骤110，以提供完全应变材料组成的鳍状物于基板上。以图2为例，鳍状物200的组成可为硅锗应变材料210。鳍状物200亦可包含外延成长的硅层220组成的中间部分于n型硅区230上。在一些实施例中，介电层240形成于鳍状物200之间，因此硅锗应变材料210凸起高于介电层240。在一些实施例中，衬垫层250覆盖鳍状物200的底部。在一些实施例中，衬垫层250可提供结构支撑至鳍状物200。举例说明(但不限于此)，衬垫层250的组成可为氮化硅、硅、或另一合适材料。在一些实施例中，每一鳍状物200的高度H(自硅层220的顶部至硅锗应变材料210的尖端)可介于约30nm至约90nm之间，比如60nm。换言之，硅锗应变材料210的高度为鳍状物200的高度H。在一些实施例中，硅锗应变材料210的整个高度(沿着z方向)的锗浓度可为定值，其可介于约20原子百分比至约40原子百分比之间。在一些实施例中，硅锗应变材料210可包含顶子层与底子层，顶子层的锗浓度梯度自0至约5原子百分比，而底子层的固定锗浓度介于约20原子百分比至约40原子百分比之间。顶子层的厚度可为约25nm，而底子层的厚度可介于约5nm至约65nm之间。上述锗浓度仅用以举例说明而非局限本发明实施例。因此可能具有不同的锗浓度。
在图2中，沿着y方向(即沿着鳍状物200的宽度)显示鳍状物200。图2中的鳍状物200其长度沿着x方向，即延伸至纸面中。在一些实施例中，n型区230可形成于基板(未图示于图2中)的顶部中。在一些实施例中，基板的组成可为硅或(i)另一半导体元素(比如锗)；(ii)半导体化合物如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟；(iii)半导体合金如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、和/或磷砷化镓铟；或(iv)上述的组合。
举例来说，n型区230可描述为n型掺杂的硅区。在一些实施例中，用于n型区230的n型掺质可包含砷、锑、或磷。在一些实施例中，n型区230中的n型掺质浓度可介于约5×1016原子/cm3至约1×1019原子/cm3之间。基于此处所述的内容，可采用其他材料(如上述)，且其他材料符合本发明实施例的构思与范围。
在一些实施例中，介电层240可为浅沟槽隔离，其组成可为氧化硅、氮化硅、氮氧化硅、掺杂氟的硅酸盐玻璃、低介电常数(比如低于3.9)的介电材料、和/或具有适当填充性质的其他合适绝缘材料。此外，介电层240可包含多层结构，比如具有一或多个上述介电层。在一些实施例中，介电层240的沉积方法可为化学气相沉积工艺、等离子体增强化学气相沉积工艺、或可流动的化学气相沉积工艺。
在一些实施例中，可能有更多或更少的鳍状物200。因此图2所示的鳍状物200的数目并非用以局限本发明实施例。此外，鳍状物200之间可以不同间隔配置，比如具有不同鳍状物间距的鳍状物200。在一些实施例中，具有第一型装置(如逻辑装置)的芯片的区域的鳍状物间距，不同于具有第二型装置(如存储器，比如静态随机存取存储器)的芯片的区域的鳍状物间距。
例示性的制作方法100接着进行步骤120，以形成一或多个栅极结构于鳍状物200上。如图3所示，栅极结构300的最长尺寸沿着y方向，而鳍状物200的长度沿着x方向，且y方向垂直于x方向。在一些实施例中，栅极结构300的组成可为多晶硅。
举例来说(但不限于此)，搭配图4说明栅极结构300的形成方法。硅盖层400可成长于硅锗应变材料210上。在一些实施例中，硅盖层400可为外延层，其未成长于介电层240上。此外，硅盖层400的厚度可介于约至约之间，比如举例来说(但不限于此)，硅盖层400的沉积方法可为化学气相沉积工艺。用于形成盖层的可能硅前驱物气体，可包含硅烷、四氯化硅、三氯硅烷、或二氯硅烷。氢气可作为反应气体，以减少前述的硅前驱物气体。
硅盖层400可形成于硅锗应变材料210上，因此氧化物层可成长其上。举例来说，栅极氧化物410可热成长于硅盖层410与介电层240上。在一些实施例中，栅极氧化物410可为氧化硅层。如图5所示的一些实施例，在形成栅极氧化物410之后，可沉积多晶硅层500于栅极氧化物410上。多晶硅层500可为栅极氧化物410上的毯覆层，其覆盖鳍状物200。在一些实施例中，接着可图案化多晶硅层500以形成栅极结构于鳍状物200上。图6是一些实施例中，沿着x方向的例示性图案化多晶硅的栅极结构300的剖视图。在图6中，沿着鳍状物200的长轴(x方向的长度)显示鳍状物200。多晶硅层500的图案化方法可采用光刻与蚀刻步骤。在图案化步骤之前，可沉积氮化硅层510与氧化物层520于多晶硅层500上。在后续蚀刻多晶硅的图案化工艺中，氮化硅层510与氧化物层520可作为硬掩模层。
举例来说，图6显示两个栅极结构300位于鳍状物200的一者上。然而额外的栅极结构300，可沿着栅极结构300的侧部形成于一或多个鳍状物200上(与图3类似)。举例来说，栅极结构300可为牺牲栅极结构，其可在置换金属栅极工艺中取代为个别的金属栅极结构。在一些实施例中，金属栅极结构可包含金属栅极堆叠与高介电常数(比如大于3.9)的栅极介电层。
例示性的制作方法100接着进行步骤130，以形成间隔物堆叠于鳍状物的侧壁表面上。在一些实施例中，步骤130可为多重步骤的工艺。以图6为例，顺应性地沉积第一间隔物600A于栅极结构300与鳍状物200上。如此一来，第一间隔物600A可覆盖栅极结构300与鳍状物200，比如覆盖其上表面与侧壁表面。在一些实施例中，第一间隔物600A可为碳氮氧化硅层，其厚度可介于约1nm至约10nm之间(如约3nm)。在一些实施例中，第一间隔物600A可做为布植掩模，比如以离子布植工艺形成源极/漏极区中的轻掺杂区时的布植掩模。源极/漏极区的轻掺杂区(图6未图示)称作“源极/漏极延伸”或“轻掺杂漏极区”。然而用语“轻掺杂漏极区”仅为命名习惯，而不局限于漏极区。举例来说，轻掺杂漏极区亦可包含轻掺杂源极区。第一间隔物600A的厚度所定义的轻掺杂漏极区紧邻完全应变通道区的边缘，以提供源极/漏极区的渐变掺质浓度。轻掺杂漏极区可形成横向与垂直的掺杂轮廓于完全应变通道边缘的界面区中。若未形成轻掺杂漏极区，在操作晶体管时可能产生高电场于源极/漏极区与完全应变通道区之间。
在一些实施例中，在形成轻掺杂漏极区之后，可沉积第二侧壁间隔物600B于第一侧壁间隔物600A上。举例来说(但不限于此)，第二间隔物600B可为碳氮氧化硅层，其厚度可介于约1nm至约10nm之间(如约3nm)。与第一间隔物600A类似，第二间隔物600B亦可延伸于栅极结构300与鳍状物200上，比如延伸于其上表面与侧壁表面上。由于第一间隔物600A与第二间隔物600B的材料与厚度可类似，两者可统称为间隔物600。在一些实施例中，第三间隔物610沉积于间隔物600上。在图6的剖视图中，未图示鳍状物200的侧壁上的间隔物600与第三间隔物610。举例来说(但不限于此)，第三间隔物610可为氮化硅，且其厚度介于约1nm至约10nm之间(如约4nm)。与间隔物600类似，第三间隔物610亦延伸于栅极结构300与鳍状物200上，比如延伸于其上表面与侧壁表面上。在一些实施例中，间隔物600与第三间隔物610形成间隔物堆叠。
在一些实施例中，可采用非等向蚀刻工艺蚀刻间隔物600与第三间隔物610，因此自栅极结构300与鳍状物200的水平表面移除间隔物600与第三间隔物610。举例来说，可自栅极结构300与鳍状物200移除间隔物600与第三间隔物610，如图7所示。然而上述步骤并未自栅极结构300与鳍状物200的侧壁移除间隔物600与第三间隔物610。
如图1所示，制作方法100的步骤140选择性地蚀刻栅极结构300之间的鳍状物200，以降低鳍状物的初始高度H，并形成具有凹陷量A的鳍状物凹陷区700，如图7所示。此外，额外的鳍状物凹陷区(如鳍状物凹陷区700)可形成于鳍状物200的其他位置(在个别的栅极结构之间)。在一些实施例中，额外鳍状物的特征在于形成凹陷区于栅极结构之间。在一些实施例中，硅锗源极/漏极外延层可成长于鳍状物凹陷区(如鳍状物凹陷区700)中。举例来说(但不限于此)，图7中的鳍状物凹陷区700的形成方法可为干蚀刻工艺。在一些实施例中，鳍状物凹陷区700自对准两个相邻的栅极结构300之间的空间。在一些实施例中，干蚀刻工艺可为非等向蚀刻。换言之，蚀刻工艺在垂直的z方向对硅锗应变材料210的移除速率，比在水平的x方向对硅锗应变材料210的移除速率快。如此一来，鳍状物凹陷区700的高度大于其宽度(x方向)。在本发明实施例中，鳍状物凹陷区700的高度可称作凹陷量A。在一些实施例中，可在干蚀刻工艺中采用图案化光刻胶层或硬掩模，保护鳍状物200不需凹陷的区域。
如上所述，可能形成多个鳍状物凹陷区700。在一些实施例中，图8是形成多个鳍状物凹陷区700于相邻的栅极结构300之间之后，栅极结构300与鳍状物200的上视图。在一些实施例中，鳍状物可具有多个鳍状物凹陷区700(或多个凹陷位置)，如图8所示。
在制作方法100的步骤150中，可自鳍状物200的侧壁使间隔物堆叠(如间隔物600与第三间隔物610)部分地凹陷或“修整”(如蚀刻)。在一些实施例中，步骤150可与制作方法100的步骤140同时进行。以图9为例，在形成鳍状物凹陷区700时，可使间隔物600与第三间隔物610部分地凹陷，以露出鳍状物侧壁的部分。图9是沿着图7的y方向中的虚线710的剖视图。虚线920对应鳍状物200的未凹陷区，比如沿着图7的线段720。如此一来，凹陷量A为鳍状物200的凹陷区与非凹陷区之间的高度差。此外，凹陷量A可等于制作方法100的步骤140中，栅极结构300之间的鳍状物凹陷量。
如图9所示的一些实施例，使间隔物600与第三间隔物610凹陷以露出鳍状物凹陷区70中的鳍状物200的部分B与B’。举例来说(但不限于此)，步骤150中的光刻与蚀刻步骤，可控制鳍状物凹陷区700中的鳍状物200的每一侧壁上的间隔物600与第三间隔物610的凹陷量。此外如图9所示，可蚀刻间隔物堆叠，因此内侧的侧壁高度C大于外侧的侧壁高度C’(C>C’)，且鳍状物凹陷区700中的鳍状物200的露出的内侧的部分B’，小于鳍状物200的露出的外侧的部分B(B’<B)。在一些实施例中，鳍状物凹陷区700中的鳍状物200的凹陷量A小于此位置的鳍状物高度，即A<B+C，且B+C＝B’+C’。如此一来，鳍状物200不可凹陷超过初始高度H的50％，即A/H≤0.5。举例来说(但不限于此)，图9可表示具有第一型装置(如逻辑装置)的芯片的区域中，鳍状物200的鳍状物凹陷区700。
在一些实施例中，芯片的一些区域中的间隔物堆叠其内侧的侧壁高度C’可等于外侧的侧壁高度C(即C’＝C)。举例来说，芯片的这些区域具有第二型装置(如存储器，比如静态随机存取存储器)。
在一些实施例中，鳍状物200的鳍状物凹陷区700的侧壁表面上的间隔物堆叠的侧壁高度C与C’，可调整后续步骤形成于鳍状物200的鳍状物凹陷区700中的硅锗源极/漏极外延堆叠的最终尺寸/体积。举例来说，当一对侧壁高度C与C’小于鳍状物凹陷区700中的鳍状物高度时，可增加硅锗源极/漏极外延层的尺寸。另一方面，当一对侧壁高度C与C’大于鳍状物凹陷区700中的鳍状物高度时，可减小硅锗源极/漏极外延层的尺寸。如上所述，光刻步骤可分别控制间隔物堆叠的侧壁高度C与C’。如此一来，可得间隔物600与第三间隔物610的不同侧壁高度C与C’，以用于第一型装置与第二型装置。
在一些实施例中，在选择区的鳍状物凹陷区700中，鳍状物200的凹陷量更大以进一步降低鳍状物高度。举例来说，这些区域可为芯片的第二型区域。举例来说(但不局限于此)，在形成第二型区域中的额外鳍状物凹陷时，可采用光刻胶掩模或硬掩模覆盖芯片的第一型区域，以避免第一型区域中的鳍状物进一步凹陷。
举例来说(但不限于此)，图10是在鳍状物凹陷区700中的鳍状物200上进行额外的鳍状物蚀刻步骤之后，具有第二型装置(如存储器，比如静态随机存取存储器)的芯片的区域。如上所述，在具有第二型装置的区域中，鳍状物凹陷区700中的鳍状物200的内侧侧壁表面与外侧侧壁表面之间，间隔物堆叠(间隔物600与第三间隔物610)的侧壁高度可实质上相等。此外，第二型装置的鳍状物凹陷区700中的鳍状物200如图10所示，其高度D小于间隔物600与第三间隔物610的侧壁高度C与C’，即D<C，且C＝C’。此外，在图10的鳍状物凹陷区700中，鳍状物200的凹陷量A大于凹陷的鳍状物的高度D。在一些实施例中，具有第二型装置的芯片的区域中，鳍状物200自初始的高度H的凹陷量可大于50％，即A/H>0.5。在一些实施例中，鳍状物200不会凹陷至低于介电层240的上表面。如此一来，一些实施例中的凹陷量A与初始的鳍状物高度H之间的比例大于0.5且小于1，即0.5<A/H<1。
在一些实施例中，制作方法100继续进行步骤160，可成长硅锗源极/漏极外延堆叠于鳍状物200的凹陷区上(比如成长于图7的鳍状物凹陷区700上)。值得注意的是，在间隔物600与第三间隔物610的间隔物堆叠覆盖的鳍状物凹陷区700中的鳍状物200的表面上，不会成长硅锗外延层。
如上所述，间隔物堆叠的侧壁高度C与C’可控制成长于鳍状物200的鳍状物凹陷区700上的硅锗源极/漏极外延堆叠的尺寸(如体积)。举例来说，图11显示在形成硅锗源极/漏极外延堆叠1100之后，具有第一型装置(如逻辑装置)的芯片的区域中，鳍状物200的例示性鳍状物凹陷区700。在一些实施例中，间隔物堆叠的侧壁高度C与C’与鳍状物凹陷区700中鳍状物200的凹陷量A的组合，可让自鳍状物200的相邻的鳍状物凹陷区700之间成长的个别硅锗源极/漏极外延堆叠合并，以形成合并的源极/漏极外延堆叠1100。
在一些实施例中，合并的硅锗源极/漏极外延堆叠1100可包含三个或更多硅锗外延子层。举例来说(但不局限于此)，合并的硅锗源极/漏极外延堆叠1100可包含第一外延子层1110、第二外延子层1120、与第三外延子层1130。在一些实施例中，第一外延子层1110、第二外延子层1120、与第三外延子层1130可连续成长并具有不同的锗原子百分比与硼掺杂浓度。在一些实施例中，在成长工艺时可调整锗与硼掺质浓度。
在一些实施例中，硅锗外延成长工艺的温度可介于约450℃至约740℃之间。在外延成长时，工艺压力可介于约1Torr(托)至约100torr之间，且反应物气体可包含(i)硅烷、二硅烷、锗烷、或二硼烷；以及(ii)氯化氢与氢气、氮气、或氩气。上述参数范围与气体种类仅用以举例说明而非局限本发明实施例。在一些实施例中，硅锗源极/漏极外延堆叠1100的形状与尺寸(如体积)可取决于(i)每一个别外延子层的成长条件如气流、晶圆温度、与工艺压力；(ii)鳍状物凹陷区700的鳍状物的每一侧壁表面上的间隔物600与第三间隔物610的侧壁高度C与C’；和/或(iii)鳍状物凹陷区700中的鳍状物200的凹陷量A等因素的组合。
在一些实施例中，第一外延子层1110的厚度可介于约10nm至约40nm之间。在一些实施例中，第一外延子层1110可比第二外延子层1120厚，而第二外延子层1120可比第三外延子层1130厚。在一些实施例中，第一外延子层1110的厚度可介于约20nm至约80nm之间，第二外延子层1120的厚度可介于约10nm至约60nm之间，而第三外延子层1130的厚度可介于约2nm至约15nm之间。此外，第二外延子层1120可夹设于两个相邻的鳍状物200之间，而第三外延子层1130可成长于第一外延子层1110与第二外延子层1120上，如图11所示。
在一些实施例中，硼浓度可自第一外延子层1110增加至第二外延子层1120，并自第二外延子层1120增加至第三外延子层1130。举例来说，第一外延子层1110的硼浓度可介于约1×1019原子/cm3至约1×1020原子/cm3之间，第二外延子层1120的硼浓度可介于约5×1019原子/cm3至约2×1021原子/cm3之间，且第三外延子层1130的硼浓度可介于约1×1020原子/cm3至约2×1021原子/cm3之间。
在一些实施例中，锗浓度可自第一外延子层1110增加至第二外延子层1120，并自第二外延子层1120增加至第三外延子层1130。举例来说，第一外延子层1110的锗浓度可介于约15原子百分比至约35原子百分比之间；第一外延子层1120的锗浓度可介于约30原子百分比至约65原子百分比之间；而第三外延子层1130的锗浓度可介于约40原子百分比至约65原子百分比之间。在一些实施例中，硅锗源极/漏极外延堆叠1100诱发至硅锗应变材料210的外部应力，正比于第一外延子层1110、第二外延子层1120、与第三外延子层1130的锗与硼浓度。举例来说，锗与硼的浓度越高，则通道区(如硅锗应变材料210)中诱发的应力越高。在一些实施例中，自合并的硅锗源极/漏极外延堆叠1100诱发的应力(诱发于完全应变通道中)，在通道的顶部较高且朝通道的底部较低。如图13所示的一些实施例，通道区1300可位于栅极结构300下的鳍状物中，并延伸于两个相邻的合并的硅锗源极/漏极外延堆叠1100之间(比如在图13所示的x方向中)。
上述合并的硅锗源极/漏极外延堆叠1100的每一子层的锗与硼浓度，仅用于举例说明而非局限本发明实施例。此外，一些实施例中每一硅锗子层(如第一外延子层1110、第二外延子层1120、与第三外延子层1130)的硼与锗浓度，可依据硅锗应变材料210的锗浓度轮廓以及完全应变通道区中所需的外部诱发应力等级而定。
图12中的硅锗源极/漏极外延堆叠1200，可与具有第二型装置(例如存储器，比如静态随机存取存储器)的芯片的区域中的鳍状物200的个别鳍状物凹陷区700上的硅锗源极/漏极外延堆叠1100同时成长。在具有第二型装置的区域中，由于鳍状物凹陷区700中的鳍状物200的凹陷量A以及间隔物堆叠的侧壁高度C与C’之间的关联，可控制每一硅锗源极/漏极外延堆叠1200的体积。如此一来，成长于鳍状物200的相邻的个别鳍状物凹陷区700之间的硅锗源极/漏极外延堆叠1200可分离(而非合并)。
在一些实施例中，具有第一型与第二型装置的芯片的个别区域中，硅锗源极/漏极外延堆叠1200可包含至少三个具有不同锗与硼掺质浓度的硅锗子层。此外，具有第一型装置的芯片中，合并的硅锗源极/漏极区外延堆叠可形成于鳍状物200的两个或更多相邻的鳍状物凹陷区700之间。在一些实施例中，硅锗源极/漏极外延堆叠1200可包含超过三个子层。
在一些实施例中，在形成硅锗源极/漏极外延堆叠1100与1200之后，自鳍状物移除间隔物堆叠(如间隔物600与第三间隔物610)。
本发明实施例关于具有第一型装置(如逻辑装置)与第二型装置(如存储器，比如静态随机存取存储器)的芯片的区域中，硅锗源极/漏极外延堆叠的例示性制作方法。硅锗源极/漏极外延堆叠可具有硼掺杂轮廓与锗浓度，其可诱发额外的外部应力至完全应变硅锗通道。在一些实施例中，额外应力可补偿完全应变硅锗通道中可能损失的应力。实施例所述的硅锗源极/漏极外延层沿着高度可具有应力梯度。举例来说，诱发至通道区的应力在通道区的顶部较高且朝通道区的底部较低。在一些实施例中，硅锗源极/漏极外延堆叠层的应力轮廓，可由每一硅锗源极/漏极外延层中的硼掺杂与锗浓调整。在一些实施例中，硅锗源极/漏极外延堆叠的形状与尺寸(如体积)可取决于(i)每一个别外延子层的成长条件如气流、晶圆温度、与工艺压力；(ii)鳍状物的鳍状物凹陷区的每一侧壁表面上的间隔物堆叠的侧壁高度；和/或(iii)栅极结构之间的硅锗应变材料的开口中的鳍状物凹陷量等因素的组合。
在一些实施例中，方法包括：形成一或多个栅极结构于鳍状物上，其中鳍状物包括鳍状物高度、第一侧壁、以及与第一侧壁对向的第二侧壁。方法亦包括形成第一间隔物于鳍状物的第一侧壁上，并形成第二间隔物于鳍状物的第二侧壁上；以及蚀刻鳍状物以降低栅极结构之间的鳍状物高度；蚀刻栅极结构之间的第一间隔物与第二间隔物，使蚀刻后的第一间隔物比蚀刻后的第二间隔物短，且蚀刻后的第一间隔物与蚀刻后的第二间隔物比蚀刻后的鳍状物短。方法亦包括形成外延堆叠于栅极结构之间的蚀刻后的鳍状物上。
在一些实施例中，蚀刻鳍状物的步骤使鳍状物高度降低不到50％。
在一些实施例中，外延堆叠包括锗浓度介于15％至35％之间的第一外延子层、锗浓度介于30％至65％之间的第二外延子层、与锗浓度介于40％至65％之间的第三外延子层。
在一些实施例中，第一外延子层的硼掺质浓度介于1×1019原子/cm3至1×1020原子/cm3之间，第二外延子层的硼掺质浓度介于5×1019原子/cm3至2×1021原子/cm3之间，而第三外延子层的硼掺质浓度介于1×1020原子/cm3至2×1021原子/cm3之间。
在一些实施例中，鳍状物包括硅锗应变材料。
在一些实施例中，外延堆叠诱发外部应力至硅锗应变材料。
在一些实施例中，外延堆叠的体积取决于蚀刻后的第一间隔物与蚀刻后的第二间隔物的高度。
在一些实施例中，方法包括形成栅极结构于鳍状物上，其中鳍状物具有第一鳍状物高度；形成间隔物堆叠于鳍状物的侧壁上，其中间隔物堆叠具有间隔物高度；使栅极结构之间的鳍状物选择性地凹陷，以降低第一鳍状物高度至第二鳍状物高度，其中第二鳍状物高度小于间隔物高度；以及在栅极结构之间形成外延堆叠于鳍状物上。
在一些实施例中，第二鳍状物高度与第一鳍状物高度之间的比例介于0.5至1之间。
在一些实施例中，外延堆叠形成硅锗源极/漏极外延堆叠以诱发应力至鳍状物。
在一些实施例中，外延堆叠包括锗浓度介于15％至35％之间的第一外延子层、锗浓度介于30％至65％之间的第二外延子层、与锗浓度介于40％至65％之间的第三外延子层。
在一些实施例中，第一外延子层的硼掺质浓度介于1×1019原子/cm3至1×1020原子/cm3之间，第二外延子层的硼掺质浓度介于5×1019原子/cm3至2×1021原子/cm3之间，而第三外延子层的硼掺质浓度介于1×1020原子/cm3至2×1021原子/cm3之间。
在一些实施例中，外延堆叠的体积取决于第一鳍状物高度至第二鳍状物高度的降低量。
在一些实施例中，结构包括：第一鳍状物与第二鳍状物互相平行；第一间隔物，位于第一鳍状物的第一侧壁与第二鳍状物的第一侧壁上，其中第一鳍状物的第一侧壁面对第二鳍状物的第一侧壁；以及第二间隔物，位于第一鳍状物的第二侧壁与第二鳍状物的第二侧壁上，第二间隔物的高度不同于第一间隔物，且第一间隔物与第二间隔物比第一鳍状物与第二鳍状物短。结构还包括外延堆叠，其具有锗与硼浓度且形成于第一鳍状物与第二鳍状物上，其中外延堆叠诱发梯度应力至相邻的通道区。外延堆叠包括：第一厚度的第一共用外延子层，且第一鳍状物与第二鳍状物共用第一共用外延子层；第二厚度的第二外延子层，形成于第一鳍状物与第二鳍状物之间，并位于第一共用外延子层上；以及第三厚度的第三外延子层，形成于第一共用外延子层与第二外延子层上，其中第一厚度大于第二厚度，且第二厚度大于第三厚度。
在一些实施例中，其中第一鳍状物与第二鳍状物包括硅锗应变材料。
在一些实施例中，外延堆叠位于第一间隔物与第二间隔物未覆盖的第一鳍状物与第二鳍状物的部分上。
在一些实施例中，第二间隔物比第一间隔物短。
在一些实施例中，在通道区顶部的渐变应力高于在通道区底部的渐变应力。
在一些实施例中，第一共用外延子层的锗浓度介于15％至35％之间、第二外延子层的锗浓度介于30％至65％之间、且第三外延子层的锗浓度介于40％至65％之间。
在一些实施例中，第一共用外延子层的硼掺质浓度介于1×1019原子/cm3至1×1020原子/cm3之间，第二外延子层的硼掺质浓度介于5×1019原子/cm3至2×1021原子/cm3之间，而第三外延子层的硼掺质浓度介于1×1020原子/cm3至2×1021原子/cm3之间。
上述实施例的特征有利于本技术领域中技术人员理解本发明实施例。本技术领域中技术人员应理解可采用本发明作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的和/或相同优点。本技术领域中技术人员亦应理解，这些等效置换并未脱离本发明构思与范围，并可在未脱离本发明的构思与范围的前提下进行改变、替换、或变动。

Claims (1)

1.一种半导体结构的形成方法，包括：
形成一或多个栅极结构于一鳍状物上，其中该鳍状物包括一鳍状物高度、一第一侧壁、以及与该第一侧壁对向的一第二侧壁；
形成一第一间隔物于该鳍状物的该第一侧壁上，并形成一第二间隔物于该鳍状物的该第二侧壁上；
蚀刻该鳍状物以降低所述栅极结构之间的该鳍状物高度；
蚀刻所述栅极结构之间的该第一间隔物与该第二间隔物，使蚀刻后的该第一间隔物比蚀刻后的该第二间隔物短，且蚀刻后的该第一间隔物与蚀刻后的该第二间隔物比蚀刻后的该鳍状物短；以及
形成一外延堆叠于所述栅极结构之间的蚀刻后的该鳍状物上。
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