CN109786316B - Semiconductor device, manufacturing method and electronic apparatus - Google Patents
Semiconductor device, manufacturing method and electronic apparatus Download PDFInfo
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- CN109786316B CN109786316B CN201711106055.0A CN201711106055A CN109786316B CN 109786316 B CN109786316 B CN 109786316B CN 201711106055 A CN201711106055 A CN 201711106055A CN 109786316 B CN109786316 B CN 109786316B
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Abstract
The invention provides a semiconductor device, a manufacturing method and an electronic device, which can reduce the thickness of an inorganic passivation layer above a first region and increase the thickness of an organic passivation layer above the first region, thereby reducing parasitic capacitance and improving device performance.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a semiconductor device, a manufacturing method, and an electronic apparatus.
Background
In an integrated circuit, many components need to be assembled on the same semiconductor substrate, the components need to be connected with each other by wiring, and the wiring density must be increased with the increase of the integration and the reduction of the feature size, so the surface passivation technology of the integrated circuit for electrical isolation between the components and between the wirings is very important. The surface passivation technology of the integrated circuit can isolate the components from the ambient atmosphere, enhance the blocking capability of the components to external ion contamination, control and stabilize the characteristics of the surface of the integrated circuit, and protect the circuit and internal wiring from mechanical and chemical damage. For example, the surface passivation of some capacitive sensors commonly found in touch devices (such as various smart products like mobile phones, tablet computers, wearable devices, and smart homes), fingerprint recognition devices, etc. is usually implemented by stacking three layers, i.e., a silicon dioxide layer, a silicon nitride layer, and a polyimide layer. However, because the surface passivation of the capacitive sensor adopts a lamination mode of three layers, namely a silicon dioxide layer, a silicon nitride layer and a polyimide layer, the internal parasitic capacitance of the capacitive sensor is large, and further, a sensing signal in the sensing region is easily influenced by the internal parasitic capacitance and becomes unstable in a transmission process, the performance of the capacitive sensor is reduced, and the sensing result of the capacitive sensor becomes inaccurate or even misjudged, so that the user experience is influenced.
Disclosure of Invention
The invention provides a semiconductor device, a manufacturing method and an electronic apparatus, which can reduce parasitic capacitance and improve device performance.
In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate having a first region and a second region, forming at least one layer of metal wiring on a surface of the semiconductor substrate in electrical communication with the first region and the second region;
covering an inorganic passivation layer on the surface of the metal wiring of the top layer;
removing part of the thickness of the inorganic passivation layer above the first region to form an opening;
and forming an organic passivation layer filled in the opening, wherein the upper surface of the organic passivation layer is not lower than that of the inorganic passivation layer above the second region.
Optionally, the inorganic passivation layer is a single layer or a stacked layer, and the material of the inorganic passivation layer is selected from at least one of an oxide, a nitride, an oxynitride, and an inorganic material including carbon as its main component.
Optionally, the material of the organic passivation layer is at least one selected from polyimide, epoxy resin, acrylic resin, polyamide-imide resin, polyvinyl alcohol, polyisobutylene, polyurethane elastic sponge, polyethylene terephthalate, polyvinyl butyral, polychloroprene, natural rubber, polyacrylonitrile, poly (bisphenol carbonate), polyvinyl chloride ether, polyvinylidene chloride, polystyrene, polyethylene, polypropylene, polyvinyl chloride, polydimethylsiloxane and polytetrafluoroethylene.
Optionally, the process of removing the inorganic passivation layer with a thickness of a portion above the first region and the process of forming the organic passivation layer filled in the opening both include a photolithography process, and the photolithography processes in the two processes are implemented by using the same photomask.
Optionally, the process of removing the inorganic passivation layer above the first region by a thickness of the inorganic passivation layer includes:
coating photoresist on the surface of the inorganic passivation layer;
photoetching the photoresist by using the photomask plate to form patterned photoresist exposing the surface of the inorganic passivation layer above the first region;
and etching and removing the exposed inorganic passivation layer with partial thickness by taking the patterned photoresist as a mask so as to form the opening.
Optionally, when the tone of the pattern of the photomask corresponding to the opening is a light-transmitting color, the photoresist is a positive photoresist; when the tone of the pattern of the photomask corresponding to the opening is an opaque dark color, the photoresist is a negative photoresist.
Optionally, the inorganic passivation layer includes a first inorganic passivation layer and a second inorganic passivation layer sequentially stacked on the surface of the metal wire on the top layer, the first inorganic passivation layer and the second inorganic passivation layer are made of different materials, and when a part of the exposed inorganic passivation layer is removed by etching, all the exposed second inorganic passivation layer and the first inorganic passivation layer below the second inorganic passivation layer are removed.
Optionally, a dry etching process is used to etch and remove a part of the exposed inorganic passivation layer to form the opening.
Optionally, the process of forming the organic passivation layer filled in the opening includes:
covering an organic passivation layer on the surface of the opening and the inorganic passivation layer, wherein the thickness of the organic passivation layer is larger than the depth of the opening;
photoetching or photoetching and etching the organic passivation layer by using the photomask plate to remove the organic passivation layer outside the opening region;
and curing the organic passivation layer in the opening area to form the organic passivation layer filled in the opening.
Optionally, the depth of the opening is 1.5 μm to 2 μm.
Optionally, the thickness of the inorganic passivation layer at the bottom of the opening is
The present invention also provides a semiconductor device comprising:
a semiconductor substrate having a first region and a second region;
at least one layer of metal wiring formed on the surface of the semiconductor substrate and used for electrically communicating the first region and the second region;
an inorganic passivation layer covering a surface of the metal wiring of the top layer and having an opening over the first region not exposing the surface of the metal wiring of the top layer;
and the organic passivation layer is filled in the opening, and the upper surface of the organic passivation layer is higher than the upper surface of the inorganic passivation layer above the second region.
Optionally, the inorganic passivation layer is a single layer or a stacked layer, and the material of the inorganic passivation layer is selected from at least one of an oxide, a nitride, an oxynitride, and an inorganic material including carbon as its main component.
Optionally, the material of the organic passivation layer is at least one selected from polyimide, epoxy resin, acrylic resin, polyamide-imide resin, polyvinyl alcohol, polyisobutylene, polyurethane elastic sponge, polyethylene terephthalate, polyvinyl butyral, polychloroprene, natural rubber, polyacrylonitrile, poly (bisphenol carbonate), polyvinyl chloride ether, polyvinylidene chloride, polystyrene, polyethylene, polypropylene, polyvinyl chloride, polydimethylsiloxane and polytetrafluoroethylene.
Optionally, the depth of the opening is 1.5 μm to 2 μm.
Optionally, the thickness of the inorganic passivation layer at the bottom of the opening is
Optionally, the semiconductor device is a capacitive sensor, the first region is a sensing region, and the second region is a logic region.
The present invention also provides an electronic device including the semiconductor device of one of the above.
Optionally, the electronic device is a touch device or a fingerprint recognition device.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. removing part of the inorganic passivation layer above the first region, and forming an opening for thickening the organic passivation layer, thereby thinning the inorganic passivation layer above the first region and thickening the organic passivation layer above the first region, so that the parasitic capacitance can be reduced, and the device performance can be improved;
2. the thickness of the organic passivation layer coated above the second area is not influenced, so that the photoetching effect of the organic passivation layer is not influenced, and the problems of scum and the like caused by the thicker overall coating thickness of the organic passivation layer can be avoided;
3. the same photomask may be used to define the etched regions of the inorganic passivation layer (i.e., the thinned regions) and the remaining regions of the organic passivation layer (i.e., the thickened regions), and thus, the photomask cost is not increased.
Drawings
FIG. 1 is a schematic cross-sectional view of a capacitive sensor;
FIG. 2 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention;
fig. 3A to 3E are schematic cross-sectional views of the device in the manufacturing method shown in fig. 2.
Detailed Description
As described in the background, the surface passivation of some capacitive sensors is often implemented by sequentially stacking a silicon dioxide layer, a silicon nitride layer and a polyimide layer, and particularly, referring to fig. 1, the capacitive sensor includes: a semiconductor substrate 100 having a sensing region I and a logic region II, a sensing electrode (which may be a pixel electrode), metal wirings (M1 to M3, TM), a silicon oxide layer 101, a silicon nitride layer 102, and a polyimide layer (polyimide) 103. Wherein, the silicon dioxide layer 101, the silicon nitride layer 102 and the polymer layer (polyimide)103 are sequentially laminated above the metal wiring TM to form a surface passivation structure, which can isolate the device from the surrounding atmosphere, prevent foreign matters from contaminating the device surface of the capacitive sensor, such as harmful impurity ions Na +, moisture, dust, etc., control and stabilize the electrical characteristics of the device surface, such as surface conductance and surface state, etc., protect the metal wiring inside the device and prevent the device from mechanical and chemical damage, and improve the stability and reliability of the device performance, specifically, the silicon dioxide layer 101 is in direct contact with the metal wiring TM, and is used for controlling and stabilizing the electrical properties of the chip surface of the capacitive sensor, controlling the fixed positive charge and reducing the surface recombination speed, so as to make the device stably work; the silicon nitride layer 102 is formed on the surface of the silicon dioxide layer 101, can absorb and block sodium ions and the like from diffusing to the substrate of the semiconductor substrate 100, has the functions of isolating and providing mechanical protection for metal wiring and end point metallization, is a barrier for impurity ions, and enables the surface of a device to have good mechanical properties; the polyimide layer 103 formed on the surface of the silicon nitride layer 102 enables better surface passivation protection and protects the metallization layer from mechanical scratches. In addition, the multiple sensing electrodes are arranged in the sensing region I and used for sensing object contact, such as finger touch and the like; the metal wirings M1-M3 and TM are sequentially stacked for connecting the sensing electrodes and the logic circuit in the logic region II, and transmitting the corresponding capacitance change (such as the capacitance change of a capacitor between the metal wiring TM and the skin of a human body) sensed by the sensing electrodes to the logic circuit in the logic region II, so that the logic circuit in the logic region II can determine specific user touch operation or human body biological information and the like according to the capacitance change Cfinger′＝Cpassivation+Cpolyimide+CfingerIn the formula, CpassivationA contact portion of a finger or the like with the sensing region I is formed of a silicon dioxide layerParasitic capacitance, C, generated by the silicon nitride layer 102 and the 101polyimideParasitic capacitance, C, generated by the polyimide layer 103 in the contact portion of the finger or the like with the sensing region IfingerThe contact capacitance generated for the contact of a finger or the like with the sensing region I.
In order to reduce the parasitic capacitance of the capacitive sensor and improve the accuracy of the sensing result, the thickness of the polyimide layer 103 coated on the surface of the silicon nitride layer 102 is usually increased, but the thicker polyimide layer affects the subsequent photolithography effect, resulting in scum and other problems.
Therefore, the invention provides a semiconductor device, a manufacturing method thereof and electronic equipment, which can increase the thickness of organic passivation layers such as a polyimide layer and the like and reduce the thickness of inorganic passivation layers such as silicon nitride, silicon oxide and the like, thereby reducing parasitic capacitance, simultaneously not influencing the photoetching effect of the organic passivation layers and ensuring the performance of the device.
The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.
Referring to fig. 2, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:
s1, providing a semiconductor substrate with a first area and a second area, and forming at least one layer of metal wiring which is electrically communicated with the first area and the second area on the surface of the semiconductor substrate;
s2, covering an inorganic passivation layer on the surface of the metal wiring of the top layer;
s3, removing the inorganic passivation layer with partial thickness above the first region to form an opening;
and S4, forming an organic passivation layer filled in the opening, wherein the upper surface of the organic passivation layer is higher than the upper surface of the inorganic passivation layer above the second region.
Referring to fig. 3A, in step S1, the semiconductor substrate 300 provided may be any semiconductor material known to those skilled in the art, which may include, but is not limited to: si (silicon), SiC (silicon carbide), SiGe (silicon germanium), SiGeC (silicon germanium carbide), Ge alloys, GeAs (germanium arsenic), InAs (indium arsenide), InP (indium phosphide) and other III-V or II-VI compound semiconductors. The semiconductor substrate 300 is not limited to bulk materials and may include epitaxial layers (e.g., epitaxial SiGe on Si substrates) or layered semiconductors such as silicon-on-insulator (SOI), SiGe-on-insulator (sgoi), and the like. The semiconductor substrate 300 includes various isolation structures for defining various device regions, which may include different structures and may be formed by different processing techniques. For example, the semiconductor substrate 300 includes a first region I and a second region II partitioned by a shallow trench isolation structure (not shown), wherein the first region I is a sensing region, and at least one sensing element (not shown) is formed in the first region I for sensing the presence and position of a touch of a finger, a stylus pen, or the like, or sensing an arbitrary finger fingerprint, etc.; the second area II is a logic area, and is configured to provide input signals for the components in the first area I and receive and process signals output by the components in the first area I, and in particular, can determine a corresponding touch operation or a fingerprint pattern according to a capacitance change sensed by the sensing elements in the first area I. In step S1, at least one layer of metal wiring 301 electrically connecting the first region I and the second region II may be formed on the surface of the semiconductor substrate 300 by a wiring technique such as a copper interconnection process, and the metal wiring 301 is simultaneously distributed over the first region I and the second region II. In this embodiment, a bottom metal wire M1, a middle metal wire Mx, and a top metal wire TM are sequentially formed on the surface of the semiconductor substrate 300, a metal interlayer dielectric 301a is filled between two adjacent metal wires, and the two adjacent metal wires are electrically connected through a conductive Via (Via) structure penetrating through the corresponding metal interlayer dielectric 301a, and the bottom metal wire M1 is electrically connected to corresponding components in the first area I and the second area II through corresponding conductive plugs (not shown), so as to achieve the electrical connection between the first area I and the second area II, so that the components in the second area II can provide corresponding input signals for the components in the first area I and receive and process signals output by the components in the first area I. The forming process of the metal wiring 301 is not the focus of the present invention, and will not be described herein again
Continuing to refer to fig. 3A, in step S2, sequentially depositing a first inorganic passivation layer 302a and a second inorganic passivation layer 302b on the surface of the top metal wiring TM and the exposed metal interlayer dielectric thereof to serve as inorganic passivation layers (passivation) of the present invention, wherein the first inorganic passivation layer 302a is in direct contact with the surface of the metal wiring TM, so as to control and stabilize the electrical properties of the device surface, control the positive charges and reduce the recombination velocity of the device surface, and enable the device to stably operate; the second inorganic passivation layer 302b can absorb and block impurities or contaminants such as sodium ions, water vapor, oxygen, dust, etc. from diffusing to the semiconductor substrate 300, and has the functions of isolating and providing mechanical protection for metal wiring and end point metallization, and is not only a barrier for impurity ions, but also a good mechanical property for the surface of the device. Specifically, the materials of the first and second inorganic passivation layers 302a and 302b may be respectively selected from at least one of an oxide, a nitride, an oxynitride, and an inorganic material including carbon as its main component, for example, the material of the first inorganic passivation layer 302a may be silicon dioxide (SiO)2) The second inorganic passivation layer 302b is made of a material different from the first inorganic passivation layer 302a, and may be Phosphorus Silicate Glass (PSG), silicon dioxide, silicon nitride (SiN), aluminum oxide (Al)2O3) Silicon nitride oxide (SiNO, composition ratio N > O), silicon oxynitride (SiON, composition ratio N < O), or an inorganic thin film material (diamond-like carbon DLC film, CN film, or the like) including carbon as its main component, and the like. Wherein the silicon dioxide is formed by a process selected from thermal oxidation, thermal decomposition deposition, chemical vapor deposition, sputtering, vacuum evaporation, anodization, epitaxial deposition, and the like, for example, using SiH silane4And oxygen as a reaction gas, and performing low temperature chemical vapor deposition at a reaction temperature of 250 to 500 ℃ to form silicon dioxide as a first inorganic passivation layer 302 a; the phosphosilicate glass (PSG) formation process may be low temperature chemical vapor deposition (e.g., by reacting phosphane PH3Addition to silane SiH4Chemical vapor deposition reaction process with oxygen), or, Si thermally grown at high temperatureO2Introducing phosphorus (P) -containing steam (for example, introducing a small amount of phosphorus oxychloride steam in the silicon thermal oxidation process); the silicon nitride may be formed by physical vapor deposition such as dc sputtering or rf sputtering, or by chemical vapor deposition such as Plasma Enhanced Chemical Vapor Deposition (PECVD). In other embodiments of the present invention, the inorganic passivation layer 302 is not limited to a stacked structure with a double layer, and may be a single-layer structure, or may be a stacked structure with three or more layers.
Referring to fig. 3A and 3B, in step S3, first, a photoresist is coated on a surface of the inorganic passivation layer 302 (i.e., the second inorganic passivation layer 302B), and the coated photoresist covers the first region I and the second region II; then, a series of photolithography processes such as exposure and development are performed on the coated photoresist by using a corresponding photomask 304, so as to form a patterned photoresist 303 exposing the surface of the inorganic passivation layer 302 (i.e., the second inorganic passivation layer 302b) above the first region I; then, with the patterned photoresist 303 as a mask, the exposed inorganic passivation layer is removed by etching with a dry etching process, that is, the inorganic passivation layer 302 above the first region I is thinned to form the opening 305, in this embodiment, since the inorganic passivation layer 302 is formed by laminating a first inorganic passivation layer 302a and a second inorganic passivation layer 302b, when the inorganic passivation layer 302 above the first region I is etched, the second inorganic passivation layer 302b above the first region I is completely removed and the first inorganic passivation layer 302a with most of the thickness is removed by etching, so as to form the opening 305 with a depth h1 of 1.5 μm to 2 μm, and the thickness h2 of the first inorganic passivation layer 302a at the bottom of the opening 305 remains with a thickness h2 of 1.5 μm to 2 μm
In addition, it should be noted that the photoresist applied in this step is selected to be negative or positive, depending on the tone of the pattern 304a of the photomask 304 used, because the negative photoresist forms insoluble matter upon illumination, and can replicate and transfer the pattern opposite to that on the photomask; the positive photoresist becomes soluble substances after being irradiated, and can copy and transfer the patterns same as the patterns on the photomask plate, so when the photomask plate 304 used in the step is the photomask plate used for manufacturing the organic passivation layer in the step S4, and the tone of the pattern 304a of the organic passivation layer corresponding to the photomask plate is a light-transmitting tone, that is, the tone of the pattern corresponding to the opening of the photomask plate is a light-transmitting tone, the photoresist coated in the step is a positive photoresist, after exposure treatment, the photoresist part above the first area I is irradiated with light and becomes soluble substances, and is removed through photolithography treatment such as development, and the photoresist above the second area II is not dissolved and is retained, thereby forming the patterned photoresist 303; when the photomask 304 used in this step is the photomask used in step S4 for manufacturing the organic passivation layer, and the tone of the pattern of the organic passivation layer corresponding to the photomask is an opaque tone (dark tone), that is, the tone of the pattern of the opening corresponding to the photomask 304a is an opaque tone, the photoresist is a negative photoresist, after exposure treatment, the photoresist portion above the second region II is illuminated and becomes an insoluble substance, and then the non-illuminated portion above the first region I is removed through photolithography treatment such as development, so that the patterned photoresist 303 is formed.
Referring to fig. 3C to 3E, in step S4, first, an organic passivation layer 306 with photosensitive characteristics (i.e., patterned directly by a photolithography process) is coated on the surface of the opening 305 and the surface of the inorganic passivation layer 302 by a spin coating process, etc., i.e., the coated organic passivation layer 306 covers the first inorganic passivation layer 302a over the first region I and the second inorganic passivation layer 302b over the second region II, the organic passivation layer 306 is coated to a thickness sufficient to fill the opening 305, and the top of the organic passivation layer 306 over the first region I is higher than the top of the second inorganic passivation layer 302b over the second region II; then, photoetching the coated organic passivation layer 306 by using a mask 304, and removing the organic passivation layer part in the second region II while reserving the organic passivation layer 306a above the first region I; then, the organic passivation layer 306a above the first region I (i.e., in the region of the opening 305 of fig. 3B) is cured to densify the organic passivation layer 306a, so as to form an organic passivation layer 306B filled in the opening 305. The upper surface of the organic passivation layer 306b is higher than the upper surface of the inorganic passivation layer 302 (i.e., the upper surface of the second inorganic passivation layer 302b) over the second region II.
It should be noted that the material of the organic passivation layer 306 coated in this step may also be non-photosensitive and cannot be directly patterned by photolithography processes such as exposure and development, and at this time, a layer of photoresist needs to be formed on the surface of the organic passivation layer 306 coated first, and the material property (i.e., positive or negative) of the photoresist is opposite to the material property of the photoresist used in forming the opening 305 in step S3, and then the mask plate 304 is used to perform photolithography on the photoresist formed again to form a photoresist mask layer; then, the coated organic passivation layer 306 is etched by using the photoresist mask layer as a mask through a dry etching process or the like, so as to remove the organic passivation layer above the second region II and leave the organic passivation layer 306a above the first region I, and then the organic passivation layer 306a above the first region I (i.e., in the region of the opening 305 in fig. 3B) may be cured to densify the organic passivation layer 306a, so as to form the organic passivation layer 306B filled in the opening 305.
Alternatively, the material of the organic passivation layer 306 applied in step S4 may be selected from at least one of polyimide, epoxy resin, acrylic resin, polyamide-imide resin, polyvinyl alcohol, polyisobutylene, polyurethane elastic sponge, polyethylene terephthalate, polyvinyl butyral, polychloroprene, natural rubber, polyacrylonitrile, poly bisphenol carbonate, polyvinyl chloride ether, polyvinylidene chloride, polystyrene, polyethylene, polypropylene, polyvinyl chloride, polydimethylsiloxane, and polytetrafluoroethylene.
Referring to fig. 3E, in the organic passivation layer 306b formed in step S4, compared with the organic passivation layer 103 shown in fig. 1, the thickness of the inorganic passivation layer 302 at the bottom of the organic passivation layer 306b is smaller, and the lower surface of the organic passivation layer 306 is equivalent to being recessed in the inorganic passivation layer 302, and the upper surface can at least maintain the same height as the organic passivation layer 103, that is, the organic passivation layer 306b is increased by at least the reduced thickness of the inorganic passivation layer 302 in the first region I relative to the organic passivation layer 103, so that the parasitic capacitance of the formed semiconductor device is greatly reduced, and the performance is greatly improved.
In view of the above, in the manufacturing method of the semiconductor device of the present invention, firstly, the inorganic passivation layer with a partial thickness above the first region is removed, that is, the inorganic passivation layer above the first region is thinned, and simultaneously, the organic passivation layer is formed on the surface of the inorganic passivation layer above the first region, and the upper surface of the organic passivation layer is higher than the upper surface of the inorganic passivation layer above the second region, that is, the thickness of the organic passivation layer is increased, so that the parasitic capacitance can be reduced, and the device performance can be improved; secondly, the thickness of the organic passivation layer coated above the second area is not affected, so that the photoetching effect of the organic passivation layer is not affected, and the problems of scum and the like are avoided; in addition, the same photomask can be used to define the etched area of the inorganic passivation layer and the reserved area of the organic passivation layer, so the cost of the photomask is not increased. The manufacturing method of the semiconductor device has the advantages of simple process and low cost, can reduce parasitic capacitance generated by surface passivation, improves the performance of the device, and is suitable for manufacturing capacitive sensors such as touch sensors, fingerprint identification sensors and the like.
Referring to fig. 3E, the present invention further provides a semiconductor device, including: a semiconductor substrate 300 having a first region I and a second region II, at least one metal wiring 301, an inorganic passivation layer 302, and an organic passivation layer 306 b.
The metal wiring 301 is used for electrically connecting corresponding components in the first region I and the second region II, and may be a multilayer laminated structure (i.e., a multilayer metal interconnection structure) sequentially formed on the surface of the semiconductor substrate, for example, the multilayer laminated structure includes a bottom metal wiring M1, a middle metal wiring Mx, and a top metal wiring TM, a metal interlayer medium 301a is filled between two adjacent metal wirings, the two adjacent metal wirings are electrically connected through a conductive via structure, and the bottom metal wiring M1 is electrically connected with corresponding components in the first region I and the second region II through corresponding conductive plugs.
Inorganic substanceThe passivation layer 302 covers the surface of the metal wiring TM of the top layer, and may have a single-layer structure or a stacked-layer structure, and a material thereof may be selected from at least one of an oxide, a nitride, an oxynitride, and an inorganic material including carbon as its main component. And an opening (not shown) which does not expose the upper surface of the metal wire TM of the top layer is formed above the first region I, the opening may have a depth of 1.5 μm to 2 μm, and the inorganic passivation layer 302 at the bottom of the opening may have a thickness of 1.5 μm to 2 μm
For example, in the present embodiment, the inorganic passivation layer 302 includes a stacked layer structure formed by sequentially stacking a first inorganic passivation layer 302a and a second inorganic passivation layer 302b, the first inorganic passivation layer 302a covers the first region I and the second region II, and the thickness of the first inorganic passivation layer 302a above the first region I (may be a thickness of the first inorganic passivation layer 302a above the first region I)
) Less than its thickness over the second region II to form the opening, the second inorganic passivation layer 302b covers only the surface of the first inorganic passivation layer 302a over the second region II.
The organic passivation layer 306b is filled in the opening, i.e., the organic passivation layer 306b is only located above the first region I, and the upper surface of the organic passivation layer 306b is higher than the upper surface of the inorganic passivation layer 302 (i.e., the upper surface of the second inorganic passivation layer 302b) above the second region II. The organic passivation layer 306b is used as a part of the surface passivation, which can relieve the stress generated by the inorganic passivation layer 302, prevent the inorganic passivation layer 302 from peeling or cracking, and further improve the pollutant blocking effect. The material of the organic passivation layer 306b may be selected from at least one of polyimide, epoxy resin, acrylic resin, polyamide-imide resin, polyvinyl alcohol, polyisobutylene, polyurethane elastic sponge, polyethylene terephthalate, polyvinyl butyral, polychloroprene, natural rubber, polyacrylonitrile, poly (bisphenol carbonate), polychlorinated ether, polyvinylidene chloride, polystyrene, polyethylene, polypropylene, polyvinyl chloride, polydimethylsiloxane, and polytetrafluoroethylene. For reasons of space and not exhaustive description, and only a few specific polymeric materials are listed herein for reference, it will be apparent that these specific materials are not limiting to the scope of the invention, since other similar materials will be readily selected by those skilled in the art based on the triboelectric properties of these materials, as taught by the present invention.
The semiconductor device of the present invention may be a capacitive sensor such as a touch sensor or a fingerprint sensor, in which case, the first region I may be a sensing region for sensing touch or a fingerprint, and the second region II may be a logic region for inputting signals to devices (including sensing electrodes) in the first region I and receiving and processing output signals of the devices in the first region I.
In addition, the invention also provides electronic equipment which comprises the semiconductor device, wherein the electronic equipment is touch equipment or fingerprint identification equipment.
In the semiconductor device and the electronic apparatus of the present invention, the inorganic passivation layer above the first region is thinner than the inorganic passivation layer above the second region, and the height difference between the inorganic passivation layers in the two regions increases the thickness of the organic passivation layer, thereby greatly reducing the parasitic capacitance and improving the device performance.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (16)
1. A method of manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate having a first region and a second region, forming at least one layer of metal wiring on a surface of the semiconductor substrate in electrical communication with the first region and the second region;
covering an inorganic passivation layer on the surface of the metal wiring of the top layer;
removing part of the thickness of the inorganic passivation layer above the first region to form an opening;
forming an organic passivation layer filled in the opening, wherein the upper surface of the organic passivation layer is higher than the upper surface of the inorganic passivation layer above the second region;
in the manufacturing method of the semiconductor device, the process of removing the inorganic passivation layer with the thickness of the part above the first area and the process of forming the organic passivation layer filled in the opening both comprise a photoetching process, and the photoetching processes in the two processes are realized by using the same photomask.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the inorganic passivation layer is a single layer or a stacked layer, and a material of the inorganic passivation layer is at least one selected from an oxide, a nitride, an oxynitride, and an inorganic material including carbon as its main component.
3. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the organic passivation layer is at least one selected from the group consisting of polyimide, epoxy resin, acrylic resin, polyamide-imide resin, polyvinyl alcohol, polyisobutylene, polyurethane elastic sponge, polyethylene terephthalate, polyvinyl butyral, polychloroprene, natural rubber, polyacrylonitrile, poly (bisphenol carbonate), polychlorinated ether, polyvinylidene chloride, polystyrene, polyethylene, polypropylene, polyvinyl chloride, polydimethylsiloxane, and polytetrafluoroethylene.
4. The method of manufacturing a semiconductor device according to claim 1, wherein the process of removing the partial thickness of the inorganic passivation layer over the first region comprises:
coating photoresist on the surface of the inorganic passivation layer;
photoetching the photoresist by using the photomask plate to form patterned photoresist exposing the surface of the inorganic passivation layer above the first region;
and etching and removing the exposed inorganic passivation layer with partial thickness by taking the patterned photoresist as a mask so as to form the opening.
5. The method for manufacturing a semiconductor device according to claim 4, wherein when the tone of the pattern of the photomask corresponding to the opening is a light transmissive color, the photoresist is a negative photoresist; when the tone of the pattern of the photomask corresponding to the opening is an opaque dark color, the photoresist is a positive photoresist.
6. The method of manufacturing a semiconductor device according to claim 4, wherein the inorganic passivation layer comprises a first inorganic passivation layer and a second inorganic passivation layer sequentially stacked on the surface of the metal wire of the top layer, the first inorganic passivation layer and the second inorganic passivation layer are made of different materials, and when a partial thickness of the exposed inorganic passivation layer is removed by etching, all of the exposed second inorganic passivation layer and a partial thickness of the first inorganic passivation layer are removed.
7. The method for manufacturing a semiconductor device according to claim 4, wherein the opening is formed by etching and removing a part of the thickness of the exposed inorganic passivation layer by using a dry etching process.
8. The method for manufacturing a semiconductor device according to claim 4, wherein the process of forming the organic passivation layer filled in the opening comprises:
covering an organic passivation layer on the surface of the opening and the inorganic passivation layer, wherein the thickness of the organic passivation layer is larger than the depth of the opening;
photoetching or photoetching and etching the organic passivation layer by using the photomask plate to remove the organic passivation layer outside the opening region;
and curing the organic passivation layer in the opening area to form the organic passivation layer filled in the opening.
9. The method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein a depth of the opening is 1.5 μm to 2 μm; and/or the thickness of the inorganic passivation layer at the bottom of the opening is
10. A semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 1 to 9, comprising:
a semiconductor substrate having a first region and a second region;
at least one layer of metal wiring formed on the surface of the semiconductor substrate and used for electrically communicating the first region and the second region;
an inorganic passivation layer covering a surface of the metal wiring of the top layer and having an opening over the first region that does not expose the surface of the metal wiring of the top layer;
and the organic passivation layer is filled in the opening, and the upper surface of the organic passivation layer is higher than the upper surface of the inorganic passivation layer above the second region.
11. The semiconductor device according to claim 10, wherein the inorganic passivation layer is a single layer or a stacked layer, and a material of the inorganic passivation layer is selected from at least one of an oxide, a nitride, an oxynitride, and an inorganic material including carbon as its main component.
12. The semiconductor device according to claim 10, wherein a material of the organic passivation layer is at least one selected from the group consisting of polyimide, epoxy resin, acrylic resin, polyamide-imide resin, polyvinyl alcohol, polyisobutylene, polyurethane elastic sponge, polyethylene terephthalate, polyvinyl butyral, polychloroprene, natural rubber, polyacrylonitrile, poly (bisphenol carbonate), polychlorinated ether, polyvinylidene chloride, polystyrene, polyethylene, polypropylene, polyvinyl chloride, polydimethylsiloxane, and polytetrafluoroethylene.
13. The semiconductor device according to claim 10, wherein a depth of the opening is 1.5 μm to 2 μm; and/or the thickness of the inorganic passivation layer at the bottom of the opening is
14. The semiconductor device according to any one of claims 10 to 13, wherein the semiconductor device is a capacitive sensor, the first region is a sensing region, and the second region is a logic region.
15. An electronic device characterized by comprising the semiconductor device according to any one of claims 10 to 14.
16. The electronic device of claim 15, wherein the electronic device is a touch device or a fingerprint recognition device.
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| CN104269417A (en) * | 2014-07-04 | 2015-01-07 | 友达光电股份有限公司 | Pixel Array Substrate And Panel |
| CN104736983A (en) * | 2012-10-17 | 2015-06-24 | 株式会社鹭宫制作所 | Pressure sensor, and sensor unit provided with same |
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